[ARM] Allow Usage of R4-R5 as Global Register Variables for ARM

[anwel]

Summary

This patch is an extension of an earlier patch introducing support for r6-r11 (https://reviews.llvm.org/D68862). Here we replace the former hard-coded use of r4 as a scratch register in some parts of the ARM backend, and deal with the cases where r4 and r5 are used as input registers to segmented stack routines (e.g. __chkstk).

Reserving r4 or r5 with segmented stacks is realized by temporarily storing the contents of these registers in free scratch registers, so is subject to a small performance impact (i.e., two additional mov instructions per register). This is only supported on targets where ARMv6 instructions are available.

clang/docs/ClangCommandLineReference.rst

 Wavefront size 64 is used if enabled and wavefront size 32 if disabled (AMDGPU only)
 
 .. option:: -mxnack, -mno-xnack
 
 Enable XNACK (AMDGPU only)
 
 ARM
 ---
+.. option:: -ffixed-r4
+
+Reserve the r4 register (ARM only)
+
+.. option:: -ffixed-r5
+
+Reserve the r5 register (ARM only)
 
 .. option:: -ffixed-r6
 
 Reserve the r6 register (ARM only)
 
 .. option:: -ffixed-r7
 
 Reserve the r7 register (ARM only)

clang/include/clang/Driver/Options.td

 def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (same as mno-unaligned-access)">;
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>;
 def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Disallow generation of deprecated IT blocks for ARMv8. It is on by default for ARMv8 Thumb mode.">;
 def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Allow generation of deprecated IT blocks for ARMv8. It is off by default for ARMv8 Thumb mode">;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
-foreach i = {6-11} in
+foreach i = {4-11} in
   def ffixed_r#i : Flag<["-"], "ffixed-r"#i>, Group<m_arm_Features_Group>,
     HelpText<"Reserve the r"#i#" register (ARM only)">;
 def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of movt/movw pairs (ARM only)">;
 def mcrc : Flag<["-"], "mcrc">, Group<m_Group>,
   HelpText<"Allow use of CRC instructions (ARM/Mips only)">;
 def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of CRC instructions (ARM only)">;

clang/lib/Driver/ToolChains/Arch/ARM.cpp

if (Args.hasArg(RestrictFPOpt)) {
     D.Diag(diag::err_reserved_frame_pointer)
         << OptStr << OptStr.substr(SubStrIndex);
   }
 
 // Reservation of general purpose registers.
 #define HANDLE_FFIXED_R(n) \
   if (Args.hasArg(options::OPT_ffixed_r##n)) \
     Features.push_back("+reserve-r" #n)
+  HANDLE_FFIXED_R(4);
+  HANDLE_FFIXED_R(5);
   HANDLE_FFIXED_R(6);
   HANDLE_FFIXED_R(7);
   HANDLE_FFIXED_R(8);
   HANDLE_FFIXED_R(9);
   HANDLE_FFIXED_R(10);
   HANDLE_FFIXED_R(11);
 
   // The kext linker doesn't know how to deal with movw/movt.

llvm/lib/Target/ARM/ARM.td

def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
                                              "Generate calls via indirect call "
                                              "instructions">;
 
 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
                                              "GenExecuteOnly", "true",
                                              "Enable the generation of "
                                              "execute only code.">;
 
-foreach i = {6-11} in
+foreach i = {4-11} in
     def FeatureReserveR#i : SubtargetFeature<"reserve-r"#i,
                                              "ReservedGPRegisters["#i#"]", "true",
                                              "Reserve R"#i#", making it "
                                              "unavailable as a GPR">;
 
 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
                                              "Don't use movt/movw pairs for "
                                              "32-bit imms">;

llvm/lib/Target/ARM/ARMFrameLowering.h

 //===- ARMTargetFrameLowering.h - Define frame lowering for ARM -*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
 #define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
 
+#include "llvm/ADT/BitVector.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include <vector>
 
 namespace llvm {
 
 class ARMSubtarget;
 class CalleeSavedInfo;
bool enableShrinkWrapping(const MachineFunction &MF) const override {
     return true;
   }
   bool isProfitableForNoCSROpt(const Function &F) const override {
     // The no-CSR optimisation is bad for code size on ARM, because we can save
     // many registers with a single PUSH/POP pair.
     return false;
   }
 
+  // Return a non-reserved general purpose register that can be used as scratch
+  // register
+  unsigned getScratchRegister(const MachineFunction &MF,
+                              BitVector inUse = BitVector()) const;
+
 private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,
                     unsigned StrOpc, bool NoGap,
                     bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs,
                     unsigned MIFlags = 0) const;
   void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                    std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc,

llvm/lib/Target/ARM/ARMFrameLowering.cpp

 using namespace llvm;
 
 static cl::opt<bool>
 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
                      cl::desc("Align ARM NEON spills in prolog and epilog"));
 
 static MachineBasicBlock::iterator
 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
-                        unsigned NumAlignedDPRCS2Regs);
+                        unsigned NumAlignedDPRCS2Regs, unsigned ScratchReg);
 
 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
     : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, Align(4)),
       STI(sti) {}
 
 bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const {
   // iOS always has a FP for backtracking, force other targets to keep their FP
   // when doing FastISel. The emitted code is currently superior, and in cases
bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
   // address the stack frame. So a large call frame can cause poor codegen
   // and may even makes it impossible to scavenge a register.
   if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
     return false;
 
   return !MFI.hasVarSizedObjects();
 }
 
+// Decide which register out of r4-r11 can be used as a scratch register, based
+// on whether they're free according to RegisterInfo and not excluded by inUse
+unsigned ARMFrameLowering::getScratchRegister(const MachineFunction &MF,
+                                              BitVector InUse) const {
+  bool HasFP = hasFP(MF);
+  unsigned R4 = ARM::R4 - ARM::GPRRegClass.begin()[0];
+  for (unsigned i = R4; i < ARM::GPRRegClass.getNumRegs() - R4; i++) {
+    if (!STI.isGPRegisterReserved(i) &&
+        !((InUse.size() >= i && InUse[i]) ||
+          (HasFP &&
+           i == STI.getInstrInfo()->getRegisterInfo().getFrameRegister(MF)))) {
+      return ARM::GPRRegClass.getRegister(i);
+    }
+  }
+  report_fatal_error("ran out of registers: Too many registers reserved");
+  return ARM::NoRegister;
+}
+
 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
 /// call frame pseudos can be simplified.  Unlike most targets, having a FP
 /// is not sufficient here since we still may reference some objects via SP
 /// even when FP is available in Thumb2 mode.
 bool
 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
   return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects();
 }
if (DPRCSSize > 0) {
     while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
       DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
       LastPush = MBBI++;
     }
   }
 
   // Move past the aligned DPRCS2 area.
   if (AFI->getNumAlignedDPRCS2Regs() > 0) {
-    MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
+    MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs(),
+                                   getScratchRegister(MF));
     // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
     // leaves the stack pointer pointing to the DPRCS2 area.
     //
     // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
     NumBytes += MFI.getObjectOffset(D8SpillFI);
   } else
     NumBytes = DPRCSOffset;
 
   if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
+    // r4 might be used as global named register, which means its value has not
+    // been and must not be saved to the stack. Thus temporarily save its
+    // content in another register so r4 is free to be used for __chkstk
+    unsigned BackupR4 = ARM::NoRegister;
+    if (STI.isGPRegisterReserved(ARM::R4 - ARM::GPRRegClass.begin()[0])) {
+      if (!STI.hasV6Ops())
+        // Do not allow r4 to be reserved if segmented stacks are used on a
+        // target where 'mov low_reg, low_reg' is not possible
+        report_fatal_error("-ffixed-r4 is not allowed for this target when "
+                           "segmented stacks are in use.");
+      BackupR4 = getScratchRegister(MF);
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BackupR4)
+          .addReg(ARM::R4)
+          .add(predOps(ARMCC::AL));
+    }
+
     uint32_t NumWords = NumBytes >> 2;
 
     if (NumWords < 65536)
       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
           .addImm(NumWords)
           .setMIFlags(MachineInstr::FrameSetup)
           .add(predOps(ARMCC::AL));
     else
if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
 
     BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
         .addReg(ARM::SP, RegState::Kill)
         .addReg(ARM::R4, RegState::Kill)
         .setMIFlags(MachineInstr::FrameSetup)
         .add(predOps(ARMCC::AL))
         .add(condCodeOp());
     NumBytes = 0;
+
+    // If r4 is actually a fixed register, restore it
+    if (BackupR4) {
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
+          .addReg(BackupR4)
+          .add(predOps(ARMCC::AL));
+    }
   }
 
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
     if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
         tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
       DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
     else {
void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   // realigned.
   if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
     unsigned MaxAlign = MFI.getMaxAlignment();
     assert(!AFI->isThumb1OnlyFunction());
     if (!AFI->isThumbFunction()) {
       emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
                                false);
     } else {
-      // We cannot use sp as source/dest register here, thus we're using r4 to
-      // perform the calculations. We're emitting the following sequence:
+      // We cannot use sp as source/dest register here, thus we're using a
+      // scratch register to perform the calculations. We're emitting the
+      // following sequence (ex.: scratchReg=r4):
       // mov r4, sp
       // -- use emitAligningInstructions to produce best sequence to zero
       // -- out lower bits in r4
       // mov sp, r4
-      // FIXME: It will be better just to find spare register here.
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
+      unsigned ScratchReg = getScratchRegister(MF);
+      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ScratchReg)
           .addReg(ARM::SP, RegState::Kill)
           .add(predOps(ARMCC::AL));
-      emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
-                               false);
+      emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ScratchReg,
+                               MaxAlign, false);
       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
-          .addReg(ARM::R4, RegState::Kill)
+          .addReg(ScratchReg, RegState::Kill)
           .add(predOps(ARMCC::AL));
     }
 
     AFI->setShouldRestoreSPFromFP(true);
   }
 
   // If we need a base pointer, set it up here. It's whatever the value
   // of the stack pointer is at this point. Any variable size objects
if (AFI->shouldRestoreSPFromFP()) {
                                   ARMCC::AL, 0, TII);
         else {
           // It's not possible to restore SP from FP in a single instruction.
           // For iOS, this looks like:
           // mov sp, r7
           // sub sp, #24
           // This is bad, if an interrupt is taken after the mov, sp is in an
           // inconsistent state.
-          // Use the first callee-saved register as a scratch register.
-          assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
+          // Use the scratch register.
+          unsigned ScratchReg = getScratchRegister(MF);
+          assert(!MFI.getPristineRegs(MF).test(ScratchReg) &&
                  "No scratch register to restore SP from FP!");
-          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
+          emitT2RegPlusImmediate(MBB, MBBI, dl, ScratchReg, FramePtr, -NumBytes,
                                  ARMCC::AL, 0, TII);
           BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
-              .addReg(ARM::R4)
+              .addReg(ScratchReg)
               .add(predOps(ARMCC::AL));
         }
       } else {
         // Thumb2 or ARM.
         if (isARM)
           BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
               .addReg(FramePtr)
               .add(predOps(ARMCC::AL))

 
 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
 /// starting from d8.  Also insert stack realignment code and leave the stack
 /// pointer pointing to the d8 spill slot.
 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator MI,
                                     unsigned NumAlignedDPRCS2Regs,
                                     const std::vector<CalleeSavedInfo> &CSI,
-                                    const TargetRegisterInfo *TRI) {
+                                    const TargetRegisterInfo *TRI,
+                                    unsigned ScratchReg) {
   MachineFunction &MF = *MBB.getParent();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
 
   // Mark the D-register spill slots as properly aligned.  Since MFI computes
   // stack slot layout backwards, this can actually mean that the d-reg stack
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     // computes all offsets relative to the incoming stack pointer which is a
     // bit weird when realigning the stack.  Any extra padding for this
     // over-alignment is not realized because the code inserted below adjusts
     // the stack pointer by numregs * 8 before aligning the stack pointer.
     if (DNum == 0)
       MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
   }
 
-  // Move the stack pointer to the d8 spill slot, and align it at the same
-  // time. Leave the stack slot address in the scratch register r4.
+  // Move the stack pointer to the d8 spill slot, and align it at the same time.
+  // Leave the stack slot address in the scratch register. (ex.: scratchReg=r4)
   //
   //   sub r4, sp, #numregs * 8
   //   bic r4, r4, #align - 1
   //   mov sp, r4
   //
   bool isThumb = AFI->isThumbFunction();
   assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
   AFI->setShouldRestoreSPFromFP(true);
 
   // sub r4, sp, #numregs * 8
   // The immediate is <= 64, so it doesn't need any special encoding.
   unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
-  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
+  BuildMI(MBB, MI, DL, TII.get(Opc), ScratchReg)
       .addReg(ARM::SP)
       .addImm(8 * NumAlignedDPRCS2Regs)
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
 
   unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
   // We must set parameter MustBeSingleInstruction to true, since
   // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
   // stack alignment.  Luckily, this can always be done since all ARM
   // architecture versions that support Neon also support the BFC
   // instruction.
-  emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
+  emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ScratchReg, MaxAlign,
+                           true);
 
   // mov sp, r4
   // The stack pointer must be adjusted before spilling anything, otherwise
   // the stack slots could be clobbered by an interrupt handler.
-  // Leave r4 live, it is used below.
+  // Leave scratch register live, it is used below.
   Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
-                                .addReg(ARM::R4)
+                                .addReg(ScratchReg)
                                 .add(predOps(ARMCC::AL));
   if (!isThumb)
     MIB.add(condCodeOp());
 
   // Now spill NumAlignedDPRCS2Regs registers starting from d8.
-  // r4 holds the stack slot address.
+  // The scratch register holds the stack slot address.
   unsigned NextReg = ARM::D8;
 
   // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
   // The writeback is only needed when emitting two vst1.64 instructions.
   if (NumAlignedDPRCS2Regs >= 6) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QQPRRegClass);
     MBB.addLiveIn(SupReg);
-    BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
-        .addReg(ARM::R4, RegState::Kill)
+    BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ScratchReg)
+        .addReg(ScratchReg, RegState::Kill)
         .addImm(16)
         .addReg(NextReg)
         .addReg(SupReg, RegState::ImplicitKill)
         .add(predOps(ARMCC::AL));
     NextReg += 4;
     NumAlignedDPRCS2Regs -= 4;
   }
 
-  // We won't modify r4 beyond this point.  It currently points to the next
-  // register to be spilled.
+  // We won't modify the scratch register beyond this point. It currently points
+  // to the next register to be spilled.
   unsigned R4BaseReg = NextReg;
 
   // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
   if (NumAlignedDPRCS2Regs >= 4) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QQPRRegClass);
     MBB.addLiveIn(SupReg);
     BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
-        .addReg(ARM::R4)
+        .addReg(ScratchReg)
         .addImm(16)
         .addReg(NextReg)
         .addReg(SupReg, RegState::ImplicitKill)
         .add(predOps(ARMCC::AL));
     NextReg += 4;
     NumAlignedDPRCS2Regs -= 4;
   }
 
   // 16-byte aligned vst1.64 with 2 d-regs.
   if (NumAlignedDPRCS2Regs >= 2) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QPRRegClass);
     MBB.addLiveIn(SupReg);
     BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
-        .addReg(ARM::R4)
+        .addReg(ScratchReg)
         .addImm(16)
         .addReg(SupReg)
         .add(predOps(ARMCC::AL));
     NextReg += 2;
     NumAlignedDPRCS2Regs -= 2;
   }
 
   // Finally, use a vanilla vstr.64 for the odd last register.
   if (NumAlignedDPRCS2Regs) {
     MBB.addLiveIn(NextReg);
     // vstr.64 uses addrmode5 which has an offset scale of 4.
     BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
         .addReg(NextReg)
-        .addReg(ARM::R4)
+        .addReg(ScratchReg)
         .addImm((NextReg - R4BaseReg) * 2)
         .add(predOps(ARMCC::AL));
   }
 
-  // The last spill instruction inserted should kill the scratch register r4.
-  std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
+  // The last spill instruction inserted should kill the scratch register.
+  std::prev(MI)->addRegisterKilled(ScratchReg, TRI);
 }
 
 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
 /// iterator to the following instruction.
 static MachineBasicBlock::iterator
 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
-                        unsigned NumAlignedDPRCS2Regs) {
+                        unsigned NumAlignedDPRCS2Regs, unsigned ScratchReg) {
   //   sub r4, sp, #numregs * 8
   //   bic r4, r4, #align - 1
   //   mov sp, r4
+  //   (ex.: scratchReg=r4)
   ++MI; ++MI; ++MI;
   assert(MI->mayStore() && "Expecting spill instruction");
 
   // These switches all fall through.
   switch(NumAlignedDPRCS2Regs) {
   case 7:
     ++MI;
     assert(MI->mayStore() && "Expecting spill instruction");
     LLVM_FALLTHROUGH;
   default:
     ++MI;
     assert(MI->mayStore() && "Expecting spill instruction");
     LLVM_FALLTHROUGH;
   case 1:
   case 2:
   case 4:
-    assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
+    assert(MI->killsRegister(ScratchReg) && "Missed kill flag");
     ++MI;
   }
   return MI;
 }
 
 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
 /// starting from d8.  These instructions are assumed to execute while the
 /// stack is still aligned, unlike the code inserted by emitPopInst.
 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
                                       MachineBasicBlock::iterator MI,
                                       unsigned NumAlignedDPRCS2Regs,
                                       const std::vector<CalleeSavedInfo> &CSI,
-                                      const TargetRegisterInfo *TRI) {
+                                      const TargetRegisterInfo *TRI,
+                                      unsigned ScratchReg) {
   MachineFunction &MF = *MBB.getParent();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
 
   // Find the frame index assigned to d8.
   int D8SpillFI = 0;
   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
     if (CSI[i].getReg() == ARM::D8) {
       D8SpillFI = CSI[i].getFrameIdx();
       break;
     }
 
-  // Materialize the address of the d8 spill slot into the scratch register r4.
+  // Materialize the address of the d8 spill slot into the scratch register.
   // This can be fairly complicated if the stack frame is large, so just use
   // the normal frame index elimination mechanism to do it.  This code runs as
   // the initial part of the epilog where the stack and base pointers haven't
   // been changed yet.
   bool isThumb = AFI->isThumbFunction();
   assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
 
   unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
-  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
+  BuildMI(MBB, MI, DL, TII.get(Opc), ScratchReg)
       .addFrameIndex(D8SpillFI)
       .addImm(0)
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
 
   // Now restore NumAlignedDPRCS2Regs registers starting from d8.
   unsigned NextReg = ARM::D8;
 
   // 16-byte aligned vld1.64 with 4 d-regs and writeback.
   if (NumAlignedDPRCS2Regs >= 6) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QQPRRegClass);
     BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
-        .addReg(ARM::R4, RegState::Define)
-        .addReg(ARM::R4, RegState::Kill)
+        .addReg(ScratchReg, RegState::Define)
+        .addReg(ScratchReg, RegState::Kill)
         .addImm(16)
         .addReg(SupReg, RegState::ImplicitDefine)
         .add(predOps(ARMCC::AL));
     NextReg += 4;
     NumAlignedDPRCS2Regs -= 4;
   }
 
-  // We won't modify r4 beyond this point.  It currently points to the next
-  // register to be spilled.
+  // We won't modify the scratch register beyond this point. It currently points
+  // to the next register to be spilled.
   unsigned R4BaseReg = NextReg;
 
   // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
   if (NumAlignedDPRCS2Regs >= 4) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QQPRRegClass);
     BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
-        .addReg(ARM::R4)
+        .addReg(ScratchReg)
         .addImm(16)
         .addReg(SupReg, RegState::ImplicitDefine)
         .add(predOps(ARMCC::AL));
     NextReg += 4;
     NumAlignedDPRCS2Regs -= 4;
   }
 
   // 16-byte aligned vld1.64 with 2 d-regs.
   if (NumAlignedDPRCS2Regs >= 2) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QPRRegClass);
     BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
-        .addReg(ARM::R4)
+        .addReg(ScratchReg)
         .addImm(16)
         .add(predOps(ARMCC::AL));
     NextReg += 2;
     NumAlignedDPRCS2Regs -= 2;
   }
 
   // Finally, use a vanilla vldr.64 for the remaining odd register.
   if (NumAlignedDPRCS2Regs)
     BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
-        .addReg(ARM::R4)
+        .addReg(ScratchReg)
         .addImm(2 * (NextReg - R4BaseReg))
         .add(predOps(ARMCC::AL));
 
-  // Last store kills r4.
-  std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
+  // Last store kills the scratch register.
+  std::prev(MI)->addRegisterKilled(ScratchReg, TRI);
 }
 
 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         const std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
                MachineInstr::FrameSetup);
   emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
                NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
 
   // The code above does not insert spill code for the aligned DPRCS2 registers.
   // The stack realignment code will be inserted between the push instructions
   // and these spills.
   if (NumAlignedDPRCS2Regs)
-    emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
+    emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI,
+                            getScratchRegister(MF));
 
   return true;
 }
 
 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   MachineFunction &MF = *MBB.getParent();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   bool isVarArg = AFI->getArgRegsSaveSize() > 0;
   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
 
   // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
   // registers. Do that here instead.
   if (NumAlignedDPRCS2Regs)
-    emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
+    emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI,
+                              getScratchRegister(MF));
 
   unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
   unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
   unsigned FltOpc = ARM::VLDMDIA_UPD;
   emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
               NumAlignedDPRCS2Regs);
   emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
               &isARMArea2Register, 0);
static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
   }
 
   return Limit;
 }
 
 // In functions that realign the stack, it can be an advantage to spill the
 // callee-saved vector registers after realigning the stack. The vst1 and vld1
 // instructions take alignment hints that can improve performance.
-static void
-checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
+static void checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs,
+                                      unsigned ScratchReg) {
   MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
   if (!SpillAlignedNEONRegs)
     return;
 
   // Naked functions don't spill callee-saved registers.
   if (MF.getFunction().hasFnAttribute(Attribute::Naked))
     return;
 
static void checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs,
   // Don't do this for just one d-register. It's not worth it.
   if (NumSpills < 2)
     return;
 
   // Spill the first NumSpills D-registers after realigning the stack.
   MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
 
   // A scratch register is required for the vst1 / vld1 instructions.
-  SavedRegs.set(ARM::R4);
+  SavedRegs.set(ScratchReg);
 }
 
 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                             BitVector &SavedRegs,
                                             RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
   // This tells PEI to spill the FP as if it is any other callee-save register
   // to take advantage the eliminateFrameIndex machinery. This also ensures it
const ARMBaseInstrInfo &TII =
       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   (void)TRI;  // Silence unused warning in non-assert builds.
   Register FramePtr = RegInfo->getFrameRegister(MF);
 
-  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
-  // scratch register. Also spill R4 if Thumb2 function has varsized objects,
-  // since it's not always possible to restore sp from fp in a single
-  // instruction.
-  // FIXME: It will be better just to find spare register here.
+  unsigned ScratchReg = getScratchRegister(MF);
+
+  // Spill scratch register if Thumb2 function requires stack realignment.
+  // Also spill it if Thumb2 function has varsized objects, since it's not
+  // always possible to restore sp from fp in a single instruction.
   if (AFI->isThumb2Function() &&
       (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
-    SavedRegs.set(ARM::R4);
+    SavedRegs.set(ScratchReg);
 
-  // If a stack probe will be emitted, spill R4 and LR, since they are
-  // clobbered by the stack probe call.
+  // If a stack probe will be emitted, spill scratch register and LR, since they
+  // are clobbered by the stack probe call.
   // This estimate should be a safe, conservative estimate. The actual
   // stack probe is enabled based on the size of the local objects;
   // this estimate also includes the varargs store size.
   if (STI.isTargetWindows() &&
       WindowsRequiresStackProbe(MF, MFI.estimateStackSize(MF))) {
-    SavedRegs.set(ARM::R4);
+    SavedRegs.set(ScratchReg);
     SavedRegs.set(ARM::LR);
   }
 
   if (AFI->isThumb1OnlyFunction()) {
     // Spill LR if Thumb1 function uses variable length argument lists.
     if (AFI->getArgRegsSaveSize() > 0)
       SavedRegs.set(ARM::LR);
 
-    // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function
-    // requires stack alignment.  We don't know for sure what the stack size
-    // will be, but for this, an estimate is good enough. If there anything
-    // changes it, it'll be a spill, which implies we've used all the registers
-    // and so R4 is already used, so not marking it here will be OK.
-    // FIXME: It will be better just to find spare register here.
+    // Spill the scratch register if Thumb1 epilogue has to restore SP from FP
+    // or the function requires stack alignment.  We don't know for sure what
+    // the stack size will be, but for this, an estimate is good enough. If
+    // there anything changes it, it'll be a spill, which implies we've used all
+    // the registers and so R4 is already used, so not marking it here will be
+    // OK.
     if (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) ||
         MFI.estimateStackSize(MF) > 508)
-      SavedRegs.set(ARM::R4);
+      SavedRegs.set(ScratchReg);
   }
 
   // See if we can spill vector registers to aligned stack.
-  checkNumAlignedDPRCS2Regs(MF, SavedRegs);
+  checkNumAlignedDPRCS2Regs(MF, SavedRegs, ScratchReg);
 
   // Spill the BasePtr if it's used.
   if (RegInfo->hasBasePointer(MF))
     SavedRegs.set(RegInfo->getBaseRegister());
 
   // Don't spill FP if the frame can be eliminated. This is determined
   // by scanning the callee-save registers to see if any is modified.
   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
void ARMFrameLowering::adjustForSegmentedStacks(
   // its non-existent prologue, it would fail with an error. Mark the object
   // file so that such failures are not errors. See this Go language bug-report
   // https://go-review.googlesource.com/c/go/+/148819/
   if (StackSize == 0 && !MFI.hasTailCall()) {
     MF.getMMI().setHasNosplitStack(true);
     return;
   }
 
-  // Use R4 and R5 as scratch registers.
-  // We save R4 and R5 before use and restore them before leaving the function.
-  unsigned ScratchReg0 = ARM::R4;
-  unsigned ScratchReg1 = ARM::R5;
+  // We will use r4 to hold stack limit and r5 to hold the stack size
+  // requested and arguments for __morestack().
+
+  // r4 and r5 might be used as global named registers. If that is the case,
+  // temporarily save their content in other registers so they're free
+  // to be used for __morestack
+  unsigned BackupR4 = ARM::NoRegister;
+  unsigned BackupR5 = ARM::NoRegister;
+  BitVector UsedRegs = BitVector(ARM::GPRRegClass.getNumRegs());
+  // make sure we won't get the suggestion to use r4/r5 as backup reg
+  unsigned R4 = ARM::R4 - ARM::GPRRegClass.begin()[0];
+  unsigned R5 = ARM::R5 - ARM::GPRRegClass.begin()[0];
+  UsedRegs[R4] = true;
+  UsedRegs[R5] = true;
+
+  if (STI.isGPRegisterReserved(R4)) {
+    if (!STI.hasV6Ops())
+      // Do not allow r4 to be reserved if segmented stacks are used on a
+      // target where 'mov low_reg, low_reg' is not possible
+      report_fatal_error("-ffixed-r4 is not allowed for this target when "
+                         "segmented stacks are in use.");
+    BackupR4 = getScratchRegister(MF, UsedRegs);
+    UsedRegs[BackupR4 - ARM::GPRRegClass.begin()[0]] = true;
+  }
+  if (STI.isGPRegisterReserved(R5)) {
+    if (!STI.hasV6Ops())
+      // Do not allow r5 to be reserved if segmented stacks are used on a
+      // target where 'mov low_reg, low_reg' is not possible
+      report_fatal_error("-ffixed-r5 is not allowed for this target when "
+                         "segmented stacks are in use.");
+    BackupR5 = getScratchRegister(MF, UsedRegs);
+  }
+
   uint64_t AlignedStackSize;
 
   MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
   MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
   MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
   MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
   MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
 
void ARMFrameLowering::adjustForSegmentedStacks(
 
   // The required stack size that is aligned to ARM constant criterion.
   AlignedStackSize = alignToARMConstant(StackSize);
 
   // When the frame size is less than 256 we just compare the stack
   // boundary directly to the value of the stack pointer, per gcc.
   bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
 
-  // We will use two of the callee save registers as scratch registers so we
-  // need to save those registers onto the stack.
-  // We will use SR0 to hold stack limit and SR1 to hold the stack size
-  // requested and arguments for __morestack().
-  // SR0: Scratch Register #0
-  // SR1: Scratch Register #1
-  // push {SR0, SR1}
+  // We will use r4 and r5 either directly or use scratch registers to save
+  // their values, so we need to save those registers onto the stack.
+  // push {r4/sr4, r5/sr5}
+  unsigned sortedPushList[2] = {
+      std::min(BackupR4 ? BackupR4 : (unsigned)ARM::R4,
+               BackupR5 ? BackupR5 : (unsigned)ARM::R5),
+      std::max(BackupR5 ? BackupR5 : (unsigned)ARM::R5,
+               BackupR4 ? BackupR4 : (unsigned)ARM::R4)};
   if (Thumb) {
     BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
         .add(predOps(ARMCC::AL))
-        .addReg(ScratchReg0)
-        .addReg(ScratchReg1);
+        .addReg(sortedPushList[0])
+        .addReg(sortedPushList[1]);
   } else {
     BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
-        .addReg(ScratchReg0)
-        .addReg(ScratchReg1);
+        .addReg(sortedPushList[0])
+        .addReg(sortedPushList[1]);
   }
 
+  if (BackupR4)
+    BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), BackupR4)
+        .addReg(ARM::R4)
+        .add(predOps(ARMCC::AL));
+  if (BackupR5)
+    BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), BackupR5)
+        .addReg(ARM::R5)
+        .add(predOps(ARMCC::AL));
+
   // Emit the relevant DWARF information about the change in stack pointer as
   // well as where to find both r4 and r5 (the callee-save registers)
   CFIIndex =
       MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
   BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
   CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
-      nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
+      nullptr, MRI->getDwarfRegNum(ARM::R5, true), -4));
   BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
   CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
-      nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
+      nullptr, MRI->getDwarfRegNum(ARM::R4, true), -8));
   BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
 
   // mov SR1, sp
   if (Thumb) {
-    BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
+    BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ARM::R5)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL));
   } else if (CompareStackPointer) {
-    BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
+    BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ARM::R5)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .add(condCodeOp());
   }
 
   // sub SR1, sp, #StackSize
   if (!CompareStackPointer && Thumb) {
-    BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
+    BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ARM::R5)
         .add(condCodeOp())
-        .addReg(ScratchReg1)
+        .addReg(ARM::R5)
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL));
   } else if (!CompareStackPointer) {
-    BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
+    BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ARM::R5)
         .addReg(ARM::SP)
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL))
         .add(condCodeOp());
   }
 
   if (Thumb && ST->isThumb1Only()) {
     unsigned PCLabelId = ARMFI->createPICLabelUId();
     ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
         MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0);
     MachineConstantPool *MCP = MF.getConstantPool();
     unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4);
 
-    // ldr SR0, [pc, offset(STACK_LIMIT)]
-    BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
+    // ldr r4, [pc, offset(STACK_LIMIT)]
+    BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ARM::R4)
         .addConstantPoolIndex(CPI)
         .add(predOps(ARMCC::AL));
 
-    // ldr SR0, [SR0]
-    BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
-        .addReg(ScratchReg0)
+    // ldr r4, [r4]
+    BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ARM::R4)
+        .addReg(ARM::R4)
         .addImm(0)
         .add(predOps(ARMCC::AL));
   } else {
     // Get TLS base address from the coprocessor
-    // mrc p15, #0, SR0, c13, c0, #3
-    BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
+    // mrc p15, #0, r4, c13, c0, #3
+    BuildMI(McrMBB, DL, TII.get(ARM::MRC), ARM::R4)
         .addImm(15)
         .addImm(0)
         .addImm(13)
         .addImm(0)
         .addImm(3)
         .add(predOps(ARMCC::AL));
 
     // Use the last tls slot on android and a private field of the TCP on linux.
     assert(ST->isTargetAndroid() || ST->isTargetLinux());
     unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
 
     // Get the stack limit from the right offset
-    // ldr SR0, [sr0, #4 * TlsOffset]
-    BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
-        .addReg(ScratchReg0)
+    // ldr r4, [sr0, #4 * TlsOffset]
+    BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ARM::R4)
+        .addReg(ARM::R4)
         .addImm(4 * TlsOffset)
         .add(predOps(ARMCC::AL));
   }
 
   // Compare stack limit with stack size requested.
-  // cmp SR0, SR1
+  // cmp r4, r5
   Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
   BuildMI(GetMBB, DL, TII.get(Opcode))
-      .addReg(ScratchReg0)
-      .addReg(ScratchReg1)
+      .addReg(ARM::R4)
+      .addReg(ARM::R5)
       .add(predOps(ARMCC::AL));
 
   // This jump is taken if StackLimit < SP - stack required.
   Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
   BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
        .addImm(ARMCC::LO)
        .addReg(ARM::CPSR);
 
-
   // Calling __morestack(StackSize, Size of stack arguments).
-  // __morestack knows that the stack size requested is in SR0(r4)
-  // and amount size of stack arguments is in SR1(r5).
+  // __morestack knows that the stack size requested is in r4
+  // and amount size of stack arguments is in r5.
 
-  // Pass first argument for the __morestack by Scratch Register #0.
+  // Pass first argument for the __morestack by r4.
   //   The amount size of stack required
   if (Thumb) {
-    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
+    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ARM::R4)
         .add(condCodeOp())
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL));
   } else {
-    BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
+    BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ARM::R4)
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL))
         .add(condCodeOp());
   }
   // Pass second argument for the __morestack by Scratch Register #1.
-  //   The amount size of stack consumed to save function arguments.
+  // Pass second argument for the __morestack by r5.
   if (Thumb) {
-    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
+    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ARM::R5)
         .add(condCodeOp())
         .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
         .add(predOps(ARMCC::AL));
   } else {
-    BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
+    BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ARM::R5)
         .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
         .add(predOps(ARMCC::AL))
         .add(condCodeOp());
   }
 
   // push {lr} - Save return address of this function.
   if (Thumb) {
     BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
BuildMI(AllocMBB, DL, TII.get(ARM::BL))
         .addExternalSymbol("__morestack");
   }
 
   // pop {lr} - Restore return address of this original function.
   if (Thumb) {
     if (ST->isThumb1Only()) {
       BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
           .add(predOps(ARMCC::AL))
-          .addReg(ScratchReg0);
+          .addReg(ARM::R4);
       BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
-          .addReg(ScratchReg0)
+          .addReg(ARM::R4)
           .add(predOps(ARMCC::AL));
     } else {
       BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
           .addReg(ARM::LR, RegState::Define)
           .addReg(ARM::SP, RegState::Define)
           .addReg(ARM::SP)
           .addImm(4)
           .add(predOps(ARMCC::AL));
     }
   } else {
     BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .addReg(ARM::LR);
   }
 
-  // Restore SR0 and SR1 in case of __morestack() was called.
+  // If r4 and r5 were secured using other registers, restore them from there
+  // movr r4, sr4
+  // movr r5, sr5
+  if (BackupR4)
+    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::R4)
+        .addReg(BackupR4)
+        .add(predOps(ARMCC::AL));
+  if (BackupR5)
+    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::R5)
+        .addReg(BackupR5)
+        .add(predOps(ARMCC::AL));
+
+  // Restore r4 and r5, resp. the secure scratch registers, in case of
+  // __morestack() was not called.
   // __morestack() will skip PostStackMBB block so we need to restore
   // scratch registers from here.
-  // pop {SR0, SR1}
+  // pop {r4/sr4, r5/sr5}
   if (Thumb) {
     BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
         .add(predOps(ARMCC::AL))
-        .addReg(ScratchReg0)
-        .addReg(ScratchReg1);
+        .addReg(sortedPushList[0])
+        .addReg(sortedPushList[1]);
   } else {
     BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
-        .addReg(ScratchReg0)
-        .addReg(ScratchReg1);
+        .addReg(sortedPushList[0])
+        .addReg(sortedPushList[1]);
   }
 
   // Update the CFA offset now that we've popped
   CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
   BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
 
   // Return from this function.
   BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
 
   // Restore SR0 and SR1 in case of __morestack() was not called.
-  // pop {SR0, SR1}
+  // Restore r4 and r5, resp. the secure scratch registers, in case of
+  // __morestack() was not called.
+  // movr r4, sr4
+  // movr r5, sr5
+  // pop {r4/sr4, r5/sr5}
   if (Thumb) {
     BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
         .add(predOps(ARMCC::AL))
-        .addReg(ScratchReg0)
-        .addReg(ScratchReg1);
+        .addReg(sortedPushList[0])
+        .addReg(sortedPushList[1]);
   } else {
     BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
         .addReg(ARM::SP, RegState::Define)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
-        .addReg(ScratchReg0)
-        .addReg(ScratchReg1);
+        .addReg(sortedPushList[0])
+        .addReg(sortedPushList[1]);
   }
 
   // Update the CFA offset now that we've popped
   CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
   BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
 
   // Tell debuggers that r4 and r5 are now the same as they were in the
   // previous function, that they're the "Same Value".
   CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
-      nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
+      nullptr, MRI->getDwarfRegNum(ARM::R4, true)));
   BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
   CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
-      nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
+      nullptr, MRI->getDwarfRegNum(ARM::R5, true)));
   BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
 
   // Organizing MBB lists
   PostStackMBB->addSuccessor(&PrologueMBB);
 
   AllocMBB->addSuccessor(PostStackMBB);
 

llvm/lib/Target/ARM/ARMISelLowering.h

public:
     bool isDesirableToCommuteWithShift(const SDNode *N,
                                        CombineLevel Level) const override;
 
     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                            CombineLevel Level) const override;
 
     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 
+    unsigned getScratchRegister(unsigned FramePointer) const;
+
   protected:
     std::pair<const TargetRegisterClass *, uint8_t>
     findRepresentativeClass(const TargetRegisterInfo *TRI,
                             MVT VT) const override;
 
   private:
     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
     /// make the right decision when generating code for different targets.

llvm/lib/Target/ARM/ARMISelLowering.cpp

SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
   return FrameAddr;
 }
 
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
                                               const MachineFunction &MF) const {
   Register Reg = StringSwitch<unsigned>(RegName)
+                     .Case("r4", ARM::R4)
+                     .Case("r5", ARM::R5)
                      .Case("r6", ARM::R6)
                      .Case("r7", ARM::R7)
                      .Case("r8", ARM::R8)
                      .Case("r9", ARM::R9)
                      .Case("r10", ARM::R10)
                      .Case("r11", ARM::R11)
                      .Case("sp", ARM::SP)
                      .Default(ARM::NoRegister);
ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
   const TargetMachine &TM = getTargetMachine();
   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
   DebugLoc DL = MI.getDebugLoc();
 
   assert(Subtarget->isTargetWindows() &&
          "__chkstk is only supported on Windows");
   assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
 
+  // r4 might be used as global named register, which means its value has not
+  // been and must not be saved to the stack. Thus temporarily save its
+  // content in another register so r4 is free to be used for __chkstk
+  unsigned BackupR4 = ARM::NoRegister;
+  if (Subtarget->isGPRegisterReserved(ARM::R4 - ARM::GPRRegClass.begin()[0])) {
+    BackupR4 = getScratchRegister(ARM::R11);
+    BuildMI(*MBB, MI, DL, TII.get(ARM::tMOVr), ARM::R4)
+        .addReg(BackupR4)
+        .add(predOps(ARMCC::AL));
+    ;
+  }
+
   // __chkstk takes the number of words to allocate on the stack in R4, and
   // returns the stack adjustment in number of bytes in R4.  This will not
   // clober any other registers (other than the obvious lr).
   //
   // Although, technically, IP should be considered a register which may be
   // clobbered, the call itself will not touch it.  Windows on ARM is a pure
   // thumb-2 environment, so there is no interworking required.  As a result, we
   // do not expect a veneer to be emitted by the linker, clobbering IP.
ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
 
   BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
       .addReg(ARM::SP, RegState::Kill)
       .addReg(ARM::R4, RegState::Kill)
       .setMIFlags(MachineInstr::FrameSetup)
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
 
+  // If r4 is actually a fixed register, restore it
+  if (BackupR4) {
+    BuildMI(*MBB, MI, DL, TII.get(ARM::tMOVr), BackupR4)
+        .addReg(ARM::R4)
+        .add(predOps(ARMCC::AL));
+    ;
+  }
+
   MI.eraseFromParent();
   return MBB;
 }
 
 MachineBasicBlock *
 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
                                        MachineBasicBlock *MBB) const {
   DebugLoc DL = MI.getDebugLoc();
for (auto *Exit : Exits)
           .addReg(NewVR);
   }
 }
 
 void ARMTargetLowering::finalizeLowering(MachineFunction &MF) const {
   MF.getFrameInfo().computeMaxCallFrameSize(MF);
   TargetLoweringBase::finalizeLowering(MF);
 }
+
+unsigned ARMTargetLowering::getScratchRegister(unsigned FramePointer) const {
+  for (unsigned i = 4; i < ARM::GPRRegClass.getNumRegs() - 4; i++) {
+    // register must not be reserved nor FP
+    if (!Subtarget->isGPRegisterReserved(i) && i != FramePointer) {
+      return ARM::GPRRegClass.getRegister(i);
+    }
+  }
+  report_fatal_error("ran out of registers: Too many registers reserved");
+  return ARM::NoRegister;
+}

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

const FeatureBitset InlineFeatureWhitelist = {
       ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
       ARM::FeatureHasSlowFPVMLx, ARM::FeatureVMLxForwarding,
       ARM::FeaturePref32BitThumb, ARM::FeatureAvoidPartialCPSR,
       ARM::FeatureCheapPredicableCPSR, ARM::FeatureAvoidMOVsShOp,
       ARM::FeatureHasRetAddrStack, ARM::FeatureHasNoBranchPredictor,
       ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
       ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
       ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
-      ARM::FeatureExecuteOnly, ARM::FeatureReserveR6, ARM::FeatureReserveR7,
-      ARM::FeatureReserveR8, ARM::FeatureReserveR9, ARM::FeatureReserveR10,
-      ARM::FeatureReserveR11, ARM::FeatureNoMovt,
-      ARM::FeatureNoNegativeImmediates
+      ARM::FeatureExecuteOnly, ARM::FeatureReserveR4, ARM::FeatureReserveR5,
+      ARM::FeatureReserveR6, ARM::FeatureReserveR7, ARM::FeatureReserveR8,
+      ARM::FeatureReserveR9, ARM::FeatureReserveR10, ARM::FeatureReserveR11,
+      ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
   };
 
   const ARMSubtarget *getST() const { return ST; }
   const ARMTargetLowering *getTLI() const { return TLI; }
 
 public:
   explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),

llvm/lib/Target/ARM/Thumb1FrameLowering.h

bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
                                   std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
+  unsigned getScratchRegister(const MachineFunction &MF,
+                              BitVector inUse = BitVector()) const;
+
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override;
 
   /// Check whether or not the given \p MBB can be used as a epilogue
   /// for the target.
   /// The epilogue will be inserted before the first terminator of that block.

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
   // address the stack frame. So a large call frame can cause poor codegen
   // and may even makes it impossible to scavenge a register.
   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
     return false;
 
   return !MFI.hasVarSizedObjects();
 }
 
+unsigned Thumb1FrameLowering::getScratchRegister(const MachineFunction &MF,
+                                                 BitVector InUse) const {
+  unsigned Reg = ARMFrameLowering::getScratchRegister(MF, InUse);
+  if (isARMLowRegister(Reg))
+    return Reg;
+  report_fatal_error("ran out of registers: Too many registers reserved");
+  return ARM::NoRegister;
+}
+
 static void
 emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator &MBBI,
                              const TargetInstrInfo &TII, const DebugLoc &dl,
                              const ThumbRegisterInfo &MRI, int NumBytes,
                              unsigned ScratchReg, unsigned MIFlags) {
   // If it would take more than three instructions to adjust the stack pointer
   // using tADDspi/tSUBspi, load an immediate instead.
void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
   }
 
   if (NumBytes) {
     // Insert it after all the callee-save spills.
     //
     // For a large stack frame, we might need a scratch register to store
     // the size of the frame.  We know all callee-save registers are free
     // at this point in the prologue, so pick one.
-    unsigned ScratchRegister = ARM::NoRegister;
-    for (auto &I : CSI) {
-      unsigned Reg = I.getReg();
-      if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
-        ScratchRegister = Reg;
-        break;
-      }
-    }
+    unsigned ScratchReg = getScratchRegister(MF);
     emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
-                                 ScratchRegister, MachineInstr::FrameSetup);
+                                 ScratchReg, MachineInstr::FrameSetup);
     if (!HasFP) {
       CFAOffset -= NumBytes;
       unsigned CFIIndex = MF.addFrameInst(
           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlags(MachineInstr::FrameSetup);
     }
   }
 
   if (STI.isTargetELF() && HasFP)
     MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
                             AFI->getFramePtrSpillOffset());
 
   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
 
   if (RegInfo->needsStackRealignment(MF)) {
     const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
-    // Emit the following sequence, using R4 as a temporary, since we cannot use
-    // SP as a source or destination register for the shifts:
+    // Emit the following sequence, using our scratch register as a temporary,
+    // since we cannot use SP as a source or destination register for the
+    // shifts:
     // mov  r4, sp
     // lsrs r4, r4, #NrBitsToZero
     // lsls r4, r4, #NrBitsToZero
     // mov  sp, r4
-    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
+    // (ex.: scratchReg=r4)
+    unsigned ScratchReg = getScratchRegister(MF);
+    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ScratchReg)
         .addReg(ARM::SP, RegState::Kill)
         .add(predOps(ARMCC::AL));
 
-    BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
+    BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ScratchReg)
         .addDef(ARM::CPSR)
-      .addReg(ARM::R4, RegState::Kill)
+        .addReg(ScratchReg, RegState::Kill)
         .addImm(NrBitsToZero)
         .add(predOps(ARMCC::AL));
 
-    BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
+    BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ScratchReg)
         .addDef(ARM::CPSR)
-      .addReg(ARM::R4, RegState::Kill)
+        .addReg(ScratchReg, RegState::Kill)
         .addImm(NrBitsToZero)
         .add(predOps(ARMCC::AL));
 
     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
-      .addReg(ARM::R4, RegState::Kill)
+        .addReg(ScratchReg, RegState::Kill)
         .add(predOps(ARMCC::AL));
 
     AFI->setShouldRestoreSPFromFP(true);
   }
 
   // If we need a base pointer, set it up here. It's whatever the value
   // of the stack pointer is at this point. Any variable size objects
   // will be allocated after this, so we can still use the base pointer
   // to reference locals.
NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
                  AFI->getDPRCalleeSavedAreaSize() +
                  ArgRegsSaveSize);
 
     if (AFI->shouldRestoreSPFromFP()) {
       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
       // Reset SP based on frame pointer only if the stack frame extends beyond
       // frame pointer stack slot, the target is ELF and the function has FP, or
       // the target uses var sized objects.
+      unsigned ScratchReg = Thumb1FrameLowering::getScratchRegister(MF);
       if (NumBytes) {
-        assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
+        assert(!MFI.getPristineRegs(MF).test(ScratchReg) &&
                "No scratch register to restore SP from FP!");
-        emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
-                                  TII, *RegInfo);
+        emitThumbRegPlusImmediate(MBB, MBBI, dl, ScratchReg, FramePtr,
+                                  -NumBytes, TII, *RegInfo);
         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
-            .addReg(ARM::R4)
+            .addReg(ScratchReg)
             .add(predOps(ARMCC::AL));
       } else
         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
             .addReg(FramePtr)
             .add(predOps(ARMCC::AL));
     } else {
       // For a large stack frame, we might need a scratch register to store
       // the size of the frame.  We know all callee-save registers are free
       // at this point in the epilogue, so pick one.
-      unsigned ScratchRegister = ARM::NoRegister;
-      bool HasFP = hasFP(MF);
-      for (auto &I : MFI.getCalleeSavedInfo()) {
-        unsigned Reg = I.getReg();
-        if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
-          ScratchRegister = Reg;
-          break;
-        }
-      }
+      unsigned ScratchReg = getScratchRegister(MF);
       if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
           &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
         MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
         if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
           emitPrologueEpilogueSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes,
-                                       ScratchRegister, MachineInstr::NoFlags);
+                                       ScratchReg, MachineInstr::NoFlags);
       } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
         emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes,
-                                     ScratchRegister, MachineInstr::NoFlags);
+                                     ScratchReg, MachineInstr::NoFlags);
     }
   }
 
   if (needPopSpecialFixUp(MF)) {
     bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
     (void)Done;
     assert(Done && "Emission of the special fixup failed!?");
   }

llvm/test/CodeGen/ARM/Windows/chkstk-fixed-r4.ll

+; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -filetype asm -mattr=+reserve-r4 %s -o - \
+; RUN:  | FileCheck %s
+
+define arm_aapcs_vfpcc void @check_r4usage() {
+entry:
+  %buffer = alloca [4096 x i8], align 1
+  ret void
+}
+
+; CHECK-NOT: push {{{.*}}r4{{.*}}}
+; CHECK: push {{{.*}}r5{{.*}}}
+; CHECK: mov r5, r4
+; CHECK: movw r4, #1024
+; CHECK: bl __chkstk
+; CHECK: sub.w sp, sp, r4
+; CHECK: mov r4, r5
+; CHECK: pop {{{.*}}r5{{.*}}}
+; CHECK-NOT: pop {{{.*}}r4{{.*}}}
+

llvm/test/CodeGen/ARM/Windows/vla-fixed-r4.ll

+; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -mattr=+reserve-r4 -filetype asm -o - %s \
+; RUN:  | FileCheck %s -check-prefix CHECK-SMALL-CODE
+; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -code-model=large -mattr=+reserve-r4 -filetype asm -o - %s \
+; RUN:  | FileCheck %s -check-prefix CHECK-LARGE-CODE
+; RUN: llc -mtriple=thumbv7-windows-msvc -mcpu=cortex-a9 -mattr=+reserve-r4 -filetype asm -o - %s \
+; RUN:  | FileCheck %s -check-prefix CHECK-SMALL-CODE
+
+define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) {
+entry:
+  %vla = alloca i8, i32 %sz, align 1
+  %arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx
+  %0 = load volatile i8, i8* %arrayidx, align 1
+  ret i8 %0
+}
+
+; CHECK-SMALL-CODE:   adds [[R4:r[0-9]+]], #7
+; CHECK-SMALL-CODE:   bic [[R4]], [[R4]], #4
+; CHECK-SMALL-CODE:   lsrs r4, [[R4]], #2
+; CHECK-SMALL-CODE:   bl __chkstk
+; CHECK-SMALL-CODE:   sub.w sp, sp, r4
+
+; CHECK-LARGE-CODE:   adds  [[R4:r[0-9]+]], #7
+; CHECK-LARGE-CODE:   bic   [[R4]], [[R4]], #4
+; CHECK-LARGE-CODE:   lsrs  r4, [[R4]], #2
+; CHECK-LARGE-CODE:   movw  [[IP:r[0-9]+]], :lower16:__chkstk
+; CHECK-LARGE-CODE:   movt  [[IP]], :upper16:__chkstk
+; CHECK-LARGE-CODE:   blx   [[IP]]
+; CHECK-LARGE-CODE:   sub.w sp, sp, r4

llvm/test/CodeGen/ARM/named-reg-alloc.ll

 ; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
 ; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
 
 define i32 @get_stack() nounwind {
 entry:
 ; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name "r5".
+; CHECK: Invalid register name "r3".
   %sp = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %sp
 }
 
 declare i32 @llvm.read_register.i32(metadata) nounwind
 
-!0 = !{!"r5\00"}
+!0 = !{!"r3\00"}

llvm/test/CodeGen/ARM/reg-alloc-no-alignment.ll

+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs -mattr=+reserve-r10,+reserve-r9,+reserve-r8,+reserve-r4 \
+; RUN:     -asm-verbose=false | FileCheck %s
+
+
+declare dso_local i32 @bar(i32*) #1
+
+; Reserved registers should not be used to correct alignment.
+define hidden i32 @main() #0 {
+; CHECK-NOT: r10
+; CHECK-NOT: r9
+; CHECK-NOT: r8
+; CHECK-NOT: r4
+; CHECK: {r5, r7, lr}
+  %a = alloca i32, i32 4, align 8
+  %1 = call i32 @bar (i32* %a)
+  ret i32 %1
+}
 No newline at end of file

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r4-r5-r6.ll

+; RUN: llc < %s -mattr=+reserve-r4,+reserve-r5,+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r4{{.*}}}
+; CHECK-NOT: push {{{.*}}r5, r6{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK-NOT: {{.*}}r4{{.*}}
+; CHECK-NOT: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+; CHECK: {{.*}}r7{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r4{{.*}}}
+; CHECK-NOT: pop {{{.*}}r5, r6{{.*}}}
+}

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r5-r6.ll

+; RUN: llc < %s -mattr=+reserve-r5,+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r5, r6{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK-NOT: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+; CHECK: {{.*}}r7{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r5, r6{{.*}}}
+}

llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r5.ll

+; RUN: llc < %s -mattr=+reserve-r5 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r5,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK-NOT: {{.*}}r5{{.*}}
+; CHECK: {{.*}}r6{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r5,{{.*}}}
+}

llvm/test/CodeGen/ARM/reg-allog-with-fixed-reg-r4.ll

+; RUN: llc < %s -mattr=+reserve-r4 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r4,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r4{{.*}}
+; CHECK: {{.*}}r6{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r4,{{.*}}}
+}

llvm/test/CodeGen/ARM/segmented-stacks-fixed-r4-r5.ll

+; RUN: not llc < %s -mtriple=arm-linux-androideabi -mattr=+v4t -mattr=+reserve-r4 2>&1 | FileCheck %s -check-prefix=ARM-android-ERROR-r4
+; RUN: not llc < %s -mtriple=arm-linux-androideabi -mattr=+v4t -mattr=+reserve-r5 2>&1 | FileCheck %s -check-prefix=ARM-android-ERROR-r5
+; RUN: not llc < %s -mtriple=arm-linux-unknown-gnueabi -mattr=+v4t -mattr=+reserve-r4 2>&1 | FileCheck %s -check-prefix=ARM-linux-ERROR
+
+; ARM-android-ERROR-r4: -ffixed-r4 is not allowed for this target when segmented stacks are in use.
+; ARM-android-ERROR-r5: -ffixed-r5 is not allowed for this target when segmented stacks are in use.
+; ARM-linux-ERROR: -ffixed-r4 is not allowed for this target when segmented stacks are in use.
+
+; RUN: llc < %s -mtriple=armv7--linux-gnueabihf -mattr=+reserve-r4 -verify-machineinstrs | FileCheck %s -check-prefix=r4-ARM-linux
+; RUN: llc < %s -mtriple=armv7--linux-gnueabihf -mattr=+reserve-r4 -mattr=+reserve-r5 -verify-machineinstrs | FileCheck %s -check-prefix=r4-r5-ARM-linux
+
+; Just to prevent the alloca from being optimized away
+declare void @dummy_use(i32*, i32)
+
+define void @test_basic() #0 {
+        %mem = alloca i32, i32 10
+        call void @dummy_use (i32* %mem, i32 10)
+  ret void
+
+; r4-ARM-linux:           push    {r5, r6}
+; r4-ARM-linux-NEXT:      mov     r6, r4
+; r4-ARM-linux-NEXT:      mrc     p15, #0, r4, c13, c0, #3
+; r4-ARM-linux-NEXT:      mov     r5, sp
+; r4-ARM-linux-NEXT:       ldr     r4, [r4, #4]
+; r4-ARM-linux-NEXT:      cmp     r4, r5
+; r4-ARM-linux-NEXT:      blo     .LBB0_2
+
+; r4-ARM-linux:           mov     r4, #48
+; r4-ARM-linux-NEXT:      mov     r5, #0
+; r4-ARM-linux-NEXT:      stmdb   sp!, {lr}
+; r4-ARM-linux-NEXT:      bl      __morestack
+; r4-ARM-linux-NEXT:      ldm     sp!, {lr}
+; r4-ARM-linux-NEXT:      mov     r4, r6
+; r4-ARM-linux-NEXT:      pop     {r5, r6}
+; r4-ARM-linux-NEXT:      bx      lr
+
+
+
+; r4-r5-ARM-linux:        push    {r6, r7}
+; r4-r5-ARM-linux-NEXT:   mov     r6, r4
+; r4-r5-ARM-linux-NEXT:   mrc     p15, #0, r4, c13, c0, #3
+; r4-r5-ARM-linux-NEXT:   mov     r7, r5
+; r4-r5-ARM-linux-NEXT:   mov     r5, sp
+; r4-r5-ARM-linux-NEXT:   ldr     r4, [r4, #4]
+; r4-r5-ARM-linux-NEXT:   cmp     r4, r5
+; r4-r5-ARM-linux-NEXT:   blo     .LBB0_2
+
+; r4-r5-ARM-linux:        mov     r4, #48
+; r4-r5-ARM-linux-NEXT:   mov     r5, #0
+; r4-r5-ARM-linux-NEXT:    stmdb   sp!, {lr}
+; r4-r5-ARM-linux-NEXT:   bl      __morestack
+; r4-r5-ARM-linux-NEXT:   ldm     sp!, {lr}
+; r4-r5-ARM-linux-NEXT:   mov     r4, r6
+; r4-r5-ARM-linux-NEXT:   mov     r5, r7
+; r4-r5-ARM-linux-NEXT:   pop     {r6, r7}
+; r4-r5-ARM-linux-NEXT:   bx      lr
+
+}
+
+attributes #0 = { "split-stack" }

llvm/test/CodeGen/Thumb/callee_save_reserved.ll

-; RUN: llc < %s -mtriple=thumbv6m-none-eabi -verify-machineinstrs -frame-pointer=none -mattr=+reserve-r6,+reserve-r8 \
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi -verify-machineinstrs -frame-pointer=none -mattr=+reserve-r6,+reserve-r5 \
 ; RUN:     -asm-verbose=false | FileCheck --check-prefix=CHECK-INVALID %s
 
 ; Reserved low registers should not be used to correct reg deficit.
 define <4 x i32> @four_high_four_return_reserved() {
 entry:
-  ; CHECK-INVALID-NOT: r{{6|8}}
+  ; CHECK-INVALID-NOT: r{{[5-6]+}}
   tail call void asm sideeffect "", "~{r8},~{r9}"()
   %vecinit = insertelement <4 x i32> undef, i32 1, i32 0
   %vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
   %vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
   %vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
   ret <4 x i32> %vecinit13
 }
 

llvm/test/CodeGen/Thumb/emergency-spill-slot.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
 target triple = "thumbv6m-unknown-unknown-eabi"
 
 define void @vla_emergency_spill(i32 %n) {
 ; CHECK-LABEL: vla_emergency_spill:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    .setfp r7, sp, #12
 ; CHECK-NEXT:    add r7, sp, #12
 ; CHECK-NEXT:    .pad #4100
-; CHECK-NEXT:    ldr r6, .LCPI0_0
-; CHECK-NEXT:    add sp, r6
+; CHECK-NEXT:    ldr r4, .LCPI0_0
+; CHECK-NEXT:    add sp, r4
 ; CHECK-NEXT:    mov r6, sp
 ; CHECK-NEXT:    adds r0, r0, #7
 ; CHECK-NEXT:    movs r1, #7
 ; CHECK-NEXT:    bics r0, r1
 ; CHECK-NEXT:    mov r1, sp
 ; CHECK-NEXT:    subs r0, r1, r0
 ; CHECK-NEXT:    mov sp, r0
 ; CHECK-NEXT:    adds r1, r6, #4

 }
 
 define void @simple_emergency_spill(i32 %n) {
 ; CHECK-LABEL: simple_emergency_spill:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    .pad #8196
-; CHECK-NEXT:    ldr r7, .LCPI1_0
-; CHECK-NEXT:    add sp, r7
+; CHECK-NEXT:    ldr r4, .LCPI1_0
+; CHECK-NEXT:    add sp, r4
 ; CHECK-NEXT:    add r0, sp, #4
 ; CHECK-NEXT:    ldr r1, .LCPI1_2
 ; CHECK-NEXT:    add r1, sp
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    str r0, [sp]
 ; CHECK-NEXT:    ldr r0, .LCPI1_3
 ; CHECK-NEXT:    add r0, sp
 ; CHECK-NEXT:    str r5, [r0]
 ; CHECK-NEXT:    ldr r0, [sp]
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    ldr r7, .LCPI1_1
-; CHECK-NEXT:    add sp, r7
+; CHECK-NEXT:    ldr r4, .LCPI1_1
+; CHECK-NEXT:    add sp, r4
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI1_0:
 ; CHECK-NEXT:    .long 4294959100 @ 0xffffdffc
 ; CHECK-NEXT:  .LCPI1_1:
 ; CHECK-NEXT:    .long 8196 @ 0x2004
 ; CHECK-NEXT:  .LCPI1_2:

 ; the priority list, so we use it anyway.  This is likely to confuse
 ; debuggers, so maybe worth changing at some point.
 define void @simple_emergency_spill_nor7(i32 %n) {
 ; CHECK-LABEL: simple_emergency_spill_nor7:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, lr}
 ; CHECK-NEXT:    .pad #8196
-; CHECK-NEXT:    ldr r6, .LCPI2_0
-; CHECK-NEXT:    add sp, r6
+; CHECK-NEXT:    ldr r4, .LCPI2_0
+; CHECK-NEXT:    add sp, r4
 ; CHECK-NEXT:    add r0, sp, #4
 ; CHECK-NEXT:    ldr r1, .LCPI2_2
 ; CHECK-NEXT:    add r1, sp
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    str r7, [sp]
 ; CHECK-NEXT:    ldr r7, .LCPI2_3
 ; CHECK-NEXT:    add r7, sp
 ; CHECK-NEXT:    str r5, [r7]
 ; CHECK-NEXT:    ldr r7, [sp]
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    ldr r6, .LCPI2_1
-; CHECK-NEXT:    add sp, r6
+; CHECK-NEXT:    ldr r4, .LCPI2_1
+; CHECK-NEXT:    add sp, r4
 ; CHECK-NEXT:    pop {r4, r5, r6, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI2_0:
 ; CHECK-NEXT:    .long 4294959100 @ 0xffffdffc
 ; CHECK-NEXT:  .LCPI2_1:
 ; CHECK-NEXT:    .long 8196 @ 0x2004
 ; CHECK-NEXT:  .LCPI2_2:

llvm/test/CodeGen/Thumb2/segmented-stacks-fixed-r4.ll

+; RUN: llc < %s -mtriple=thumb-linux-androideabi -mcpu=arm1156t2-s -mattr=+thumb2 -mattr=+reserve-r4 -verify-machineinstrs | FileCheck %s -check-prefix=Thumb-android
+; RUN: llc < %s -mtriple=thumb-linux-androideabi -mcpu=arm1156t2-s -mattr=+thumb2 -mattr=+reserve-r4 -filetype=obj
+
+
+; Just to prevent the alloca from being optimized away
+declare void @dummy_use(i32*, i32)
+
+define void @test_basic() #0 {
+        %mem = alloca i32, i32 10
+        call void @dummy_use (i32* %mem, i32 10)
+  ret void
+
+; Thumb-android:      test_basic:
+
+; Thumb-android:      push    {r5, r6}
+; Thumb-android-NEXT: mov     r6, r4
+; Thumb-android-NEXT: mrc     p15, #0, r4, c13, c0, #3
+; Thumb-android-NEXT: mov     r5, sp
+; Thumb-android-NEXT: ldr     r4, [r4, #252]
+; Thumb-android-NEXT: cmp     r4, r5
+; Thumb-android-NEXT: blo     .LBB0_2
+
+; Thumb-android:      mov     r4, #48
+; Thumb-android-NEXT: mov     r5, #0
+; Thumb-android-NEXT: push    {lr}
+; Thumb-android-NEXT: bl      __morestack
+; Thumb-android-NEXT: ldr     lr, [sp], #4
+; Thumb-android-NEXT: mov     r4, r6
+; Thumb-android-NEXT: pop     {r5, r6}
+; Thumb-android-NEXT: bx      lr
+
+; Thumb-android:      pop     {r5, r6}
+
+}
+
+attributes #0 = { "split-stack" }