diff --git a/llvm/test/tools/llvm-dwarfdump/RISCV/lit.local.cfg b/llvm/test/tools/llvm-dwarfdump/RISCV/lit.local.cfg new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/RISCV/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'RISCV' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/tools/llvm-dwarfdump/RISCV/riscv-relocs.yaml b/llvm/test/tools/llvm-dwarfdump/RISCV/riscv-relocs.yaml new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/RISCV/riscv-relocs.yaml @@ -0,0 +1,134 @@ +# Tests RISC-V relocations. We provide a .debug_info with multiple compilation +# units and apply a relocation on top of each DW_TAG_compile_unit's +# DW_AT_high_pc field, since that's a field where relocations are resolved. +# +# RUN: yaml2obj %s | llvm-dwarfdump - | FileCheck %s + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_RISCV +Sections: + - Name: .debug_info + Type: SHT_PROGBITS + # To add more relocations copy and append the starting 44-byte block: + # [28 00 00 00 04 .. 28). Change the last 16 bytes to change DW_AT_high_pc + # and DW_AT_stmt_list. + Content: 280000000400000000000801000000000C000000002F00000000000000000042000000000000000100000000280000000400000000000801000000000C000000002F00000000000000000042000000000000000200000000280000000400000000000801000000000C000000002F00000000000000000042000000000000000300000000280000000400000000000801000000000C000000002F00000000000000000042000000000000000400000000280000000400000000000801000000000C000000002F00000000000000000042000000000000000500000000280000000400000000000801000000000C000000002F00000000000000000042000000000000000600000000280000000400000000000801000000000C000000002F00000000000000000042000000000000000700000000280000000400000000000801000000000C000000002F00000000000000000042420000000000000800000000280000000400000000000801000000000C000000002F00000000000000000042420000000000000900000000280000000400000000000801000000000C000000002F00000000000000000042424242000000000A00000000280000000400000000000801000000000C000000002F00000000000000000042424242000000000B00000000280000000400000000000801000000000C000000002F00000000000000000042424242424242000C00000000280000000400000000000801000000000C000000002F00000000000000000042424242424242000D00000000 + - Name: .rela.debug_info + Type: SHT_RELA + Flags: [ SHF_INFO_LINK ] + Link: .symtab + EntSize: 0x0000000000000018 + Info: .debug_info + Relocations: +# 0x42 with R_RISCV_NONE(0x1) = 0x42 +# CHECK: DW_AT_high_pc (0x0000000000000042) +# CHECK-NEXT: DW_AT_stmt_list (0x00000001) + - Offset: 0x000000000000001F + Symbol: v1 + Type: R_RISCV_NONE +# 0x42 with R_RISCV_32(0xffffffffffffffff) = 0x00000000ffffffff +# CHECK: DW_AT_high_pc (0x00000000ffffffff) +# CHECK-NEXT: DW_AT_stmt_list (0x00000002) + - Offset: 0x000000000000004B + Symbol: vFFFFFFFFFFFFFFFF + Type: R_RISCV_32 +# 0x42 with R_RISCV_64(0xffffffffffffffff) = 0xffffffffffffffff +# CHECK: DW_AT_high_pc (0xffffffffffffffff) +# CHECK-NEXT: DW_AT_stmt_list (0x00000003) + - Offset: 0x0000000000000077 + Symbol: vFFFFFFFFFFFFFFFF + Type: R_RISCV_64 +# 0x42 with R_RISCV_SET6(1) = 0x41 +# CHECK: DW_AT_high_pc (0x0000000000000041) +# CHECK-NEXT: DW_AT_stmt_list (0x00000004) + - Offset: 0x00000000000000A3 + Symbol: v1 + Type: R_RISCV_SET6 +# 0x42 with R_RISCV_SUB6(0x4) = 0x7E +# CHECK: DW_AT_high_pc (0x000000000000007e) +# CHECK-NEXT: DW_AT_stmt_list (0x00000005) + - Offset: 0x00000000000000CF + Symbol: v4 + Type: R_RISCV_SUB6 +# 0x42 with R_RISCV_ADD8(0x04020103) = 0x45 +# CHECK: DW_AT_high_pc (0x0000000000000045) +# CHECK-NEXT: DW_AT_stmt_list (0x00000006) + - Offset: 0x00000000000000FB + Symbol: v04020103 + Type: R_RISCV_ADD8 +# 0x42 with R_RISCV_SUB8(0x04020103) = 0x3F +# CHECK: DW_AT_high_pc (0x000000000000003f) +# CHECK-NEXT: DW_AT_stmt_list (0x00000007) + - Offset: 0x0000000000000127 + Symbol: v04020103 + Type: R_RISCV_SUB8 +# 0x4242 with R_RISCV_ADD16(0x04020103) = 0x4345 +# CHECK: DW_AT_high_pc (0x0000000000004345) +# CHECK-NEXT: DW_AT_stmt_list (0x00000008) + - Offset: 0x0000000000000153 + Symbol: v04020103 + Type: R_RISCV_ADD16 +# 0x4242 with R_RISCV_SUB16(0x04020103) = 0x413F +# CHECK: DW_AT_high_pc (0x000000000000413f) +# CHECK-NEXT: DW_AT_stmt_list (0x00000009) + - Offset: 0x000000000000017F + Symbol: v04020103 + Type: R_RISCV_SUB16 +# 0x42424242 with R_RISCV_ADD32(0x04020103) = 0x46444345 +# CHECK: DW_AT_high_pc (0x0000000046444345) +# CHECK-NEXT: DW_AT_stmt_list (0x0000000a) + - Offset: 0x00000000000001AB + Symbol: v04020103 + Type: R_RISCV_ADD32 +# 0x42424242 with R_RISCV_SUB32(0x04020103) = 0x3E40413F +# CHECK: DW_AT_high_pc (0x000000003e40413f) +# CHECK-NEXT: DW_AT_stmt_list (0x0000000b) + - Offset: 0x00000000000001D7 + Symbol: v04020103 + Type: R_RISCV_SUB32 +# 0x0042424242424242 with R_RISCV_ADD64(0x0100000000000000) = 0x0142424242424242 +# CHECK: DW_AT_high_pc (0x0142424242424242) +# CHECK-NEXT: DW_AT_stmt_list (0x0000000c) + - Offset: 0x0000000000000203 + Symbol: v0100000000000000 + Type: R_RISCV_ADD64 +# 0x0042424242424242 with R_RISCV_SUB64(0x0100000000000000) = 0xFF42424242424242 +# CHECK: DW_AT_high_pc (0xff42424242424242) +# CHECK-NEXT: DW_AT_stmt_list (0x0000000d) + - Offset: 0x000000000000022F + Symbol: v0100000000000000 + Type: R_RISCV_SUB64 + - Name: .debug_abbrev + Type: SHT_PROGBITS + Content: 011101250E130B030E1B081101120710170000022E003F1903083A0B3B0B390B110112074018974219000000 + - Name: .debug_str + Type: SHT_PROGBITS + Flags: [ SHF_MERGE, SHF_STRINGS ] + EntSize: 0x0000000000000001 + Content: 546573742072656C6F636174696F6E732E00 +Symbols: + - Name: v1 + Type: STT_SECTION + Section: .debug_info + Value: 0x0000000000000001 + - Name: v4 + Type: STT_SECTION + Section: .debug_info + Value: 0x0000000000000004 + - Name: v04020103 + Type: STT_SECTION + Section: .debug_info + Value: 0x0000000004020103 + - Name: vFFFFFFFFFFFFFFFF + Type: STT_SECTION + Section: .debug_info + Value: 0xFFFFFFFFFFFFFFFF + - Name: v0100000000000000 + Type: STT_SECTION + Section: .debug_info + Value: 0x0100000000000000 +...