- Add AMDGPU DWARF proposal.
- Add references for gfx10 ISA and SemVer.
scott.linder b-sumner arsenm zoran.zaric echristo t-tye jdoerfert
- rG756ba3548cbe: [AMDGPU] DWARF proposal review feedback
rG1eac2c55d861: [AMDGPU] Move DWARF proposal to separate file
rG1b58cbad018c: [AMDGPU] DWARF For Heterogeneous Debugging
rGb43612401077: [AMDGPU] Update DWARF proposal
rG926a2fa6f638: [AMDGPU] Update AMDGPUUsage with DWARF proposal
rG084f3cf92b95: [AMDGPU] Update DWARF proposal encodings
rGf5678d4a6a60: [AMDGPU] Update AMDGPUUsage with DWARF proposal
rGb4668a268dde: [AMDGPU] DWARF Proposal For Heterogeneous Debugging
Add DW_OP_LLVM_call_frame_entry_reg and fix typos
- Add DW_OP_LLVM_call_frame_entry_reg needed for CFI unwinding of VGPRs that are spilled using the EXEC mask on entry.
- Remove mention of DW_OP_* that are no longer part of the proposal.
- Correct some names and other minor typos.
I think this is at a stage where it is OK to commit it to AMDGPUUsage as a draft proposal, to let us iterate on it before actually proposing it to DWARF proper. It is harder to start a discussion about it without a public document describing it, and it seems easier to refer to it in AMDGPUUsage than to refer to a Phabricator review.
[AMDGPU] Update DWARF proposal
- Unify the sections on DWARF expression and location lists.
- Allow a location description to have one or more single location descriptions.
- Define context of DWARF expression that includes an initial stack. Allow initial stack to be used when evaluating location list expression with overlapping PC ranges.
- Reorganize the DWARF proposal in AMDGPUUsage so suitable for submission to the DWARF site.
- Replace CFI instruction DW_CFA_LLVM_def_cfa_aspace with DW_CFA_def_aspace_cfa and DW_CFA_def_aspace_cfa_sf. This is to avoid the problem that DW_CFA_def_cfa and DW_CFA_def_cfa_sf cannot use a register that is not the size of an address in the CFA address space.
- Clarify DWARF address class and DWARF address space. Define language values for DWARF address classes and specify how they are used by some common source languages.
- Define rules for accessing registers and derefencing memory when the type size and register size or byte size operand do not match.
- Numerous cleanups for consistency.
Enthusiastic LGTM. :)
I would love to see this formally written up and passed along to the committee. Feel free to talk to me, Paul, Adrian, or a few others if you need or want any help.
Hi @echristo, Yes that is what I am currently doing. This update is to bring the proposal in line with a form I hope is ready for submission by moving the AMDGPU specific parts out of the proposal into their own section, reordering the sections to match the current DWARF 5 spec order, and adding DWARF 5 section numbers for where the changes apply. There is one more review to move the whole section into a separate file, and add some references. Then I plan to submit to the DWARF issue queue. Some committee members have already reviewed earlier revisions and their feedback has been incorporated. Please let me know if there is anything else you think needs to be done prior to submission.
[AMDGPU] DWARF proposal review feedback
- Rename DW_OP_LLVM_offset_constu to DW_OP_LLVM_offset_uconst to matches DW_OP_plus_uconst.
- Correct DW_OP_LLVM_call_ref to be DW_OP_call_ref.
- Move proposed changes to a separate section to clarify that the introduction section is not part of the changes.
- Fix formatting typos and add missing reference.
- Clarify why DW_OP_LLVM_offset et al do not wrap on overflow.
- Correct syntax of augmentation string.
We have just continued to update this differential for all the changes to the proposal document. We wanted to make it easy for people to track the development by just looking through the diffs here.
The latest diff hasn't been committed, so I will commit that and close this. For future diffs in the document I guess we could just create a new differential and "stack" it on top of this one?