Index: llvm/lib/Target/PowerPC/PPC.h =================================================================== --- llvm/lib/Target/PowerPC/PPC.h +++ llvm/lib/Target/PowerPC/PPC.h @@ -34,7 +34,7 @@ #ifndef NDEBUG FunctionPass *createPPCCTRLoopsVerify(); #endif - FunctionPass *createPPCLoopPreIncPrepPass(PPCTargetMachine &TM); + FunctionPass *createPPCLoopInstrFormPrepPass(PPCTargetMachine &TM); FunctionPass *createPPCTOCRegDepsPass(); FunctionPass *createPPCEarlyReturnPass(); FunctionPass *createPPCVSXCopyPass(); @@ -60,7 +60,7 @@ #ifndef NDEBUG void initializePPCCTRLoopsVerifyPass(PassRegistry&); #endif - void initializePPCLoopPreIncPrepPass(PassRegistry&); + void initializePPCLoopInstrFormPrepPass(PassRegistry&); void initializePPCTOCRegDepsPass(PassRegistry&); void initializePPCEarlyReturnPass(PassRegistry&); void initializePPCVSXCopyPass(PassRegistry&); Index: llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp +++ llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp @@ -1,4 +1,4 @@ -//===------ PPCLoopPreIncPrep.cpp - Loop Pre-Inc. AM Prep. Pass -----------===// +//===------ PPCLoopInstrFormPrep.cpp - Loop Instr Form Prep Pass ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -41,7 +41,7 @@ // *++p = c; //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "ppc-loop-preinc-prep" +#define DEBUG_TYPE "ppc-loop-instr-form-prep" #include "PPC.h" #include "PPCSubtarget.h" @@ -148,16 +148,16 @@ // For DQ form instructions, their displacements must be multiple of 16. enum InstrForm { UpdateForm = 1, DSForm = 4, DQForm = 16 }; - class PPCLoopPreIncPrep : public FunctionPass { + class PPCLoopInstrFormPrep : public FunctionPass { public: static char ID; // Pass ID, replacement for typeid - PPCLoopPreIncPrep() : FunctionPass(ID) { - initializePPCLoopPreIncPrepPass(*PassRegistry::getPassRegistry()); + PPCLoopInstrFormPrep() : FunctionPass(ID) { + initializePPCLoopInstrFormPrepPass(*PassRegistry::getPassRegistry()); } - PPCLoopPreIncPrep(PPCTargetMachine &TM) : FunctionPass(ID), TM(&TM) { - initializePPCLoopPreIncPrepPass(*PassRegistry::getPassRegistry()); + PPCLoopInstrFormPrep(PPCTargetMachine &TM) : FunctionPass(ID), TM(&TM) { + initializePPCLoopInstrFormPrepPass(*PassRegistry::getPassRegistry()); } void getAnalysisUsage(AnalysisUsage &AU) const override { @@ -237,20 +237,20 @@ } // end anonymous namespace -char PPCLoopPreIncPrep::ID = 0; -static const char *name = "Prepare loop for pre-inc. addressing modes"; -INITIALIZE_PASS_BEGIN(PPCLoopPreIncPrep, DEBUG_TYPE, name, false, false) +char PPCLoopInstrFormPrep::ID = 0; +static const char *name = "Prepare loop for ppc preferred instruction forms"; +INITIALIZE_PASS_BEGIN(PPCLoopInstrFormPrep, DEBUG_TYPE, name, false, false) INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass) -INITIALIZE_PASS_END(PPCLoopPreIncPrep, DEBUG_TYPE, name, false, false) +INITIALIZE_PASS_END(PPCLoopInstrFormPrep, DEBUG_TYPE, name, false, false) static const std::string PHINodeNameSuffix = ".phi"; static const std::string CastNodeNameSuffix = ".cast"; static const std::string GEPNodeIncNameSuffix = ".inc"; static const std::string GEPNodeOffNameSuffix = ".off"; -FunctionPass *llvm::createPPCLoopPreIncPrepPass(PPCTargetMachine &TM) { - return new PPCLoopPreIncPrep(TM); +FunctionPass *llvm::createPPCLoopInstrFormPrepPass(PPCTargetMachine &TM) { + return new PPCLoopInstrFormPrep(TM); } static bool IsPtrInBounds(Value *BasePtr) { @@ -284,7 +284,7 @@ return nullptr; } -bool PPCLoopPreIncPrep::runOnFunction(Function &F) { +bool PPCLoopInstrFormPrep::runOnFunction(Function &F) { if (skipFunction(F)) return false; @@ -305,7 +305,7 @@ return MadeChange; } -void PPCLoopPreIncPrep::addOneCandidate(Instruction *MemI, const SCEV *LSCEV, +void PPCLoopInstrFormPrep::addOneCandidate(Instruction *MemI, const SCEV *LSCEV, SmallVector &Buckets, unsigned MaxCandidateNum) { assert((MemI && GetPointerOperand(MemI)) && @@ -328,7 +328,7 @@ } } -SmallVector PPCLoopPreIncPrep::collectCandidates( +SmallVector PPCLoopInstrFormPrep::collectCandidates( Loop *L, std::function isValidCandidate, unsigned MaxCandidateNum) { @@ -369,7 +369,7 @@ return Buckets; } -bool PPCLoopPreIncPrep::prepareBaseForDispFormChain(Bucket &BucketChain, +bool PPCLoopInstrFormPrep::prepareBaseForDispFormChain(Bucket &BucketChain, InstrForm Form) { // RemainderOffsetInfo details: // key: value of (Offset urem DispConstraint). For DSForm, it can @@ -444,7 +444,7 @@ // {-32769, 2003, 2007, 2011}, we choose -32769 as base offset, and left disp // for load/stores are {0, 34772, 34776, 34780}. Though each offset now is a // multipler of 4, it cannot be represented by sint16. -bool PPCLoopPreIncPrep::prepareBaseForUpdateFormChain(Bucket &BucketChain) { +bool PPCLoopInstrFormPrep::prepareBaseForUpdateFormChain(Bucket &BucketChain) { // We have a choice now of which instruction's memory operand we use as the // base for the generated PHI. Always picking the first instruction in each // bucket does not work well, specifically because that instruction might @@ -484,7 +484,7 @@ return true; } -bool PPCLoopPreIncPrep::rewriteLoadStores(Loop *L, Bucket &BucketChain, +bool PPCLoopInstrFormPrep::rewriteLoadStores(Loop *L, Bucket &BucketChain, SmallSet &BBChanged, InstrForm Form) { bool MadeChange = false; @@ -676,7 +676,7 @@ return MadeChange; } -bool PPCLoopPreIncPrep::updateFormPrep(Loop *L, +bool PPCLoopInstrFormPrep::updateFormPrep(Loop *L, SmallVector &Buckets) { bool MadeChange = false; if (Buckets.empty()) @@ -695,7 +695,7 @@ return MadeChange; } -bool PPCLoopPreIncPrep::dispFormPrep(Loop *L, SmallVector &Buckets, +bool PPCLoopInstrFormPrep::dispFormPrep(Loop *L, SmallVector &Buckets, InstrForm Form) { bool MadeChange = false; @@ -721,7 +721,7 @@ // This function will check to see if that PHI already exists and will return // true if it found an existing PHI with the matched start and increment as the // one we wanted to create. -bool PPCLoopPreIncPrep::alreadyPrepared(Loop *L, Instruction* MemI, +bool PPCLoopInstrFormPrep::alreadyPrepared(Loop *L, Instruction* MemI, const SCEV *BasePtrStartSCEV, const SCEVConstant *BasePtrIncSCEV, InstrForm Form) { @@ -787,7 +787,7 @@ return false; } -bool PPCLoopPreIncPrep::runOnLoop(Loop *L) { +bool PPCLoopInstrFormPrep::runOnLoop(Loop *L) { bool MadeChange = false; // Only prep. the inner-most loop Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -51,8 +51,8 @@ cl::desc("Disable CTR loops for PPC")); static cl:: -opt DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, - cl::desc("Disable PPC loop preinc prep")); +opt DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden, + cl::desc("Disable PPC loop instr form prep")); static cl::opt VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", @@ -104,7 +104,7 @@ #ifndef NDEBUG initializePPCCTRLoopsVerifyPass(PR); #endif - initializePPCLoopPreIncPrepPass(PR); + initializePPCLoopInstrFormPrepPass(PR); initializePPCTOCRegDepsPass(PR); initializePPCEarlyReturnPass(PR); initializePPCVSXCopyPass(PR); @@ -431,8 +431,8 @@ } bool PPCPassConfig::addPreISel() { - if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None) - addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine())); + if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None) + addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine())); if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) addPass(createHardwareLoopsPass()); Index: llvm/test/CodeGen/PowerPC/addi-licm.ll =================================================================== --- llvm/test/CodeGen/PowerPC/addi-licm.ll +++ llvm/test/CodeGen/PowerPC/addi-licm.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -disable-ppc-preinc-prep < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -disable-ppc-instr-form-prep < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PIP target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" Index: llvm/test/CodeGen/PowerPC/ppc-passname.ll =================================================================== --- llvm/test/CodeGen/PowerPC/ppc-passname.ll +++ llvm/test/CodeGen/PowerPC/ppc-passname.ll @@ -1,13 +1,13 @@ -; Test pass name: ppc-loop-preinc-prep. -; RUN: llc -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-before=ppc-loop-preinc-prep -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-BEFORE-LOOP-PREINC-PREP -; STOP-BEFORE-LOOP-PREINC-PREP-NOT: -ppc-loop-preinc-prep -; STOP-BEFORE-LOOP-PREINC-PREP-NOT: "ppc-loop-preinc-prep" pass is not registered. -; STOP-BEFORE-LOOP-PREINC-PREP-NOT: Prepare loop for pre-inc. addressing modes - -; RUN: llc -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-after=ppc-loop-preinc-prep -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-LOOP-PREINC-PREP -; STOP-AFTER-LOOP-PREINC-PREP: -ppc-loop-preinc-prep -; STOP-AFTER-LOOP-PREINC-PREP-NOT: "ppc-loop-preinc-prep" pass is not registered. -; STOP-AFTER-LOOP-PREINC-PREP: Prepare loop for pre-inc. addressing modes +; Test pass name: ppc-loop-instr-form-prep. +; RUN: llc -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-before=ppc-loop-instr-form-prep -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-BEFORE-LOOP-INSTR-FORM-PREP +; STOP-BEFORE-LOOP-INSTR-FORM-PREP-NOT: -ppc-loop-instr-form-prep +; STOP-BEFORE-LOOP-INSTR-FORM-PREP-NOT: "ppc-loop-instr-form-prep" pass is not registered. +; STOP-BEFORE-LOOP-INSTR-FORM-PREP-NOT: Prepare loop for ppc preferred instruction forms + +; RUN: llc -mtriple=powerpc64le-unknown-unknown < %s -debug-pass=Structure -stop-after=ppc-loop-instr-form-prep -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-LOOP-INSTR-FORM-PREP +; STOP-AFTER-LOOP-INSTR-FORM-PREP: -ppc-loop-instr-form-prep +; STOP-AFTER-LOOP-INSTR-FORM-PREP-NOT: "ppc-loop-instr-form-prep" pass is not registered. +; STOP-AFTER-LOOP-INSTR-FORM-PREP: Prepare loop for ppc preferred instruction forms ; Test pass name: ppc-toc-reg-deps.