Index: llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h =================================================================== --- llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h +++ llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h @@ -573,7 +573,8 @@ assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); if (!MO.isReg() || - &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum)) != + &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum), + MRI.getType(MO.getReg())) != RBI.getRegBank(MO.getReg(), MRI, TRI)) { if (handleReject() == RejectAndGiveUp) return false; Index: llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h =================================================================== --- llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -20,6 +20,7 @@ #include "llvm/ADT/iterator_range.h" #include "llvm/CodeGen/Register.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/LowLevelTypeImpl.h" #include #include #include @@ -543,7 +544,7 @@ const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, - const TargetRegisterInfo &TRI) const; + const MachineRegisterInfo &MRI) const; /// Helper method to apply something that is like the default mapping. /// Basically, that means that \p OpdMapper.getMI() is left untouched @@ -599,7 +600,7 @@ /// /// \todo This should be TableGen'ed. virtual const RegisterBank & - getRegBankFromRegClass(const TargetRegisterClass &RC) const { + getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const { llvm_unreachable("The target must override this method"); } Index: llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp =================================================================== --- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -82,15 +82,18 @@ const RegisterBank * RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const { - if (Register::isPhysicalRegister(Reg)) - return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI)); + if (Register::isPhysicalRegister(Reg)) { + // FIXME: This was probably a copy to a virtual register that does have a + // type we could use. + return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT()); + } assert(Reg && "NoRegister does not have a register bank"); const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); if (auto *RB = RegClassOrBank.dyn_cast()) return RB; if (auto *RC = RegClassOrBank.dyn_cast()) - return &getRegBankFromRegClass(*RC); + return &getRegBankFromRegClass(*RC, MRI.getType(Reg)); return nullptr; } @@ -108,15 +111,18 @@ const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, - const TargetRegisterInfo &TRI) const { + const MachineRegisterInfo &MRI) const { + const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); + // The mapping of the registers may be available via the // register class constraints. - const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); + const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); if (!RC) return nullptr; - const RegisterBank &RegBank = getRegBankFromRegClass(*RC); + Register Reg = MI.getOperand(OpIdx).getReg(); + const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); // Sanity check that the target properly implemented getRegBankFromRegClass. assert(RegBank.covers(*RC) && "The mapping of the register bank does not make sense"); @@ -195,7 +201,7 @@ if (!CurRegBank) { // If this is a target specific instruction, we can deduce // the register bank from the encoding constraints. - CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI); + CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI); if (!CurRegBank) { // All our attempts failed, give up. CompleteMapping = false; Index: llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h +++ llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h @@ -132,8 +132,8 @@ unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override; - const RegisterBank & - getRegBankFromRegClass(const TargetRegisterClass &RC) const override; + const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const override; InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override; Index: llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -222,8 +222,9 @@ return RegisterBankInfo::copyCost(A, B, Size); } -const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( - const TargetRegisterClass &RC) const { +const RegisterBank & +AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const { switch (RC.getID()) { case AArch64::FPR8RegClassID: case AArch64::FPR16RegClassID: Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h @@ -149,8 +149,8 @@ unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank = nullptr) const override; - const RegisterBank & - getRegBankFromRegClass(const TargetRegisterClass &RC) const override; + const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const override; InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override; Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -164,8 +164,9 @@ return 1; } -const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass( - const TargetRegisterClass &RC) const { +const RegisterBank & +AMDGPURegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT Ty) const { if (&RC == &AMDGPU::SReg_1RegClass) return AMDGPU::VCCRegBank; Index: llvm/lib/Target/ARM/ARMRegisterBankInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMRegisterBankInfo.h +++ llvm/lib/Target/ARM/ARMRegisterBankInfo.h @@ -32,8 +32,8 @@ public: ARMRegisterBankInfo(const TargetRegisterInfo &TRI); - const RegisterBank & - getRegBankFromRegClass(const TargetRegisterClass &RC) const override; + const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const override; const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override; Index: llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -172,8 +172,9 @@ #endif } -const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass( - const TargetRegisterClass &RC) const { +const RegisterBank & +ARMRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const { using namespace ARM; switch (RC.getID()) { Index: llvm/lib/Target/Mips/MipsRegisterBankInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsRegisterBankInfo.h +++ llvm/lib/Target/Mips/MipsRegisterBankInfo.h @@ -32,8 +32,8 @@ public: MipsRegisterBankInfo(const TargetRegisterInfo &TRI); - const RegisterBank & - getRegBankFromRegClass(const TargetRegisterClass &RC) const override; + const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const override; const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override; Index: llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -76,8 +76,9 @@ MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) : MipsGenRegisterBankInfo() {} -const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass( - const TargetRegisterClass &RC) const { +const RegisterBank & +MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const { using namespace Mips; switch (RC.getID()) { Index: llvm/lib/Target/X86/X86RegisterBankInfo.h =================================================================== --- llvm/lib/Target/X86/X86RegisterBankInfo.h +++ llvm/lib/Target/X86/X86RegisterBankInfo.h @@ -64,8 +64,8 @@ public: X86RegisterBankInfo(const TargetRegisterInfo &TRI); - const RegisterBank & - getRegBankFromRegClass(const TargetRegisterClass &RC) const override; + const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const override; InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override; Index: llvm/lib/Target/X86/X86RegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -40,8 +40,9 @@ assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit"); } -const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass( - const TargetRegisterClass &RC) const { +const RegisterBank & +X86RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, + LLT) const { if (X86::GR8RegClass.hasSubClassEq(&RC) || X86::GR16RegClass.hasSubClassEq(&RC) ||