Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1953,6 +1953,41 @@
 def MVE_VQNEGs16 : MVE_VQABSNEG<"vqneg", "s16", 0b01, 0b1>;
 def MVE_VQNEGs32 : MVE_VQABSNEG<"vqneg", "s32", 0b10, 0b1>;
 
+// int_min/int_max: vector containing INT_MIN/INT_MAX VTI.Size times
+// zero_vec: v4i32-initialized zero vector, potentially wrapped in a bitconvert
+multiclass vqabs_pattern<MVEVectorVTInfo VTI, dag int_min, dag int_max,
+                         dag zero_vec, MVE_VQABSNEG vqabs_instruction> {
+  // The below tree can be replaced by a vqabs instruction, as it represents
+  // the following vectorized expression (r being the value in $reg):
+  // r > 0 ? r : (r == INT_MIN ? INT_MAX : -r)
+  let Predicates = [HasMVEInt] in {
+    def : Pat<(VTI.Vec (vselect
+                      (VTI.Pred (ARMvcmpz (VTI.Vec MQPR:$reg), (i32 12))),
+                      (VTI.Vec MQPR:$reg),
+                      (VTI.Vec (vselect
+                                (VTI.Pred (ARMvcmp (VTI.Vec MQPR:$reg), int_min, (i32 0))),
+                                int_max,
+                                (sub (VTI.Vec zero_vec), (VTI.Vec MQPR:$reg)))))),
+            (VTI.Vec (vqabs_instruction (VTI.Vec MQPR:$reg)))>;
+  }
+}
+
+defm MVE_VQABS_Ps8  : vqabs_pattern<MVE_v16i8,
+                                    (v16i8 (ARMvmovImm (i32 3712))),
+                                    (v16i8 (ARMvmovImm (i32 3711))),
+                                    (bitconvert (v4i32 (ARMvmovImm (i32 0)))),
+                                    MVE_VQABSs8>;
+defm MVE_VQABS_Ps16 : vqabs_pattern<MVE_v8i16,
+                                    (v8i16 (ARMvmovImm (i32 2688))),
+                                    (v8i16 (ARMvmvnImm (i32 2688))),
+                                    (bitconvert (v4i32 (ARMvmovImm (i32 0)))),
+                                    MVE_VQABSs16>;
+defm MVE_VQABS_Ps32 : vqabs_pattern<MVE_v4i32,
+                                    (v4i32 (ARMvmovImm (i32 1664))),
+                                    (v4i32 (ARMvmvnImm (i32 1664))),
+                                    (ARMvmovImm (i32 0)),
+                                    MVE_VQABSs32>;
+
 class MVE_mod_imm<string iname, string suffix, bits<4> cmode, bit op,
                   dag iops, list<dag> pattern=[]>
   : MVE_p<(outs MQPR:$Qd), iops, NoItinerary, iname, suffix, "$Qd, $imm",
Index: llvm/test/CodeGen/Thumb2/vqabs.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/vqabs.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc <16 x i8> @vqabs_test16(<16 x i8> %A) nounwind {
+; CHECK-LABEL: vqabs_test16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqabs.s8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+
+  %0 = icmp sgt <16 x i8> %A, zeroinitializer
+  %1 = icmp eq <16 x i8> %A, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
+  %2 = sub nsw <16 x i8> zeroinitializer, %A
+  %3 = select <16 x i1> %1, <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>, <16 x i8> %2
+  %4 = select <16 x i1> %0, <16 x i8> %A, <16 x i8> %3
+  
+  ret <16 x i8> %4
+}
+
+define arm_aapcs_vfpcc <8 x i16> @vqabs_test8(<8 x i16> %A) nounwind {
+; CHECK-LABEL: vqabs_test8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqabs.s16 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+
+  %0 = icmp sgt <8 x i16> %A, zeroinitializer
+  %1 = icmp eq <8 x i16> %A, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
+  %2 = sub nsw <8 x i16> zeroinitializer, %A
+  %3 = select <8 x i1> %1, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>, <8 x i16> %2
+  %4 = select <8 x i1> %0, <8 x i16> %A, <8 x i16> %3
+  
+  ret <8 x i16> %4
+}
+
+define arm_aapcs_vfpcc <4 x i32> @vqabs_test4(<4 x i32> %A) nounwind {
+; CHECK-LABEL: vqabs_test4:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vqabs.s32 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+
+  %0 = icmp sgt <4 x i32> %A, zeroinitializer
+  %1 = icmp eq <4 x i32> %A, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+  %2 = sub nsw <4 x i32> zeroinitializer, %A
+  %3 = select <4 x i1> %1, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %2
+  %4 = select <4 x i1> %0, <4 x i32> %A, <4 x i32> %3
+  
+  ret <4 x i32> %4
+}
+