Index: llvm/lib/Target/ARM/ARM.td
===================================================================
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -65,7 +65,7 @@
     description#" with only 16 d-registers and no double precision",
     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
       !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
-      otherimplies>;
+      otherimplies # [FeatureFPRegs64]>;
   def _SP: SubtargetFeature<
     name#"sp", query#"SP", "true",
     description#" with no double precision",
Index: llvm/test/MC/ARM/mve-fp-registers.s
===================================================================
--- llvm/test/MC/ARM/mve-fp-registers.s
+++ llvm/test/MC/ARM/mve-fp-registers.s
@@ -27,7 +27,7 @@
 // the FP64 instructions are optional. They are also limited to 16 D registers,
 // but we don't test that here.
 // RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4d16sp 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32
-// RUN: FileCheck %s < %t --check-prefix=NOFP16 --check-prefix=NOFP64
+// RUN: FileCheck %s < %t --check-prefix=NOFP16
 // RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4,-d32 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
 // RUN: FileCheck %s < %t --check-prefix=NOFP16