diff --git a/llvm/test/CodeGen/RISCV/srem-lkk.ll b/llvm/test/CodeGen/RISCV/srem-lkk.ll
--- a/llvm/test/CodeGen/RISCV/srem-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-lkk.ll
@@ -8,19 +8,15 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK,RV64IM %s
 
-define i32 @fold_srem_positive_odd(i32 %x) {
+define i32 @fold_srem_positive_odd(i32 %x) nounwind {
 ; RV32I-LABEL: fold_srem_positive_odd:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_positive_odd:
@@ -35,22 +31,17 @@
 ; RV32IM-NEXT:    addi a2, zero, 95
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_positive_odd:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    addi a1, zero, 95
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_positive_odd:
@@ -72,26 +63,21 @@
 ; RV64IM-NEXT:    addi a2, zero, 95
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 95
   ret i32 %1
 }
 
 
-define i32 @fold_srem_positive_even(i32 %x) {
+define i32 @fold_srem_positive_even(i32 %x) nounwind {
 ; RV32I-LABEL: fold_srem_positive_even:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a1, zero, 1060
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_positive_even:
@@ -105,22 +91,17 @@
 ; RV32IM-NEXT:    addi a2, zero, 1060
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_positive_even:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    addi a1, zero, 1060
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_positive_even:
@@ -139,26 +120,21 @@
 ; RV64IM-NEXT:    addi a2, zero, 1060
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 1060
   ret i32 %1
 }
 
 
-define i32 @fold_srem_negative_odd(i32 %x) {
+define i32 @fold_srem_negative_odd(i32 %x) nounwind {
 ; RV32I-LABEL: fold_srem_negative_odd:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a1, zero, -723
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_negative_odd:
@@ -172,22 +148,17 @@
 ; RV32IM-NEXT:    addi a2, zero, -723
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_negative_odd:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    addi a1, zero, -723
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_negative_odd:
@@ -209,27 +180,22 @@
 ; RV64IM-NEXT:    addi a2, zero, -723
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, -723
   ret i32 %1
 }
 
 
-define i32 @fold_srem_negative_even(i32 %x) {
+define i32 @fold_srem_negative_even(i32 %x) nounwind {
 ; RV32I-LABEL: fold_srem_negative_even:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    lui a1, 1048570
 ; RV32I-NEXT:    addi a1, a1, 1595
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_negative_even:
@@ -244,23 +210,18 @@
 ; RV32IM-NEXT:    addi a2, a2, 1595
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_negative_even:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    lui a1, 1048570
 ; RV64I-NEXT:    addiw a1, a1, 1595
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_negative_even:
@@ -282,7 +243,6 @@
 ; RV64IM-NEXT:    addiw a2, a2, 1595
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, -22981
   ret i32 %1
@@ -290,17 +250,13 @@
 
 
 ; Don't fold if we can combine srem with sdiv.
-define i32 @combine_srem_sdiv(i32 %x) {
+define i32 @combine_srem_sdiv(i32 %x) nounwind {
 ; RV32I-LABEL: combine_srem_sdiv:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    sw s1, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __modsi3
@@ -312,11 +268,7 @@
 ; RV32I-NEXT:    lw s1, 4(sp)
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_srem_sdiv:
@@ -332,19 +284,14 @@
 ; RV32IM-NEXT:    mul a2, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a2
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_srem_sdiv:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    .cfi_def_cfa_offset 32
 ; RV64I-NEXT:    sd ra, 24(sp)
 ; RV64I-NEXT:    sd s0, 16(sp)
 ; RV64I-NEXT:    sd s1, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
 ; RV64I-NEXT:    sext.w s0, a0
 ; RV64I-NEXT:    addi a1, zero, 95
 ; RV64I-NEXT:    mv a0, s0
@@ -357,11 +304,7 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    ld s0, 16(sp)
 ; RV64I-NEXT:    ld ra, 24(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
 ; RV64I-NEXT:    addi sp, sp, 32
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_srem_sdiv:
@@ -384,7 +327,6 @@
 ; RV64IM-NEXT:    mul a2, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a2
 ; RV64IM-NEXT:    addw a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 95
   %2 = sdiv i32 %x, 95
@@ -393,7 +335,7 @@
 }
 
 ; Don't fold for divisors that are a power of two.
-define i32 @dont_fold_srem_power_of_two(i32 %x) {
+define i32 @dont_fold_srem_power_of_two(i32 %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_power_of_two:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
@@ -401,7 +343,6 @@
 ; RV32I-NEXT:    add a1, a0, a1
 ; RV32I-NEXT:    andi a1, a1, -64
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_power_of_two:
@@ -411,7 +352,6 @@
 ; RV32IM-NEXT:    add a1, a0, a1
 ; RV32IM-NEXT:    andi a1, a1, -64
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_power_of_two:
@@ -425,7 +365,6 @@
 ; RV64I-NEXT:    addi a2, a2, -64
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_power_of_two:
@@ -439,25 +378,23 @@
 ; RV64IM-NEXT:    addi a2, a2, -64
 ; RV64IM-NEXT:    and a1, a1, a2
 ; RV64IM-NEXT:    subw a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 64
   ret i32 %1
 }
 
 ; Don't fold if the divisor is one.
-define i32 @dont_fold_srem_one(i32 %x) {
+define i32 @dont_fold_srem_one(i32 %x) nounwind {
 ; CHECK-LABEL: dont_fold_srem_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mv a0, zero
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = srem i32 %x, 1
   ret i32 %1
 }
 
 ; Don't fold if the divisor is 2^31.
-define i32 @dont_fold_srem_i32_smax(i32 %x) {
+define i32 @dont_fold_srem_i32_smax(i32 %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_i32_smax:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
@@ -466,7 +403,6 @@
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i32_smax:
@@ -477,7 +413,6 @@
 ; RV32IM-NEXT:    lui a2, 524288
 ; RV32IM-NEXT:    and a1, a1, a2
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i32_smax:
@@ -492,7 +427,6 @@
 ; RV64I-NEXT:    slli a2, a2, 31
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i32_smax:
@@ -507,56 +441,43 @@
 ; RV64IM-NEXT:    slli a2, a2, 31
 ; RV64IM-NEXT:    and a1, a1, a2
 ; RV64IM-NEXT:    addw a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 2147483648
   ret i32 %1
 }
 
 ; Don't fold i64 srem
-define i64 @dont_fold_srem_i64(i64 %x) {
+define i64 @dont_fold_srem_i64(i64 %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a2, zero, 98
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __moddi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
-; RV32IM-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IM-NEXT:    sw ra, 12(sp)
-; RV32IM-NEXT:    .cfi_offset ra, -4
 ; RV32IM-NEXT:    addi a2, zero, 98
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __moddi3
 ; RV32IM-NEXT:    lw ra, 12(sp)
-; RV32IM-NEXT:    .cfi_restore ra
 ; RV32IM-NEXT:    addi sp, sp, 16
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    addi a1, zero, 98
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i64:
@@ -576,7 +497,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 98
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i64 %x, 98
   ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
--- a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
@@ -8,11 +8,10 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK,RV64IM %s
 
-define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
+define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: fold_srem_vec_1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
@@ -20,13 +19,6 @@
 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    sw s5, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
 ; RV32I-NEXT:    lh s2, 12(a1)
 ; RV32I-NEXT:    lh s3, 8(a1)
 ; RV32I-NEXT:    lh s0, 4(a1)
@@ -58,15 +50,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_vec_1:
@@ -117,13 +101,11 @@
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_vec_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    .cfi_def_cfa_offset 64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)
 ; RV64I-NEXT:    sd s1, 40(sp)
@@ -131,13 +113,6 @@
 ; RV64I-NEXT:    sd s3, 24(sp)
 ; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    sd s5, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
-; RV64I-NEXT:    .cfi_offset s4, -48
-; RV64I-NEXT:    .cfi_offset s5, -56
 ; RV64I-NEXT:    lh s2, 24(a1)
 ; RV64I-NEXT:    lh s3, 16(a1)
 ; RV64I-NEXT:    lh s0, 8(a1)
@@ -169,15 +144,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_vec_1:
@@ -252,17 +219,15 @@
 ; RV64IM-NEXT:    sh a3, 4(a0)
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a1, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
   ret <4 x i16> %1
 }
 
-define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
+define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: fold_srem_vec_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
@@ -270,13 +235,6 @@
 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    sw s5, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
 ; RV32I-NEXT:    lh s2, 12(a1)
 ; RV32I-NEXT:    lh s3, 8(a1)
 ; RV32I-NEXT:    lh s0, 4(a1)
@@ -308,15 +266,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_vec_2:
@@ -360,13 +310,11 @@
 ; RV32IM-NEXT:    sh a2, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh t0, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_vec_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    .cfi_def_cfa_offset 64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)
 ; RV64I-NEXT:    sd s1, 40(sp)
@@ -374,13 +322,6 @@
 ; RV64I-NEXT:    sd s3, 24(sp)
 ; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    sd s5, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
-; RV64I-NEXT:    .cfi_offset s4, -48
-; RV64I-NEXT:    .cfi_offset s5, -56
 ; RV64I-NEXT:    lh s2, 24(a1)
 ; RV64I-NEXT:    lh s3, 16(a1)
 ; RV64I-NEXT:    lh s0, 8(a1)
@@ -412,15 +353,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_vec_2:
@@ -470,7 +403,6 @@
 ; RV64IM-NEXT:    sh a2, 4(a0)
 ; RV64IM-NEXT:    sh a1, 2(a0)
 ; RV64IM-NEXT:    sh t0, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   ret <4 x i16> %1
@@ -478,11 +410,10 @@
 
 
 ; Don't fold if we can combine srem with sdiv.
-define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
+define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: combine_srem_sdiv:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    .cfi_def_cfa_offset 48
 ; RV32I-NEXT:    sw ra, 44(sp)
 ; RV32I-NEXT:    sw s0, 40(sp)
 ; RV32I-NEXT:    sw s1, 36(sp)
@@ -494,17 +425,6 @@
 ; RV32I-NEXT:    sw s7, 12(sp)
 ; RV32I-NEXT:    sw s8, 8(sp)
 ; RV32I-NEXT:    sw s9, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
-; RV32I-NEXT:    .cfi_offset s6, -32
-; RV32I-NEXT:    .cfi_offset s7, -36
-; RV32I-NEXT:    .cfi_offset s8, -40
-; RV32I-NEXT:    .cfi_offset s9, -44
 ; RV32I-NEXT:    lh s2, 0(a1)
 ; RV32I-NEXT:    lh s3, 4(a1)
 ; RV32I-NEXT:    lh s4, 8(a1)
@@ -560,19 +480,7 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_srem_sdiv:
@@ -620,13 +528,11 @@
 ; RV32IM-NEXT:    sh a2, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a4, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_srem_sdiv:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -96
-; RV64I-NEXT:    .cfi_def_cfa_offset 96
 ; RV64I-NEXT:    sd ra, 88(sp)
 ; RV64I-NEXT:    sd s0, 80(sp)
 ; RV64I-NEXT:    sd s1, 72(sp)
@@ -638,17 +544,6 @@
 ; RV64I-NEXT:    sd s7, 24(sp)
 ; RV64I-NEXT:    sd s8, 16(sp)
 ; RV64I-NEXT:    sd s9, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
-; RV64I-NEXT:    .cfi_offset s4, -48
-; RV64I-NEXT:    .cfi_offset s5, -56
-; RV64I-NEXT:    .cfi_offset s6, -64
-; RV64I-NEXT:    .cfi_offset s7, -72
-; RV64I-NEXT:    .cfi_offset s8, -80
-; RV64I-NEXT:    .cfi_offset s9, -88
 ; RV64I-NEXT:    lh s2, 0(a1)
 ; RV64I-NEXT:    lh s3, 8(a1)
 ; RV64I-NEXT:    lh s4, 16(a1)
@@ -704,19 +599,7 @@
 ; RV64I-NEXT:    ld s1, 72(sp)
 ; RV64I-NEXT:    ld s0, 80(sp)
 ; RV64I-NEXT:    ld ra, 88(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
-; RV64I-NEXT:    .cfi_restore s6
-; RV64I-NEXT:    .cfi_restore s7
-; RV64I-NEXT:    .cfi_restore s8
-; RV64I-NEXT:    .cfi_restore s9
 ; RV64I-NEXT:    addi sp, sp, 96
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_srem_sdiv:
@@ -770,7 +653,6 @@
 ; RV64IM-NEXT:    sh a1, 4(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a2, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -779,21 +661,15 @@
 }
 
 ; Don't fold for divisors that are a power of two.
-define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
+define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_power_of_two:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
 ; RV32I-NEXT:    sw s2, 16(sp)
 ; RV32I-NEXT:    sw s3, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lh a2, 0(a1)
 ; RV32I-NEXT:    lh a0, 12(a1)
@@ -829,13 +705,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_power_of_two:
@@ -877,23 +747,16 @@
 ; RV32IM-NEXT:    sh a2, 2(a0)
 ; RV32IM-NEXT:    sh a1, 0(a0)
 ; RV32IM-NEXT:    sh a7, 6(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_power_of_two:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lh a2, 0(a1)
 ; RV64I-NEXT:    lh a0, 24(a1)
@@ -929,13 +792,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_power_of_two:
@@ -983,28 +840,21 @@
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a1, 0(a0)
 ; RV64IM-NEXT:    sh a7, 6(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is one.
-define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
+define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
 ; RV32I-NEXT:    sw s2, 16(sp)
 ; RV32I-NEXT:    sw s3, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
 ; RV32I-NEXT:    lh s2, 12(a1)
 ; RV32I-NEXT:    lh s1, 8(a1)
 ; RV32I-NEXT:    lh a2, 4(a1)
@@ -1030,13 +880,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_one:
@@ -1078,23 +922,16 @@
 ; RV32IM-NEXT:    sh a2, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a3, 2(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    lh s2, 24(a1)
 ; RV64I-NEXT:    lh s1, 16(a1)
 ; RV64I-NEXT:    lh a2, 8(a1)
@@ -1120,13 +957,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_one:
@@ -1185,28 +1016,21 @@
 ; RV64IM-NEXT:    sh a2, 6(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is 2^15.
-define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
+define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: dont_fold_urem_i16_smax:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
 ; RV32I-NEXT:    sw s2, 16(sp)
 ; RV32I-NEXT:    sw s3, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
 ; RV32I-NEXT:    lh a2, 4(a1)
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lh s2, 12(a1)
@@ -1234,13 +1058,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_i16_smax:
@@ -1279,23 +1097,16 @@
 ; RV32IM-NEXT:    sh a1, 6(a0)
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a2, 2(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_i16_smax:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    lh a2, 8(a1)
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lh s2, 24(a1)
@@ -1323,13 +1134,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_i16_smax:
@@ -1380,18 +1185,16 @@
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a3, 6(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold i64 srem.
-define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
+define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind {
 ; RV32I-LABEL: dont_fold_srem_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    .cfi_def_cfa_offset 48
 ; RV32I-NEXT:    sw ra, 44(sp)
 ; RV32I-NEXT:    sw s0, 40(sp)
 ; RV32I-NEXT:    sw s1, 36(sp)
@@ -1403,17 +1206,6 @@
 ; RV32I-NEXT:    sw s7, 12(sp)
 ; RV32I-NEXT:    sw s8, 8(sp)
 ; RV32I-NEXT:    sw s9, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
-; RV32I-NEXT:    .cfi_offset s6, -32
-; RV32I-NEXT:    .cfi_offset s7, -36
-; RV32I-NEXT:    .cfi_offset s8, -40
-; RV32I-NEXT:    .cfi_offset s9, -44
 ; RV32I-NEXT:    lw s2, 24(a1)
 ; RV32I-NEXT:    lw s3, 28(a1)
 ; RV32I-NEXT:    lw s4, 16(a1)
@@ -1468,25 +1260,12 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -48
-; RV32IM-NEXT:    .cfi_def_cfa_offset 48
 ; RV32IM-NEXT:    sw ra, 44(sp)
 ; RV32IM-NEXT:    sw s0, 40(sp)
 ; RV32IM-NEXT:    sw s1, 36(sp)
@@ -1498,17 +1277,6 @@
 ; RV32IM-NEXT:    sw s7, 12(sp)
 ; RV32IM-NEXT:    sw s8, 8(sp)
 ; RV32IM-NEXT:    sw s9, 4(sp)
-; RV32IM-NEXT:    .cfi_offset ra, -4
-; RV32IM-NEXT:    .cfi_offset s0, -8
-; RV32IM-NEXT:    .cfi_offset s1, -12
-; RV32IM-NEXT:    .cfi_offset s2, -16
-; RV32IM-NEXT:    .cfi_offset s3, -20
-; RV32IM-NEXT:    .cfi_offset s4, -24
-; RV32IM-NEXT:    .cfi_offset s5, -28
-; RV32IM-NEXT:    .cfi_offset s6, -32
-; RV32IM-NEXT:    .cfi_offset s7, -36
-; RV32IM-NEXT:    .cfi_offset s8, -40
-; RV32IM-NEXT:    .cfi_offset s9, -44
 ; RV32IM-NEXT:    lw s2, 24(a1)
 ; RV32IM-NEXT:    lw s3, 28(a1)
 ; RV32IM-NEXT:    lw s4, 16(a1)
@@ -1563,35 +1331,17 @@
 ; RV32IM-NEXT:    lw s1, 36(sp)
 ; RV32IM-NEXT:    lw s0, 40(sp)
 ; RV32IM-NEXT:    lw ra, 44(sp)
-; RV32IM-NEXT:    .cfi_restore ra
-; RV32IM-NEXT:    .cfi_restore s0
-; RV32IM-NEXT:    .cfi_restore s1
-; RV32IM-NEXT:    .cfi_restore s2
-; RV32IM-NEXT:    .cfi_restore s3
-; RV32IM-NEXT:    .cfi_restore s4
-; RV32IM-NEXT:    .cfi_restore s5
-; RV32IM-NEXT:    .cfi_restore s6
-; RV32IM-NEXT:    .cfi_restore s7
-; RV32IM-NEXT:    .cfi_restore s8
-; RV32IM-NEXT:    .cfi_restore s9
 ; RV32IM-NEXT:    addi sp, sp, 48
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    ld s2, 24(a1)
 ; RV64I-NEXT:    ld s1, 16(a1)
 ; RV64I-NEXT:    ld a2, 8(a1)
@@ -1617,13 +1367,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i64:
@@ -1682,7 +1426,6 @@
 ; RV64IM-NEXT:    sd a2, 24(a0)
 ; RV64IM-NEXT:    sd a3, 8(a0)
 ; RV64IM-NEXT:    sd a1, 16(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
   ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/RISCV/urem-lkk.ll b/llvm/test/CodeGen/RISCV/urem-lkk.ll
--- a/llvm/test/CodeGen/RISCV/urem-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/urem-lkk.ll
@@ -8,19 +8,15 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK,RV64IM %s
 
-define i32 @fold_urem_positive_odd(i32 %x) {
+define i32 @fold_urem_positive_odd(i32 %x) nounwind {
 ; RV32I-LABEL: fold_urem_positive_odd:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_positive_odd:
@@ -35,23 +31,18 @@
 ; RV32IM-NEXT:    addi a2, zero, 95
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_positive_odd:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    addi a1, zero, 95
 ; RV64I-NEXT:    call __umoddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_positive_odd:
@@ -74,26 +65,21 @@
 ; RV64IM-NEXT:    addi a2, zero, 95
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 95
   ret i32 %1
 }
 
 
-define i32 @fold_urem_positive_even(i32 %x) {
+define i32 @fold_urem_positive_even(i32 %x) nounwind {
 ; RV32I-LABEL: fold_urem_positive_even:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a1, zero, 1060
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_positive_even:
@@ -105,23 +91,18 @@
 ; RV32IM-NEXT:    addi a2, zero, 1060
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_positive_even:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    addi a1, zero, 1060
 ; RV64I-NEXT:    call __umoddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_positive_even:
@@ -141,7 +122,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 1060
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 1060
   ret i32 %1
@@ -149,17 +129,13 @@
 
 
 ; Don't fold if we can combine urem with udiv.
-define i32 @combine_urem_udiv(i32 %x) {
+define i32 @combine_urem_udiv(i32 %x) nounwind {
 ; RV32I-LABEL: combine_urem_udiv:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    sw s1, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __umodsi3
@@ -171,11 +147,7 @@
 ; RV32I-NEXT:    lw s1, 4(sp)
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_urem_udiv:
@@ -191,19 +163,14 @@
 ; RV32IM-NEXT:    mul a2, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a2
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_urem_udiv:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    .cfi_def_cfa_offset 32
 ; RV64I-NEXT:    sd ra, 24(sp)
 ; RV64I-NEXT:    sd s0, 16(sp)
 ; RV64I-NEXT:    sd s1, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli s0, a0, 32
 ; RV64I-NEXT:    addi a1, zero, 95
@@ -217,11 +184,7 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    ld s0, 16(sp)
 ; RV64I-NEXT:    ld ra, 24(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
 ; RV64I-NEXT:    addi sp, sp, 32
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_urem_udiv:
@@ -245,7 +208,6 @@
 ; RV64IM-NEXT:    mul a2, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a2
 ; RV64IM-NEXT:    add a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 95
   %2 = udiv i32 %x, 95
@@ -254,81 +216,66 @@
 }
 
 ; Don't fold for divisors that are a power of two.
-define i32 @dont_fold_urem_power_of_two(i32 %x) {
+define i32 @dont_fold_urem_power_of_two(i32 %x) nounwind {
 ; CHECK-LABEL: dont_fold_urem_power_of_two:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a0, a0, 63
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem i32 %x, 64
   ret i32 %1
 }
 
 ; Don't fold if the divisor is one.
-define i32 @dont_fold_urem_one(i32 %x) {
+define i32 @dont_fold_urem_one(i32 %x) nounwind {
 ; CHECK-LABEL: dont_fold_urem_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mv a0, zero
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem i32 %x, 1
   ret i32 %1
 }
 
 ; Don't fold if the divisor is 2^32.
-define i32 @dont_fold_urem_i32_umax(i32 %x) {
+define i32 @dont_fold_urem_i32_umax(i32 %x) nounwind {
 ; CHECK-LABEL: dont_fold_urem_i32_umax:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem i32 %x, 4294967296
   ret i32 %1
 }
 
 ; Don't fold i64 urem
-define i64 @dont_fold_urem_i64(i64 %x) {
+define i64 @dont_fold_urem_i64(i64 %x) nounwind {
 ; RV32I-LABEL: dont_fold_urem_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    addi a2, zero, 98
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __umoddi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_i64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -16
-; RV32IM-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IM-NEXT:    sw ra, 12(sp)
-; RV32IM-NEXT:    .cfi_offset ra, -4
 ; RV32IM-NEXT:    addi a2, zero, 98
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __umoddi3
 ; RV32IM-NEXT:    lw ra, 12(sp)
-; RV32IM-NEXT:    .cfi_restore ra
 ; RV32IM-NEXT:    addi sp, sp, 16
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
-; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    addi a1, zero, 98
 ; RV64I-NEXT:    call __umoddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_i64:
@@ -347,7 +294,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 98
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i64 %x, 98
   ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
@@ -9,11 +9,10 @@
 ; RUN:   | FileCheck -check-prefixes=CHECK,RV64IM %s
 
 
-define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
+define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: fold_urem_vec_1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
@@ -21,13 +20,6 @@
 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    sw s5, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
 ; RV32I-NEXT:    lhu s2, 12(a1)
 ; RV32I-NEXT:    lhu s3, 8(a1)
 ; RV32I-NEXT:    lhu s0, 4(a1)
@@ -59,15 +51,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_vec_1:
@@ -112,13 +96,11 @@
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_vec_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    .cfi_def_cfa_offset 64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)
 ; RV64I-NEXT:    sd s1, 40(sp)
@@ -126,13 +108,6 @@
 ; RV64I-NEXT:    sd s3, 24(sp)
 ; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    sd s5, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
-; RV64I-NEXT:    .cfi_offset s4, -48
-; RV64I-NEXT:    .cfi_offset s5, -56
 ; RV64I-NEXT:    lhu s2, 24(a1)
 ; RV64I-NEXT:    lhu s3, 16(a1)
 ; RV64I-NEXT:    lhu s0, 8(a1)
@@ -164,15 +139,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_vec_1:
@@ -242,17 +209,15 @@
 ; RV64IM-NEXT:    sh a3, 4(a0)
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a1, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
   ret <4 x i16> %1
 }
 
-define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
+define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: fold_urem_vec_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
@@ -260,13 +225,6 @@
 ; RV32I-NEXT:    sw s3, 12(sp)
 ; RV32I-NEXT:    sw s4, 8(sp)
 ; RV32I-NEXT:    sw s5, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
 ; RV32I-NEXT:    lhu s2, 12(a1)
 ; RV32I-NEXT:    lhu s3, 8(a1)
 ; RV32I-NEXT:    lhu s0, 4(a1)
@@ -298,15 +256,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_vec_2:
@@ -350,13 +300,11 @@
 ; RV32IM-NEXT:    sh a2, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh t0, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_vec_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -64
-; RV64I-NEXT:    .cfi_def_cfa_offset 64
 ; RV64I-NEXT:    sd ra, 56(sp)
 ; RV64I-NEXT:    sd s0, 48(sp)
 ; RV64I-NEXT:    sd s1, 40(sp)
@@ -364,13 +312,6 @@
 ; RV64I-NEXT:    sd s3, 24(sp)
 ; RV64I-NEXT:    sd s4, 16(sp)
 ; RV64I-NEXT:    sd s5, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
-; RV64I-NEXT:    .cfi_offset s4, -48
-; RV64I-NEXT:    .cfi_offset s5, -56
 ; RV64I-NEXT:    lhu s2, 24(a1)
 ; RV64I-NEXT:    lhu s3, 16(a1)
 ; RV64I-NEXT:    lhu s0, 8(a1)
@@ -402,15 +343,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_vec_2:
@@ -460,7 +393,6 @@
 ; RV64IM-NEXT:    sh a2, 4(a0)
 ; RV64IM-NEXT:    sh a1, 2(a0)
 ; RV64IM-NEXT:    sh t0, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   ret <4 x i16> %1
@@ -468,11 +400,10 @@
 
 
 ; Don't fold if we can combine urem with udiv.
-define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
+define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: combine_urem_udiv:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    .cfi_def_cfa_offset 48
 ; RV32I-NEXT:    sw ra, 44(sp)
 ; RV32I-NEXT:    sw s0, 40(sp)
 ; RV32I-NEXT:    sw s1, 36(sp)
@@ -484,17 +415,6 @@
 ; RV32I-NEXT:    sw s7, 12(sp)
 ; RV32I-NEXT:    sw s8, 8(sp)
 ; RV32I-NEXT:    sw s9, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
-; RV32I-NEXT:    .cfi_offset s6, -32
-; RV32I-NEXT:    .cfi_offset s7, -36
-; RV32I-NEXT:    .cfi_offset s8, -40
-; RV32I-NEXT:    .cfi_offset s9, -44
 ; RV32I-NEXT:    lhu s2, 0(a1)
 ; RV32I-NEXT:    lhu s3, 4(a1)
 ; RV32I-NEXT:    lhu s4, 8(a1)
@@ -550,19 +470,7 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_urem_udiv:
@@ -610,13 +518,11 @@
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_urem_udiv:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -96
-; RV64I-NEXT:    .cfi_def_cfa_offset 96
 ; RV64I-NEXT:    sd ra, 88(sp)
 ; RV64I-NEXT:    sd s0, 80(sp)
 ; RV64I-NEXT:    sd s1, 72(sp)
@@ -628,17 +534,6 @@
 ; RV64I-NEXT:    sd s7, 24(sp)
 ; RV64I-NEXT:    sd s8, 16(sp)
 ; RV64I-NEXT:    sd s9, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
-; RV64I-NEXT:    .cfi_offset s4, -48
-; RV64I-NEXT:    .cfi_offset s5, -56
-; RV64I-NEXT:    .cfi_offset s6, -64
-; RV64I-NEXT:    .cfi_offset s7, -72
-; RV64I-NEXT:    .cfi_offset s8, -80
-; RV64I-NEXT:    .cfi_offset s9, -88
 ; RV64I-NEXT:    lhu s2, 0(a1)
 ; RV64I-NEXT:    lhu s3, 8(a1)
 ; RV64I-NEXT:    lhu s4, 16(a1)
@@ -694,19 +589,7 @@
 ; RV64I-NEXT:    ld s1, 72(sp)
 ; RV64I-NEXT:    ld s0, 80(sp)
 ; RV64I-NEXT:    ld ra, 88(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
-; RV64I-NEXT:    .cfi_restore s6
-; RV64I-NEXT:    .cfi_restore s7
-; RV64I-NEXT:    .cfi_restore s8
-; RV64I-NEXT:    .cfi_restore s9
 ; RV64I-NEXT:    addi sp, sp, 96
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_urem_udiv:
@@ -760,7 +643,6 @@
 ; RV64IM-NEXT:    sh a1, 4(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a2, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -769,21 +651,15 @@
 }
 
 ; Don't fold for divisors that are a power of two.
-define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
+define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: dont_fold_urem_power_of_two:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
 ; RV32I-NEXT:    sw s2, 16(sp)
 ; RV32I-NEXT:    sw s3, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
 ; RV32I-NEXT:    lhu s2, 8(a1)
 ; RV32I-NEXT:    lhu s3, 4(a1)
 ; RV32I-NEXT:    lhu s1, 0(a1)
@@ -804,13 +680,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_power_of_two:
@@ -836,23 +706,16 @@
 ; RV32IM-NEXT:    sh a3, 2(a0)
 ; RV32IM-NEXT:    sh a1, 0(a0)
 ; RV32IM-NEXT:    sh a2, 6(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_power_of_two:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    lhu s2, 16(a1)
 ; RV64I-NEXT:    lhu s3, 8(a1)
 ; RV64I-NEXT:    lhu s1, 0(a1)
@@ -873,13 +736,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_power_of_two:
@@ -911,28 +768,21 @@
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a2, 0(a0)
 ; RV64IM-NEXT:    sh a1, 6(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is one.
-define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
+define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
 ; RV32I-LABEL: dont_fold_urem_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
-; RV32I-NEXT:    .cfi_def_cfa_offset 32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s0, 24(sp)
 ; RV32I-NEXT:    sw s1, 20(sp)
 ; RV32I-NEXT:    sw s2, 16(sp)
 ; RV32I-NEXT:    sw s3, 12(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
 ; RV32I-NEXT:    lhu s2, 12(a1)
 ; RV32I-NEXT:    lhu s1, 8(a1)
 ; RV32I-NEXT:    lhu a2, 4(a1)
@@ -958,13 +808,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_one:
@@ -999,23 +843,16 @@
 ; RV32IM-NEXT:    sh a3, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a2, 2(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_one:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    lhu s2, 24(a1)
 ; RV64I-NEXT:    lhu s1, 16(a1)
 ; RV64I-NEXT:    lhu a2, 8(a1)
@@ -1041,13 +878,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_one:
@@ -1103,28 +934,25 @@
 ; RV64IM-NEXT:    sh a2, 6(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is 2^16.
-define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
+define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
 ; CHECK-LABEL: dont_fold_urem_i16_smax:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold i64 urem.
-define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
+define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
 ; RV32I-LABEL: dont_fold_urem_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -48
-; RV32I-NEXT:    .cfi_def_cfa_offset 48
 ; RV32I-NEXT:    sw ra, 44(sp)
 ; RV32I-NEXT:    sw s0, 40(sp)
 ; RV32I-NEXT:    sw s1, 36(sp)
@@ -1136,17 +964,6 @@
 ; RV32I-NEXT:    sw s7, 12(sp)
 ; RV32I-NEXT:    sw s8, 8(sp)
 ; RV32I-NEXT:    sw s9, 4(sp)
-; RV32I-NEXT:    .cfi_offset ra, -4
-; RV32I-NEXT:    .cfi_offset s0, -8
-; RV32I-NEXT:    .cfi_offset s1, -12
-; RV32I-NEXT:    .cfi_offset s2, -16
-; RV32I-NEXT:    .cfi_offset s3, -20
-; RV32I-NEXT:    .cfi_offset s4, -24
-; RV32I-NEXT:    .cfi_offset s5, -28
-; RV32I-NEXT:    .cfi_offset s6, -32
-; RV32I-NEXT:    .cfi_offset s7, -36
-; RV32I-NEXT:    .cfi_offset s8, -40
-; RV32I-NEXT:    .cfi_offset s9, -44
 ; RV32I-NEXT:    lw s2, 24(a1)
 ; RV32I-NEXT:    lw s3, 28(a1)
 ; RV32I-NEXT:    lw s4, 16(a1)
@@ -1201,25 +1018,12 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_i64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi sp, sp, -48
-; RV32IM-NEXT:    .cfi_def_cfa_offset 48
 ; RV32IM-NEXT:    sw ra, 44(sp)
 ; RV32IM-NEXT:    sw s0, 40(sp)
 ; RV32IM-NEXT:    sw s1, 36(sp)
@@ -1231,17 +1035,6 @@
 ; RV32IM-NEXT:    sw s7, 12(sp)
 ; RV32IM-NEXT:    sw s8, 8(sp)
 ; RV32IM-NEXT:    sw s9, 4(sp)
-; RV32IM-NEXT:    .cfi_offset ra, -4
-; RV32IM-NEXT:    .cfi_offset s0, -8
-; RV32IM-NEXT:    .cfi_offset s1, -12
-; RV32IM-NEXT:    .cfi_offset s2, -16
-; RV32IM-NEXT:    .cfi_offset s3, -20
-; RV32IM-NEXT:    .cfi_offset s4, -24
-; RV32IM-NEXT:    .cfi_offset s5, -28
-; RV32IM-NEXT:    .cfi_offset s6, -32
-; RV32IM-NEXT:    .cfi_offset s7, -36
-; RV32IM-NEXT:    .cfi_offset s8, -40
-; RV32IM-NEXT:    .cfi_offset s9, -44
 ; RV32IM-NEXT:    lw s2, 24(a1)
 ; RV32IM-NEXT:    lw s3, 28(a1)
 ; RV32IM-NEXT:    lw s4, 16(a1)
@@ -1296,35 +1089,17 @@
 ; RV32IM-NEXT:    lw s1, 36(sp)
 ; RV32IM-NEXT:    lw s0, 40(sp)
 ; RV32IM-NEXT:    lw ra, 44(sp)
-; RV32IM-NEXT:    .cfi_restore ra
-; RV32IM-NEXT:    .cfi_restore s0
-; RV32IM-NEXT:    .cfi_restore s1
-; RV32IM-NEXT:    .cfi_restore s2
-; RV32IM-NEXT:    .cfi_restore s3
-; RV32IM-NEXT:    .cfi_restore s4
-; RV32IM-NEXT:    .cfi_restore s5
-; RV32IM-NEXT:    .cfi_restore s6
-; RV32IM-NEXT:    .cfi_restore s7
-; RV32IM-NEXT:    .cfi_restore s8
-; RV32IM-NEXT:    .cfi_restore s9
 ; RV32IM-NEXT:    addi sp, sp, 48
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
-; RV64I-NEXT:    .cfi_def_cfa_offset 48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s0, 32(sp)
 ; RV64I-NEXT:    sd s1, 24(sp)
 ; RV64I-NEXT:    sd s2, 16(sp)
 ; RV64I-NEXT:    sd s3, 8(sp)
-; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    .cfi_offset s0, -16
-; RV64I-NEXT:    .cfi_offset s1, -24
-; RV64I-NEXT:    .cfi_offset s2, -32
-; RV64I-NEXT:    .cfi_offset s3, -40
 ; RV64I-NEXT:    ld s2, 24(a1)
 ; RV64I-NEXT:    ld s1, 16(a1)
 ; RV64I-NEXT:    ld a2, 8(a1)
@@ -1350,13 +1125,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_i64:
@@ -1412,7 +1181,6 @@
 ; RV64IM-NEXT:    sd a2, 24(a0)
 ; RV64IM-NEXT:    sd a3, 8(a0)
 ; RV64IM-NEXT:    sd a1, 16(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
   ret <4 x i64> %1