Index: llvm/include/llvm/CodeGen/ReachingDefAnalysis.h =================================================================== --- llvm/include/llvm/CodeGen/ReachingDefAnalysis.h +++ llvm/include/llvm/CodeGen/ReachingDefAnalysis.h @@ -93,6 +93,17 @@ /// PhysReg that reaches MI, relative to the begining of MI's basic block. int getReachingDef(MachineInstr *MI, int PhysReg); + /// Provides the instruction of the closest reaching def instruction of + /// PhysReg that reaches MI, relative to the begining of MI's basic block. + MachineInstr *getReachingMIDef(MachineInstr *MI, int PhysReg); + + /// Provides the MI, from the given block, corresponding to the Id or a + /// nullptr if the id does not refer to the block. + MachineInstr *getInstFromId(MachineBasicBlock *MBB, int InstId); + + /// Provides the Id for the given MI. + int getInstId(MachineInstr *MI); + /// Provides the clearance - the number of instructions since the closest /// reaching def instuction of PhysReg that reaches MI. int getClearance(MachineInstr *MI, MCPhysReg PhysReg); Index: llvm/lib/CodeGen/ReachingDefAnalysis.cpp =================================================================== --- llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -135,6 +135,7 @@ if (skipFunction(mf.getFunction())) return false; MF = &mf; + MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness); TRI = MF->getSubtarget().getRegisterInfo(); LiveRegs.clear(); @@ -189,6 +190,33 @@ return LatestDef; } +MachineInstr* ReachingDefAnalysis::getReachingMIDef(MachineInstr *MI, int PhysReg) { + return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)); +} + +MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB, + int InstId) { + unsigned MBBNumber = MBB->getNumber(); + assert(MBBNumber < MBBReachingDefs.size() && + "Unexpected basic block number."); + assert(InstId < static_cast(MBB->size()) && + "Unexpected instruction id."); + + if (InstId < 0) + return nullptr; + + for (auto &MI : *MBB) { + if (InstIds.count(&MI) && InstIds[&MI] == InstId) + return &MI; + } + return nullptr; +} + +int ReachingDefAnalysis::getInstId(MachineInstr *MI) { + assert(InstIds.count(MI) && "Unexpected machine instruction"); + return InstIds[MI]; +} + int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) { assert(InstIds.count(MI) && "Unexpected machine instuction."); return InstIds[MI] - getReachingDef(MI, PhysReg); Index: llvm/lib/Target/ARM/ARMInstrThumb2.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrThumb2.td +++ llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -5232,6 +5232,7 @@ t2PseudoInst<(outs), (ins rGPR:$elts), 4, IIC_Br, [(int_set_loop_iterations rGPR:$elts)]>, Sched<[WriteBr]>; +let Defs = [CPSR] in def t2LoopDec : t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$Rn, imm0_7:$size), 4, IIC_Br, []>, Sched<[WriteBr]>; Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp =================================================================== --- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -25,6 +25,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/ReachingDefAnalysis.h" using namespace llvm; @@ -35,6 +37,7 @@ class ARMLowOverheadLoops : public MachineFunctionPass { MachineFunction *MF = nullptr; + ReachingDefAnalysis *RDA = nullptr; const ARMBaseInstrInfo *TII = nullptr; MachineRegisterInfo *MRI = nullptr; std::unique_ptr BBUtils = nullptr; @@ -47,6 +50,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -54,7 +58,8 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + MachineFunctionProperties::Property::NoVRegs).set( + MachineFunctionProperties::Property::TracksLiveness); } StringRef getPassName() const override { @@ -95,7 +100,7 @@ LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n"); auto &MLI = getAnalysis(); - MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness); + RDA = &getAnalysis(); MRI = &MF->getRegInfo(); TII = static_cast(ST.getInstrInfo()); BBUtils = std::unique_ptr(new ARMBasicBlockUtils(*MF)); @@ -116,97 +121,63 @@ MI.getOpcode() == ARM::t2WhileLoopStart; } -template -static MachineInstr* SearchForDef(MachineInstr *Begin, T End, unsigned Reg) { - for(auto &MI : make_range(T(Begin), End)) { - for (auto &MO : MI.operands()) { - if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) - continue; - return &MI; - } - } - return nullptr; -} - -static MachineInstr* SearchForUse(MachineInstr *Begin, - MachineBasicBlock::iterator End, - unsigned Reg) { - for(auto &MI : make_range(MachineBasicBlock::iterator(Begin), End)) { - for (auto &MO : MI.operands()) { - if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) - continue; - return &MI; - } - } - return nullptr; -} - // Is it safe to define LR with DLS/WLS? // LR can defined if it is the operand to start, because it's the same value, // or if it's going to be equivalent to the operand to Start. MachineInstr *ARMLowOverheadLoops::IsSafeToDefineLR(MachineInstr *Start) { - auto IsMoveLR = [](MachineInstr *MI, unsigned Reg) { + // We can define LR because LR already contains the same value. + if (Start->getOperand(0).getReg() == ARM::LR) + return Start; + + unsigned CountReg = Start->getOperand(0).getReg(); + auto IsMoveLR = [&CountReg](MachineInstr *MI) { return MI->getOpcode() == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::LR && - MI->getOperand(1).getReg() == Reg && + MI->getOperand(1).getReg() == CountReg && MI->getOperand(2).getImm() == ARMCC::AL; }; MachineBasicBlock *MBB = Start->getParent(); - unsigned CountReg = Start->getOperand(0).getReg(); - // Walk forward and backward in the block to find the closest instructions - // that define LR. Then also filter them out if they're not a mov lr. - MachineInstr *PredLRDef = SearchForDef(Start, MBB->rend(), ARM::LR); - if (PredLRDef && !IsMoveLR(PredLRDef, CountReg)) - PredLRDef = nullptr; - - MachineInstr *SuccLRDef = SearchForDef(Start, MBB->end(), ARM::LR); - if (SuccLRDef && !IsMoveLR(SuccLRDef, CountReg)) - SuccLRDef = nullptr; - - // We've either found one, two or none mov lr instructions... Now figure out - // if they are performing the equilvant mov that the Start instruction will. - // Do this by scanning forward and backward to see if there's a def of the - // register holding the count value. If we find a suitable def, return it as - // the insert point. Later, if InsertPt != Start, then we can remove the - // redundant instruction. - if (SuccLRDef) { - MachineBasicBlock::iterator End(SuccLRDef); - if (!SearchForDef(Start, End, CountReg)) { - return SuccLRDef; - } else - SuccLRDef = nullptr; + const int StartId = RDA->getInstId(Start); + + // Is there a (mov lr, Count) before Start? If so, and nothing else writes to + // Count before Start, we can insert at that mov. + if (MachineInstr *LRDef = RDA->getReachingMIDef(Start, ARM::LR)) { + if (IsMoveLR(LRDef)) { + const int CountDefId = RDA->getReachingDef(Start, CountReg); + const int LRDefId = RDA->getReachingDef(Start, ARM::LR); + if (CountDefId < LRDefId || CountDefId > StartId) + return LRDef; + } } - if (PredLRDef) { - MachineBasicBlock::reverse_iterator End(PredLRDef); - if (!SearchForDef(Start, End, CountReg)) { - return PredLRDef; - } else - PredLRDef = nullptr; + // Is there a (mov lr, Count) after Start? If so, and nothing else writes to + // Count after Start, we can insert at that mov. + if (MachineInstr *LRDef = RDA->getReachingMIDef(&MBB->back(), ARM::LR)) { + if (IsMoveLR(LRDef)) { + const int CountDefId = RDA->getReachingDef(LRDef, CountReg); + const int LRDefId = RDA->getReachingDef(Start, ARM::LR); + if (CountDefId > LRDefId || CountDefId < StartId) + return LRDef; + } } - // We can define LR because LR already contains the same value. - if (Start->getOperand(0).getReg() == ARM::LR) - return Start; - // We've found no suitable LR def and Start doesn't use LR directly. Can we - // just define LR anyway? + // just define LR anyway? const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); LivePhysRegs LiveRegs(*TRI); LiveRegs.addLiveOuts(*MBB); - // Not if we've haven't found a suitable mov and LR is live out. - if (LiveRegs.contains(ARM::LR)) - return nullptr; + // Yes, if LR is not live out and nothing uses LR after Start. + for (auto &MI : reverse(*MBB)) { + if (&MI == Start) + return Start; - // If LR is not live out, we can insert the instruction if nothing else - // uses LR after it. - if (!SearchForUse(Start, MBB->end(), ARM::LR)) - return Start; + LiveRegs.stepBackward(MI); + if (LiveRegs.contains(ARM::LR)) + return nullptr; + } - LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find suitable insertion point for" - << " LR\n"); return nullptr; } @@ -378,18 +349,14 @@ } bool ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI, - bool AllowFlags) const { + bool SetFlags) const { LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI); MachineBasicBlock *MBB = MI->getParent(); - // If nothing uses or defines CPSR between LoopDec and LoopEnd, use a t2SUBS. - bool SetFlags = false; - if (AllowFlags) { - if (auto *Def = SearchForDef(MI, MBB->end(), ARM::CPSR)) { - if (!SearchForUse(MI, MBB->end(), ARM::CPSR) && - Def->getOpcode() == ARM::t2LoopEnd) - SetFlags = true; - } + // If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS. + if (SetFlags) { + if (RDA->getInstId(MI) < RDA->getReachingDef(&MBB->back(), ARM::CPSR)) + SetFlags = false; } MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), Index: llvm/test/CodeGen/ARM/O3-pipeline.ll =================================================================== --- llvm/test/CodeGen/ARM/O3-pipeline.ll +++ llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -154,6 +154,7 @@ ; CHECK-NEXT: ARM constant island placement and branch shortening pass ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Machine Natural Loop Construction +; CHECK-NEXT: ReachingDefAnalysis ; CHECK-NEXT: ARM Low Overhead Loops pass ; CHECK-NEXT: Contiguously Lay Out Funclets ; CHECK-NEXT: StackMap Liveness Analysis Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir @@ -104,7 +104,7 @@ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -164,7 +164,7 @@ early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3) $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7) $lr = tMOVr killed $r1, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr $r12 = tMOVr $lr, 14, $noreg tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0) tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir @@ -134,7 +134,7 @@ renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir @@ -104,7 +104,7 @@ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir @@ -134,7 +134,7 @@ renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2B %bb.4, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir @@ -119,7 +119,7 @@ tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 $lr = tMOVr killed $r5, 14, $noreg renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir @@ -103,7 +103,7 @@ liveins: $lr, $r4 renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r4, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr renamable $r4 = tMOVr $lr, 14, $noreg t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir @@ -109,7 +109,7 @@ liveins: $lr $r4 = tMOVr $lr, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr renamable $r0 = t2ADDri renamable $lr, 2, 14, $noreg, $noreg $lr = tMOVr $r4, 14, $noreg t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir @@ -229,7 +229,7 @@ renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 4, 14, $noreg renamable $r8 = nsw t2ADDri killed renamable $r8, 1, 14, $noreg, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr tB %bb.2, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir @@ -135,7 +135,7 @@ renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4) early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr tB %bb.4, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir @@ -130,7 +130,7 @@ dead renamable $r2 = SPACE 4096, undef renamable $r0 renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep) early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir @@ -113,7 +113,7 @@ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -135,7 +135,7 @@ renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir @@ -149,7 +149,7 @@ liveins: $lr, $r0, $r1, $r2, $r12 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 1, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.4, implicit-def dead $cpsr tB %bb.8, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir @@ -111,7 +111,7 @@ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir @@ -111,7 +111,7 @@ renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir @@ -176,7 +176,7 @@ renamable $r12 = nsw t2MUL killed renamable $lr, killed renamable $r12, 14, $noreg early-clobber renamable $r1 = t2STR_PRE killed renamable $r12, renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep3) $lr = tMOVr killed $r0, 14, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr $r0 = tMOVr $lr, 14, $noreg tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7) tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir @@ -119,7 +119,7 @@ renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4) early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7) - renamable $lr = t2LoopDec killed renamable $lr, 1 + renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg