diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -10,10 +10,13 @@ #include "MCTargetDesc/RISCVMCExpr.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "MCTargetDesc/RISCVTargetStreamer.h" +#include "RISCVInstrInfo.h" #include "TargetInfo/RISCVTargetInfo.h" #include "Utils/RISCVBaseInfo.h" #include "Utils/RISCVMatInt.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallBitVector.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringSwitch.h" @@ -128,6 +131,9 @@ // 'add' is an overloaded mnemonic. bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands); + // Check instruction constraints. + bool validateInstruction(MCInst &Inst, OperandVector &Operands); + /// Helper for processing MC instructions that have been successfully matched /// by MatchAndEmitInstruction. Modifications to the emitted instructions, /// like the expansion of pseudo instructions (e.g., "li"), can be performed @@ -150,6 +156,8 @@ OperandMatchResultTy parseCallSymbol(OperandVector &Operands); OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands); OperandMatchResultTy parseJALOffset(OperandVector &Operands); + OperandMatchResultTy parseVTypeI(OperandVector &Operands); + OperandMatchResultTy parseMaskReg(OperandVector &Operands); bool parseOperand(OperandVector &Operands, StringRef Mnemonic); @@ -198,6 +206,8 @@ return false; } + std::unique_ptr defaultMaskRegOp() const; + public: enum RISCVMatchResultTy { Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY, @@ -245,7 +255,8 @@ Token, Register, Immediate, - SystemRegister + SystemRegister, + VType, } Kind; bool IsRV64; @@ -266,12 +277,32 @@ // e.g.: read/write or user/supervisor/machine privileges. }; + enum class VSEW { + SEW_8 = 0, + SEW_16, + SEW_32, + SEW_64, + SEW_128, + SEW_256, + SEW_512, + SEW_1024, + }; + + enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 }; + + struct VTypeOp { + VSEW Sew; + VLMUL Lmul; + unsigned Encoding; + }; + SMLoc StartLoc, EndLoc; union { StringRef Tok; RegOp Reg; ImmOp Imm; struct SysRegOp SysReg; + struct VTypeOp VType; }; RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} @@ -295,14 +326,21 @@ case KindTy::SystemRegister: SysReg = o.SysReg; break; + case KindTy::VType: + VType = o.VType; + break; } } bool isToken() const override { return Kind == KindTy::Token; } bool isReg() const override { return Kind == KindTy::Register; } + bool isV0Reg() const { + return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; + } bool isImm() const override { return Kind == KindTy::Immediate; } bool isMem() const override { return false; } bool isSystemRegister() const { return Kind == KindTy::SystemRegister; } + bool isVType() const { return Kind == KindTy::VType; } bool isGPR() const { return Kind == KindTy::Register && @@ -386,6 +424,8 @@ bool isCSRSystemRegister() const { return isSystemRegister(); } + bool isVTypeI() const { return isVType(); } + /// Return true if the operand is a valid for the fence instruction e.g. /// ('iorw'). bool isFenceArg() const { @@ -493,6 +533,15 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isSImm5() const { + if (!isImm()) + return false; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + bool isSImm6() const { if (!isImm()) return false; @@ -658,6 +707,16 @@ return IsConstantImm && (Imm == 0) && VK == RISCVMCExpr::VK_RISCV_None; } + bool isSImm5Plus1() const { + if (!isImm()) + return false; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isInt<5>(Imm - 1) && + VK == RISCVMCExpr::VK_RISCV_None; + } + /// getStartLoc - Gets location of the first token of this operand SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Gets location of the last token of this operand @@ -685,6 +744,51 @@ return Tok; } + static StringRef getSEWStr(VSEW Sew) { + switch (Sew) { + case VSEW::SEW_8: + return "e8"; + case VSEW::SEW_16: + return "e16"; + case VSEW::SEW_32: + return "e32"; + case VSEW::SEW_64: + return "e64"; + case VSEW::SEW_128: + return "e128"; + case VSEW::SEW_256: + return "e256"; + case VSEW::SEW_512: + return "e512"; + case VSEW::SEW_1024: + return "e1024"; + } + return ""; + } + + static StringRef getLMULStr(VLMUL Lmul) { + switch (Lmul) { + case VLMUL::LMUL_1: + return "m1"; + case VLMUL::LMUL_2: + return "m2"; + case VLMUL::LMUL_4: + return "m4"; + case VLMUL::LMUL_8: + return "m8"; + } + return ""; + } + + StringRef getVType(SmallString<32> &Buf) const { + assert(Kind == KindTy::VType && "Invalid access!"); + Buf.append(getSEWStr(VType.Sew)); + Buf.append(","); + Buf.append(getLMULStr(VType.Lmul)); + + return Buf.str(); + } + void print(raw_ostream &OS) const override { switch (Kind) { case KindTy::Immediate: @@ -700,6 +804,10 @@ case KindTy::SystemRegister: OS << "'; break; + case KindTy::VType: + SmallString<32> VTypeBuf; + OS << "'; + break; } } @@ -744,6 +852,20 @@ return Op; } + static std::unique_ptr createVType(APInt Sew, APInt Lmul, + SMLoc S, bool IsRV64) { + auto Op = std::make_unique(KindTy::VType); + Sew.ashrInPlace(3); + unsigned SewLog2 = Sew.logBase2(); + unsigned LmulLog2 = Lmul.logBase2(); + Op->VType.Sew = static_cast(SewLog2); + Op->VType.Lmul = static_cast(LmulLog2); + Op->VType.Encoding = (SewLog2 << 2) | LmulLog2; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const { assert(Expr && "Expr shouldn't be null!"); int64_t Imm = 0; @@ -767,6 +889,15 @@ addExpr(Inst, getImm()); } + void addSImm5Plus1Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + int64_t Imm = 0; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstant = evaluateConstantImm(getImm(), Imm, VK); + assert(IsConstant && "Expect constant value!"); + Inst.addOperand(MCOperand::createImm(Imm - 1)); + } + void addFenceArgOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // isFenceArg has validated the operand, meaning this cast is safe @@ -791,6 +922,11 @@ Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); } + void addVTypeIOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(VType.Encoding)); + } + // Returns the rounding mode represented by this RISCVOperand. Should only // be called after checking isFRMArg. RISCVFPRndMode::RoundingMode getRoundingMode() const { @@ -868,6 +1004,8 @@ default: break; case Match_Success: + if (validateInstruction(Inst, Operands)) + return true; return processInstruction(Inst, IDLoc, Operands, Out); case Match_MissingFeature: { assert(MissingFeatures.any() && "Unknown missing features!"); @@ -1040,6 +1178,20 @@ SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier"); } + case Match_InvalidVTypeI: { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, + "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]"); + } + case Match_InvalidVMaskRegister: { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be v0.t"); + } + case Match_InvalidSImm5Plus1: { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1, + (1 << 4), + "immediate must be in the range"); + } } llvm_unreachable("Unknown match type detected!"); @@ -1391,6 +1543,74 @@ return parseImmediate(Operands); } +OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) { + SMLoc S = getLoc(); + if (getLexer().getKind() != AsmToken::Identifier) + return MatchOperand_NoMatch; + + // Parse "e8,m1" + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("e")) + return MatchOperand_NoMatch; + APInt Sew(16, Name, 10); + if (Sew != 8 && Sew != 16 && Sew != 32 && Sew != 64 && Sew != 128 && + Sew != 256 && Sew != 512 && Sew != 1024) + return MatchOperand_NoMatch; + getLexer().Lex(); + + if (getLexer().getKind() == AsmToken::EndOfStatement) { + Operands.push_back( + RISCVOperand::createVType(Sew, APInt(16, 1), S, isRV64())); + + return MatchOperand_Success; + } + + if (!getLexer().is(AsmToken::Comma)) + return MatchOperand_NoMatch; + getLexer().Lex(); + + Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("m")) + return MatchOperand_NoMatch; + APInt Lmul(16, Name, 10); + if (Lmul != 1 && Lmul != 2 && Lmul != 4 && Lmul != 8) + return MatchOperand_NoMatch; + getLexer().Lex(); + + if (getLexer().getKind() != AsmToken::EndOfStatement) + return MatchOperand_NoMatch; + + Operands.push_back(RISCVOperand::createVType(Sew, Lmul, S, isRV64())); + + return MatchOperand_Success; +} + +OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) { + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::Identifier: + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_back(".t")) { + Error(getLoc(), "expected '.t' suffix"); + return MatchOperand_ParseFail; + } + Register RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + + if (RegNo == RISCV::NoRegister) + return MatchOperand_NoMatch; + if (RegNo != RISCV::V0) + return MatchOperand_NoMatch; + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64())); + } + + return MatchOperand_Success; +} + OperandMatchResultTy RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { if (getLexer().isNot(AsmToken::LParen)) { @@ -2046,6 +2266,89 @@ return false; } +std::unique_ptr RISCVAsmParser::defaultMaskRegOp() const { + return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(), + llvm::SMLoc(), isRV64()); +} + +bool RISCVAsmParser::validateInstruction(MCInst &Inst, + OperandVector &Operands) { + const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); + unsigned TargetFlags = + (MCID.TSFlags >> RISCV::ConstraintOffset) & RISCV::ConstraintMask; + if (TargetFlags == RISCV::NoConstraint) + return false; + + unsigned DestReg = Inst.getOperand(0).getReg(); + // Operands[1] will be the first operand, DestReg. + SMLoc Loc = Operands[1]->getStartLoc(); + if ((TargetFlags == RISCV::WidenV) || (TargetFlags == RISCV::WidenW) || + (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather) || + (TargetFlags == RISCV::Vcompress)) { + if (TargetFlags != RISCV::WidenW) { + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " the source vector register group."); + if (TargetFlags == RISCV::WidenV) { + // Assume DestReg LMUL is 2 at least for widening/narrowing operations. + if (DestReg + 1 == Src2Reg) + return Error(Loc, + "The destination vector register group cannot overlap" + " the source vector register group."); + } + } + if (Inst.getOperand(2).isReg()) { + unsigned Src1Reg = Inst.getOperand(2).getReg(); + if (DestReg == Src1Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " the source vector register group."); + if (TargetFlags == RISCV::WidenV || TargetFlags == RISCV::WidenW) { + // Assume DestReg LMUL is 2 at least for widening/narrowing operations. + if (DestReg + 1 == Src1Reg) + return Error(Loc, + "The destination vector register group cannot overlap" + " the source vector register group."); + } + } + if (Inst.getNumOperands() == 4) { + unsigned MaskReg = Inst.getOperand(3).getReg(); + + if (DestReg == MaskReg) + return Error(Loc, "The destination vector register group cannot overlap" + " the mask register."); + } + } else if (TargetFlags == RISCV::Narrow) { + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " the source vector register group."); + // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations. + if (DestReg == Src2Reg + 1) + return Error(Loc, "The destination vector register group cannot overlap" + " the source vector register group."); + } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::Iota) { + unsigned Src2Reg = Inst.getOperand(1).getReg(); + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " the source vector register group."); + if (TargetFlags == RISCV::WidenCvt) { + // Assume DestReg LMUL is 2 at least for widening/narrowing operations. + if (DestReg + 1 == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " the source vector register group."); + } + if (Inst.getNumOperands() == 3) { + unsigned MaskReg = Inst.getOperand(2).getReg(); + + if (DestReg == MaskReg) + return Error(Loc, "The destination vector register group cannot overlap" + " the mask register."); + } + } + return false; +} + bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands, MCStreamer &Out) { diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Endian.h" @@ -31,10 +32,12 @@ namespace { class RISCVDisassembler : public MCDisassembler { + std::unique_ptr const MCII; public: - RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) - : MCDisassembler(STI, Ctx) {} + RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, + MCInstrInfo const *MCII) + : MCDisassembler(STI, Ctx), MCII(MCII) {} DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, @@ -45,7 +48,7 @@ static MCDisassembler *createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { - return new RISCVDisassembler(STI, Ctx); + return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo()); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() { @@ -148,6 +151,33 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= 32) + return MCDisassembler::Fail; + + Register Reg = RISCV::V0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, + uint64_t Address, const void *Decoder) { + Register Reg = RISCV::NoRegister; + switch (RegNo) { + default: + return MCDisassembler::Fail; + case 0: + Reg = RISCV::V0; + break; + case 1: + break; + } + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + // Add implied SP operand for instructions *SP compressed instructions. The SP // operand isn't explicitly encoded in the instruction. static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -40,6 +40,12 @@ raw_ostream &O); void printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, + raw_ostream &O); + void printVMaskReg(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); + void printSImm5Plus1(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); // Autogenerated by tblgen. void printInstruction(const MCInst *MI, uint64_t Address, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -150,6 +150,39 @@ return; } +void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + unsigned Sew = (Imm >> 2) & 0x7; + unsigned Lmul = Imm & 0x3; + + Lmul = 0x1 << Lmul; + Sew = 0x1 << (Sew + 3); + O << "e" << Sew << ",m" << Lmul; +} + +void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + + assert(MO.isReg() && "printVMaskReg can only print register operands"); + if (MO.getReg() == RISCV::NoRegister) + return; + O << ", "; + printRegName(O, MO.getReg()); + O << ".t"; +} + +void RISCVInstPrinter::printSImm5Plus1(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + + assert(MO.isImm() && "printSImm5Plus1 can only print constant operands"); + O << MO.getImm() + 1; +} + const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) { return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -80,6 +80,10 @@ unsigned getImmOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + + unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; } // end anonymous namespace @@ -374,4 +378,20 @@ return 0; } +unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + MCOperand MO = MI.getOperand(OpNo); + assert(MO.isReg() && "Expected a register."); + + switch (MO.getReg()) { + default: + llvm_unreachable("Invalid mask register."); + case RISCV::V0: + return 0; + case RISCV::NoRegister: + return 1; + } +} + #include "RISCVGenMCCodeEmitter.inc" diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -147,6 +147,14 @@ AssemblerPredicate<(all_of FeatureRVCHints), "RVC Hint Instructions">; +def FeatureStdExtV + : SubtargetFeature<"experimental-v", "HasStdExtV", "true", + "'V' (Vector Instructions)", + [FeatureStdExtF]>; +def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, + AssemblerPredicate<(all_of FeatureStdExtV), + "'V' (Vector Instructions)">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -49,6 +49,19 @@ def InstFormatCJ : InstFormat<16>; def InstFormatOther : InstFormat<17>; +class RISCVVConstraint val> { + bits<4> Value = val; +} +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; +def WidenCvt : RISCVVConstraint<3>; +def Narrow : RISCVVConstraint<4>; +def Iota : RISCVVConstraint<5>; +def SlideUp : RISCVVConstraint<6>; +def Vrgather : RISCVVConstraint<7>; +def Vcompress : RISCVVConstraint<8>; + // The following opcode names match those given in Table 19.1 in the // RISC-V User-level ISA specification ("RISC-V base opcode map"). class RISCVOpcode val> { @@ -71,6 +84,7 @@ def OPC_NMSUB : RISCVOpcode<0b1001011>; def OPC_NMADD : RISCVOpcode<0b1001111>; def OPC_OP_FP : RISCVOpcode<0b1010011>; +def OPC_OP_V : RISCVOpcode<0b1010111>; def OPC_BRANCH : RISCVOpcode<0b1100011>; def OPC_JALR : RISCVOpcode<0b1100111>; def OPC_JAL : RISCVOpcode<0b1101111>; @@ -99,6 +113,10 @@ let Pattern = pattern; let TSFlags{4-0} = format.Value; + + // Defaults + RISCVVConstraint RVVConstraint = NoConstraint; + let TSFlags{8-5} = RVVConstraint.Value; } // Pseudo instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td @@ -0,0 +1,300 @@ +//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V V extension instruction formats. +// +//===----------------------------------------------------------------------===// + +class RISCVVFormat val> { + bits<3> Value = val; +} +def OPIVV : RISCVVFormat<0b000>; +def OPFVV : RISCVVFormat<0b001>; +def OPMVV : RISCVVFormat<0b010>; +def OPIVI : RISCVVFormat<0b011>; +def OPIVX : RISCVVFormat<0b100>; +def OPFVF : RISCVVFormat<0b101>; +def OPMVX : RISCVVFormat<0b110>; + +class RISCVMOP val> { + bits<3> Value = val; +} +def MOPLDUnitStrideU : RISCVMOP<0b000>; +def MOPLDStridedU : RISCVMOP<0b010>; +def MOPLDIndexedU : RISCVMOP<0b011>; +def MOPLDUnitStrideS : RISCVMOP<0b100>; +def MOPLDStridedS : RISCVMOP<0b110>; +def MOPLDIndexedS : RISCVMOP<0b111>; + +def MOPSTUnitStride : RISCVMOP<0b000>; +def MOPSTStrided : RISCVMOP<0b010>; +def MOPSTIndexedOrder: RISCVMOP<0b011>; +def MOPSTIndexedUnOrd: RISCVMOP<0b111>; + +class RISCVLSUMOP val> { + bits<5> Value = val; +} +def LUMOPUnitStride : RISCVLSUMOP<0b00000>; +def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; +def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>; +def SUMOPUnitStride : RISCVLSUMOP<0b00000>; +def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; + +class RISCVWidth val> { + bits<3> Value = val; +} +def LSWidthVByte : RISCVWidth<0b000>; +def LSWidthVHalf : RISCVWidth<0b101>; +def LSWidthVWord : RISCVWidth<0b110>; +def LSWidthVSEW : RISCVWidth<0b111>; + +class RVInstSetVLi + : RVInst { + bits<5> rs1; + bits<5> rd; + bits<11> vtypei; + + let Inst{31} = 0; + let Inst{30-20} = vtypei; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b111; + let Inst{11-7} = rd; + let Opcode = OPC_OP_V.Value; + + let Defs = [VTYPE, VL]; +} + +class RVInstSetVL + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> rd; + + let Inst{31} = 1; + let Inst{30-25} = 0b000000; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b111; + let Inst{11-7} = rd; + let Opcode = OPC_OP_V.Value; + + let Defs = [VTYPE, VL]; +} + +class RVInstVV funct6, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> vs1; + bits<5> vd; + bit vm; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVX funct6, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstV2 funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst { + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstIVI funct6, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> vs2; + bits<5> imm; + bits<5> vd; + bit vm; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = imm; + let Inst{14-12} = 0b011; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstV funct6, bits<5> vs1, RISCVVFormat opv, dag outs, + dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> vd; + bit vm; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVLU nf, RISCVMOP mop, RISCVLSUMOP lumop, + RISCVWidth width, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = lumop.Value; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vd; + let Opcode = OPC_LOAD_FP.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVLS nf, RISCVMOP mop, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vd; + let Opcode = OPC_LOAD_FP.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVLX nf, RISCVMOP mop, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vd; + let Opcode = OPC_LOAD_FP.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVSU nf, RISCVMOP mop, RISCVLSUMOP sumop, + RISCVWidth width, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> rs1; + bits<5> vs3; + bit vm; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = sumop.Value; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vs3; + let Opcode = OPC_STORE_FP.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVSS nf, RISCVMOP mop, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> vs3; + bit vm; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vs3; + let Opcode = OPC_STORE_FP.Value; + + let Uses = [VTYPE, VL]; +} + +class RVInstVSX nf, RISCVMOP mop, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> rs1; + bits<5> vs3; + bit vm; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vs3; + let Opcode = OPC_STORE_FP.Value; + + let Uses = [VTYPE, VL]; +} diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -133,5 +133,24 @@ protected: const RISCVSubtarget &STI; }; -} + +namespace RISCV { +// Match with the definitions in RISCVInstrFormatsV.td +enum RVVConstraintType { + NoConstraint = 0, + WidenV = 1, + WidenW = 2, + WidenCvt = 3, + Narrow = 4, + Iota = 5, + SlideUp = 6, + Vrgather = 7, + Vcompress = 8, + + ConstraintOffset = 5, + ConstraintMask = 0b1111 +}; +} // end namespace RISCV + +} // end namespace llvm #endif diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1177,3 +1177,4 @@ include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" include "RISCVInstrInfoB.td" +include "RISCVInstrInfoV.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -0,0 +1,873 @@ +//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions from the standard 'V' Vector +/// extension, version 0.8. +/// This version is still experimental as the 'V' extension hasn't been +/// ratified yet. +/// +//===----------------------------------------------------------------------===// + +include "RISCVInstrFormatsV.td" + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +def VTypeIAsmOperand : AsmOperandClass { + let Name = "VTypeI"; + let ParserMethod = "parseVTypeI"; + let DiagnosticType = "InvalidVTypeI"; +} + +def VTypeIOp : Operand { + let ParserMatchClass = VTypeIAsmOperand; + let PrintMethod = "printVTypeI"; + let DecoderMethod = "decodeUImmOperand<11>"; +} + +def VRegAsmOperand : AsmOperandClass { + let Name = "RVVRegOpOperand"; + let RenderMethod = "addRegOperands"; + let PredicateMethod = "isReg"; + let ParserMethod = "parseRegister"; +} + +def VRegOp : RegisterOperand { + let ParserMatchClass = VRegAsmOperand; + let PrintMethod = "printOperand"; +} + +def VMaskAsmOperand : AsmOperandClass { + let Name = "RVVMaskRegOpOperand"; + let RenderMethod = "addRegOperands"; + let PredicateMethod = "isV0Reg"; + let ParserMethod = "parseMaskReg"; + let IsOptional = 1; + let DefaultMethod = "defaultMaskRegOp"; + let DiagnosticType = "InvalidVMaskRegister"; +} + +def VMaskOp : RegisterOperand { + let ParserMatchClass = VMaskAsmOperand; + let PrintMethod = "printVMaskReg"; + let EncoderMethod = "getVMaskReg"; + let DecoderMethod = "decodeVMaskReg"; +} + +def simm5 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<5>; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeSImmOperand<5>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isInt<5>(Imm); + return MCOp.isBareSymbolRef(); + }]; +} + +def SImm5Plus1AsmOperand : AsmOperandClass { + let Name = "SImm5Plus1"; + let RenderMethod = "addSImm5Plus1Operands"; + let DiagnosticType = "InvalidSImm5Plus1"; +} + +def simm5_plus1 : Operand, ImmLeaf(Imm - 1);}]> { + let ParserMatchClass = SImm5Plus1AsmOperand; + let PrintMethod = "printSImm5Plus1"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isInt<5>(Imm - 1); + return MCOp.isBareSymbolRef(); + }]; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { +// load vd, (rs1), vm +class VUnitStrideLoad + : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd), + (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; + +// load vd, (rs1), rs2, vm +class VStridedLoad + : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd), + (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, + "$vd, (${rs1}), $rs2$vm">; + +// load vd, (rs1), vs2, vm +class VIndexedLoad + : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd), + (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr, + "$vd, (${rs1}), $vs2$vm">; + +// vlr.v vd, (rs1) +class VWholeLoad nf, string opcodestr> + : RVInstVLU { + let vm = 1; + let Uses = []; +} +} // hasSideEffects = 0, mayLoad = 1, mayStore = 0 + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { +// store vd, vs3, (rs1), vm +class VUnitStrideStore + : RVInstVSU<0b000, mop, sumop, width, (outs), + (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, + "$vs3, (${rs1})$vm">; + +// store vd, vs3, (rs1), rs2, vm +class VStridedStore + : RVInstVSS<0b000, mop, width, (outs), + (ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm), + opcodestr, "$vs3, (${rs1}), $rs2$vm">; + +// store vd, vs3, (rs1), vs2, vm +class VIndexedStore + : RVInstVSX<0b000, mop, width, (outs), + (ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), + opcodestr, "$vs3, (${rs1}), $vs2$vm">; + +// vsr.v vd, (rs1) +class VWholeStore nf, string opcodestr> + : RVInstVSU { + let vm = 1; + let Uses = []; +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 1 + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// op vd, vs2, vs1, vm +class VALUVV funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs2, vs1, v0 (without mask, use v0 as carry input) +class VALUmVV funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV { + let vm = 0; +} + +// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2) +class VALUrVV funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs1, vs2 +class VALUVVNoVm funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV { + let vm = 1; +} + +// op vd, vs2, rs1, vm +class VALUVX funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2, rs1, v0 (without mask, use v0 as carry input) +class VALUmVX funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX { + let vm = 0; +} + +// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2) +class VALUrVX funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs1, vs2 +class VALUVXNoVm funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX { + let vm = 1; +} + +// op vd, vs2, imm, vm +class VALUVI funct6, string opcodestr, Operand optype = simm5> + : RVInstIVI; + +// op vd, vs2, imm, v0 (without mask, use v0 as carry input) +class VALUmVI funct6, string opcodestr, Operand optype = simm5> + : RVInstIVI { + let vm = 0; +} + +// op vd, vs2, imm, vm +class VALUVINoVm funct6, string opcodestr, Operand optype = simm5> + : RVInstIVI { + let vm = 1; +} + +// op vd, vs2, rs1, vm (Float) +class VALUVF funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2) +class VALUrVF funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2, vm (use vs1 as instruction encoding) +class VALUVs2 funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> + : RVInstV; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +//===----------------------------------------------------------------------===// +// Combination of instruction classes. +// Use these multiclasses to define instructions more easily. +//===----------------------------------------------------------------------===// +multiclass VALU_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + def V : VALUVV; + def X : VALUVX; + def I : VALUVI; +} + +multiclass VALU_IV_V_X funct6, string vw = "v"> { + def V : VALUVV; + def X : VALUVX; +} + +multiclass VALUr_IV_V_X funct6, string vw = "v"> { + def V : VALUrVV; + def X : VALUrVX; +} + +multiclass VALU_IV_X_I funct6, Operand optype = simm5, string vw = "v"> { + def X : VALUVX; + def I : VALUVI; +} + +multiclass VALU_IV_V funct6> { + def _VS : VALUVV; +} + +multiclass VALUr_IV_X funct6, string vw = "v"> { + def X : VALUrVX; +} + +multiclass VALU_MV_V_X funct6, string vw = "v"> { + def V : VALUVV; + def X : VALUVX; +} + +multiclass VALU_MV_V funct6> { + def _VS : VALUVV; +} + +multiclass VALU_MV_Mask funct6, string vm = "v"> { + def M : VALUVVNoVm; +} + +multiclass VALU_MV_X funct6, string vw = "v"> { + def X : VALUVX; +} + +multiclass VALUr_MV_V_X funct6, string vw = "v"> { + def V : VALUrVV; + def X : VALUrVX; +} + +multiclass VALUr_MV_X funct6, string vw = "v"> { + def X : VALUrVX; +} + +multiclass VALU_MV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2; +} + +multiclass VALUm_IV_V_X_I funct6> { + def VM : VALUmVV; + def XM : VALUmVX; + def IM : VALUmVI; +} + +multiclass VALUm_IV_V_X funct6> { + def VM : VALUmVV; + def XM : VALUmVX; +} + +multiclass VALUNoVm_IV_V_X_I funct6, Operand optype = simm5> { + def V : VALUVVNoVm; + def X : VALUVXNoVm; + def I : VALUVINoVm; +} + +multiclass VALUNoVm_IV_V_X funct6> { + def V : VALUVVNoVm; + def X : VALUVXNoVm; +} + +multiclass VALU_FV_V_F funct6, string vw = "v"> { + def V : VALUVV; + def F : VALUVF; +} + +multiclass VALU_FV_F funct6, string vw = "v"> { + def F : VALUVF; +} + +multiclass VALUr_FV_V_F funct6, string vw = "v"> { + def V : VALUrVV; + def F : VALUrVF; +} + +multiclass VALU_FV_V funct6> { + def _VS : VALUVV; +} + +multiclass VALU_FV_VS2 funct6, bits<5> vs1> { + def "" : VALUVs2; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtV] in { +let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { +def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), + "vsetvli", "$rd, $rs1, $vtypei">; + +def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "vsetvl", "$rd, $rs1, $rs2">; +} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 + +// Vector Unit-Stride Instructions +def VLB_V : VUnitStrideLoad; +def VLH_V : VUnitStrideLoad; +def VLW_V : VUnitStrideLoad; + +def VLBU_V : VUnitStrideLoad; +def VLHU_V : VUnitStrideLoad; +def VLWU_V : VUnitStrideLoad; + +def VLE_V : VUnitStrideLoad; + +def VLBFF_V : VUnitStrideLoad; +def VLHFF_V : VUnitStrideLoad; +def VLWFF_V : VUnitStrideLoad; + +def VLBUFF_V : VUnitStrideLoad; +def VLHUFF_V : VUnitStrideLoad; +def VLWUFF_V : VUnitStrideLoad; + +def VLEFF_V : VUnitStrideLoad; + +def VSB_V : VUnitStrideStore; +def VSH_V : VUnitStrideStore; +def VSW_V : VUnitStrideStore; + +def VSE_V : VUnitStrideStore; + +// Vector Strided Instructions +def VLSB_V : VStridedLoad; +def VLSH_V : VStridedLoad; +def VLSW_V : VStridedLoad; + +def VLSBU_V : VStridedLoad; +def VLSHU_V : VStridedLoad; +def VLSWU_V : VStridedLoad; + +def VLSE_V : VStridedLoad; + +def VSSB_V : VStridedStore; +def VSSH_V : VStridedStore; +def VSSW_V : VStridedStore; +def VSSE_V : VStridedStore; + +// Vector Indexed Instructions +def VLXB_V : VIndexedLoad; +def VLXH_V : VIndexedLoad; +def VLXW_V : VIndexedLoad; + +def VLXBU_V : VIndexedLoad; +def VLXHU_V : VIndexedLoad; +def VLXWU_V : VIndexedLoad; + +def VLXE_V : VIndexedLoad; + +def VSXB_V : VIndexedStore; +def VSXH_V : VIndexedStore; +def VSXW_V : VIndexedStore; +def VSXE_V : VIndexedStore; + +def VSUXB_V : VIndexedStore; +def VSUXH_V : VIndexedStore; +def VSUXW_V : VIndexedStore; +def VSUXE_V : VIndexedStore; + +def VL1R_V : VWholeLoad<0, "vl1r.v">; +def VS1R_V : VWholeStore<0, "vs1r.v">; + +// Vector Single-Width Integer Add and Subtract +defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; +defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; +defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; + +// Vector Widening Integer Add/Subtract +// Refer to 11.2 Widening Vector Arithmetic Instructions +// The destination vector register group cannot overlap a source vector +// register group of a different element width (including the mask register +// if masked), otherwise an illegal instruction exception is raised. +let Constraints = "@earlyclobber $vd" in { +let RVVConstraint = WidenV in { +defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>; +defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>; +defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>; +defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>; +} // RVVConstraint = WidenV +// Set earlyclobber for following instructions for second and mask operands. +// This has the downside that the earlyclobber constraint is too coarse and +// will impose unnecessary restrictions by not allowing the destination to +// overlap with the first (wide) operand. +let RVVConstraint = WidenW in { +defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">; +defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">; +defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">; +defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">; +} // RVVConstraint = WidenW +} // Constraints = "@earlyclobber $vd" + +def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm", + (VWADD_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>; +def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm", + (VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>; + +// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions +defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; +defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; +defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; +defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; +defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; +defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; + +// Vector Bitwise Logical Instructions +defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; +defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>; +defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>; + +def : InstAlias<"vnot.v $vd, $vs$vm", + (VXOR_VI VRegOp:$vd, VRegOp:$vs, -1, VMaskOp:$vm)>; + +// Vector Single-Width Bit Shift Instructions +defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>; +defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>; +defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>; + +// Vector Narrowing Integer Right Shift Instructions +// Refer to 11.3. Narrowing Vector Arithmetic Instructions +// The destination vector register group cannot overlap the first source +// vector register group (specified by vs2). The destination vector register +// group cannot overlap the mask register if used, unless LMUL=1. +let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in { +defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">; +defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow + +// Vector Integer Comparison Instructions +defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>; +defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>; +defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>; +defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>; +defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>; +defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>; +defm VMSGTU_V : VALU_IV_X_I<"vmsgtu", 0b011110>; +defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>; + +def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm", + (VMSLTU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; +def : InstAlias<"vmsgt.vv $vd, $va, $vb$vm", + (VMSLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; +def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm", + (VMSLEU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; +def : InstAlias<"vmsge.vv $vd, $va, $vb$vm", + (VMSLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; +def : InstAlias<"vmsltu.vi $vd, $va, $imm$vm", + (VMSLEU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm, + VMaskOp:$vm), 0>; +def : InstAlias<"vmslt.vi $vd, $va, $imm$vm", + (VMSLE_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm, + VMaskOp:$vm), 0>; +def : InstAlias<"vmsgeu.vi $vd, $va, $imm$vm", + (VMSGTU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm, + VMaskOp:$vm), 0>; +def : InstAlias<"vmsge.vi $vd, $va, $imm$vm", + (VMSGT_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm, + VMaskOp:$vm), 0>; + +// Vector Integer Min/Max Instructions +defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>; +defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>; +defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>; +defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>; + +// Vector Single-Width Integer Multiply Instructions +defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>; +defm VMULH_V : VALU_MV_V_X<"vmulh", 0b100111>; +defm VMULHU_V : VALU_MV_V_X<"vmulhu", 0b100100>; +defm VMULHSU_V : VALU_MV_V_X<"vmulhsu", 0b100110>; + +// Vector Integer Divide Instructions +defm VDIVU_V : VALU_MV_V_X<"vdivu", 0b100000>; +defm VDIV_V : VALU_MV_V_X<"vdiv", 0b100001>; +defm VREMU_V : VALU_MV_V_X<"vremu", 0b100010>; +defm VREM_V : VALU_MV_V_X<"vrem", 0b100011>; + +// Vector Widening Integer Multiply Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { +defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011>; +defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000>; +defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV + +// Vector Single-Width Integer Multiply-Add Instructions +defm VMACC_V : VALUr_MV_V_X<"vmacc", 0b101101>; +defm VNMSAC_V : VALUr_MV_V_X<"vnmsac", 0b101111>; +defm VMADD_V : VALUr_MV_V_X<"vmadd", 0b101001>; +defm VNMSUB_V : VALUr_MV_V_X<"vnmsub", 0b101011>; + +// Vector Widening Integer Multiply-Add Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { +defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100>; +defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101>; +defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111>; +defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV + +// Vector Integer Merge Instructions +defm VMERGE_V : VALUm_IV_V_X_I<"vmerge", 0b010111>; + +// Vector Integer Move Instructions +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1 in { +// op vd, vs1 +def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VRegOp:$vd), + (ins VRegOp:$vs1), "vmv.v.v", "$vd, $vs1">; +// op vd, rs1 +def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VRegOp:$vd), + (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">; +// op vd, imm +def VMV_V_I : RVInstIVI<0b010111, (outs VRegOp:$vd), + (ins simm5:$imm), "vmv.v.i", "$vd, $imm">; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +// Vector Fixed-Point Arithmetic Instructions +defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>; +defm VSADD_V : VALU_IV_V_X_I<"vsadd", 0b100001>; +defm VSSUBU_V : VALU_IV_V_X<"vssubu", 0b100010>; +defm VSSUB_V : VALU_IV_V_X<"vssub", 0b100011>; + +// Vector Single-Width Averaging Add and Subtract +defm VAADDU_V : VALU_MV_V_X<"vaaddu", 0b001000>; +defm VAADD_V : VALU_MV_V_X<"vaadd", 0b001001>; +defm VASUBU_V : VALU_MV_V_X<"vasubu", 0b001010>; +defm VASUB_V : VALU_MV_V_X<"vasub", 0b001011>; + +// Vector Single-Width Fractional Multiply with Rounding and Saturation +defm VSMUL_V : VALU_IV_V_X<"vsmul", 0b100111>; + +// Vector Single-Width Scaling Shift Instructions +defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>; +defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>; + +// Vector Narrowing Fixed-Point Clip Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in { +defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; +defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow + +// Vector Single-Width Floating-Point Add/Subtract Instructions +defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; +defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; +defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>; + +// Vector Widening Floating-Point Add/Subtract Instructions +let Constraints = "@earlyclobber $vd" in { +let RVVConstraint = WidenV in { +defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000>; +defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010>; +} // RVVConstraint = WidenV +// Set earlyclobber for following instructions for second and mask operands. +// This has the downside that the earlyclobber constraint is too coarse and +// will impose unnecessary restrictions by not allowing the destination to +// overlap with the first (wide) operand. +let RVVConstraint = WidenW in { +defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, "w">; +defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, "w">; +} // RVVConstraint = WidenW +} // Constraints = "@earlyclobber $vd" + +// Vector Single-Width Floating-Point Multiply/Divide Instructions +defm VFMUL_V : VALU_FV_V_F<"vfmul", 0b100100>; +defm VFDIV_V : VALU_FV_V_F<"vfdiv", 0b100000>; +defm VFRDIV_V : VALU_FV_F<"vfrdiv", 0b100001>; + +// Vector Widening Floating-Point Multiply +let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { +defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV + +// Vector Single-Width Floating-Point Fused Multiply-Add Instructions +defm VFMACC_V : VALUr_FV_V_F<"vfmacc", 0b101100>; +defm VFNMACC_V : VALUr_FV_V_F<"vfnmacc", 0b101101>; +defm VFMSAC_V : VALUr_FV_V_F<"vfmsac", 0b101110>; +defm VFNMSAC_V : VALUr_FV_V_F<"vfnmsac", 0b101111>; +defm VFMADD_V : VALUr_FV_V_F<"vfmadd", 0b101000>; +defm VFNMADD_V : VALUr_FV_V_F<"vfnmadd", 0b101001>; +defm VFMSUB_V : VALUr_FV_V_F<"vfmsub", 0b101010>; +defm VFNMSUB_V : VALUr_FV_V_F<"vfnmsub", 0b101011>; + +// Vector Widening Floating-Point Fused Multiply-Add Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { +defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>; +defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>; +defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>; +defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV + +// Vector Floating-Point Square-Root Instruction +defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>; + +// Vector Floating-Point MIN/MAX Instructions +defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>; +defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>; + +// Vector Floating-Point Sign-Injection Instructions +defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>; +defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>; +defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>; + +// Vector Floating-Point Compare Instructions +defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>; +defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>; +defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>; +defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>; +defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>; +defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>; + +def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm", + (VMFLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; +def : InstAlias<"vmfge.vv $vd, $va, $vb$vm", + (VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; + +// Vector Floating-Point Classify Instruction +defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// Vector Floating-Point Merge Instruction +def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd), + (ins VRegOp:$vs2, FPR32:$rs1, VMV0:$v0), + "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> { + let vm = 0; +} + +// Vector Floating-Point Move Instruction +def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd), + (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> { + let vs2 = 0; + let vm = 1; +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +// Single-Width Floating-Point/Integer Type-Convert Instructions +defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>; +defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>; +defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>; +defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>; + +// Widening Floating-Point/Integer Type-Convert Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in { +defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>; +defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>; +defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>; +defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>; +defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt + +// Narrowing Floating-Point/Integer Type-Convert Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in { +defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>; +defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>; +defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>; +defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>; +defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>; +defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow + +// Vector Single-Width Integer Reduction Instructions +defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>; +defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>; +defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>; +defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>; +defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>; +defm VREDAND : VALU_MV_V<"vredand", 0b000001>; +defm VREDOR : VALU_MV_V<"vredor", 0b000010>; +defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>; + +// Vector Widening Integer Reduction Instructions +let Constraints = "@earlyclobber $vd" in { +// Set earlyclobber for following instructions for second and mask operands. +// This has the downside that the earlyclobber constraint is too coarse and +// will impose unnecessary restrictions by not allowing the destination to +// overlap with the first (wide) operand. +defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>; +defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>; +} // Constraints = "@earlyclobber $vd" + +// Vector Single-Width Floating-Point Reduction Instructions +defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>; +defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>; +defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>; +defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>; + +// Vector Widening Floating-Point Reduction Instructions +let Constraints = "@earlyclobber $vd" in { +// Set earlyclobber for following instructions for second and mask operands. +// This has the downside that the earlyclobber constraint is too coarse and +// will impose unnecessary restrictions by not allowing the destination to +// overlap with the first (wide) operand. +defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>; +defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>; +} // Constraints = "@earlyclobber $vd" + +// Vector Mask-Register Logical Instructions +defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">; +defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">; +defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">; +defm VMXOR_M : VALU_MV_Mask<"vmxor", 0b011011, "m">; +defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">; +defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">; +defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">; +defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">; + +def : InstAlias<"vmcpy.m $vd, $vs", + (VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>; +def : InstAlias<"vmclr.m $vd", + (VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>; +def : InstAlias<"vmset.m $vd", + (VMXNOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>; +def : InstAlias<"vmnot.m $vd, $vs", + (VMNAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// Vector mask population count vpopc +def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd), + (ins VRegOp:$vs2, VMaskOp:$vm), + "vpopc.m", "$vd, $vs2$vm">; + +// vfirst find-first-set mask bit +def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd), + (ins VRegOp:$vs2, VMaskOp:$vm), + "vfirst.m", "$vd, $vs2$vm">; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +// vmsbf.m set-before-first mask bit +defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>; + +// vmsif.m set-including-first mask bit +defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>; + +// vmsof.m set-only-first mask bit +defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>; + +// Vector Iota Instruction +let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { +defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota + +// Vector Element Index Instruction +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VRegOp:$vd), + (ins VMaskOp:$vm), "vid.v", "$vd$vm"> { + let vs2 = 0; +} + +// Integer Scalar Move Instructions +let vm = 1 in { +def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd), + (ins VRegOp:$vs2), "vmv.x.s", "$vd, $vs2">; +def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VRegOp:$vd), + (ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">; + +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 in { +// Floating-Point Scalar Move Instructions +def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd), + (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">; +def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd), + (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">; + +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 + +// Vector Slide Instructions +let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { +defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp +defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; + +let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { +defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp +defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>; + +// Vector Register Gather Instruction +let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { +defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather + +// Vector Compress Instruction +let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { +defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +foreach nf = [1, 2, 4, 8] in { + def VMV#nf#R_V : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd), + (ins VRegOp:$vs2), "vmv" # nf # "r.v", + "$vd, $vs2"> { + let Uses = []; + let vm = 1; + } +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 +} // Predicates = [HasStdExtV] diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -35,6 +35,8 @@ static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive"); static_assert(RISCV::F31_D == RISCV::F0_D + 31, "Register list not consecutive"); +static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive"); +static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive"); RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -33,7 +33,21 @@ let AltNames = subreg.AltNames; } +class RISCVRegWithSubRegs Enc, string n, list subregs, + list alt = []> + : RegisterWithSubRegs { + let HWEncoding{4-0} = Enc; + let AltNames = alt; +} + def ABIRegAltName : RegAltNameIndex; + +def sub_vrm2 : SubRegIndex<64, -1>; +def sub_vrm2_hi : SubRegIndex<64, -1>; +def sub_vrm4 : SubRegIndex<128, -1>; +def sub_vrm4_hi : SubRegIndex<128, -1>; +def sub_vrm8 : SubRegIndex<256, -1>; +def sub_vrm8_hi : SubRegIndex<256, -1>; } // Namespace = "RISCV" // Integer registers @@ -233,3 +247,88 @@ (sequence "F%u_D", 10, 15), (sequence "F%u_D", 8, 9) )>; + +// Vector registers +let RegAltNameIndices = [ABIRegAltName] in { + foreach Index = 0-31 in { + def V#Index : RISCVReg, DwarfRegNum<[!add(Index, 64)]>; + } + + foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, + 24, 26, 28, 30] in { + def V#Index#M2 : RISCVRegWithSubRegs("V"#Index), + !cast("V"#!add(Index, 1))], + ["v"#Index]>, + DwarfRegAlias("V"#Index)> { + let SubRegIndices = [sub_vrm2, sub_vrm2_hi]; + } + } + + foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in { + def V#Index#M4 : RISCVRegWithSubRegs("V"#Index#"M2"), + !cast("V"#!add(Index, 2)#"M2")], + ["v"#Index]>, + DwarfRegAlias("V"#Index)> { + let SubRegIndices = [sub_vrm4, sub_vrm4_hi]; + } + } + + foreach Index = [0, 8, 16, 24] in { + def V#Index#M8 : RISCVRegWithSubRegs("V"#Index#"M4"), + !cast("V"#!add(Index, 4)#"M4")], + ["v"#Index]>, + DwarfRegAlias("V"#Index)> { + let SubRegIndices = [sub_vrm8, sub_vrm8_hi]; + } + } + + def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; + def VL : RISCVReg<0, "vl", ["vl"]>; +} + +class RegisterTypes reg_types> { + list types = reg_types; +} + +// The order of registers represents the preferred allocation sequence, +// meaning caller-save regs are listed before callee-save. +def VR : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64], + 64, (add + (sequence "V%u", 25, 31), + (sequence "V%u", 8, 24), + (sequence "V%u", 0, 7) + )> { + let Size = 64; +} + +def VRM2 : RegisterClass<"RISCV", [nxv16i8, nxv8i16, nxv4i32, nxv2i64], 64, + (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, + V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2)> { + let Size = 128; +} + +def VRM4 : RegisterClass<"RISCV", [nxv32i8, nxv16i16, nxv8i32, nxv4i64], 64, + (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4)> { + let Size = 256; +} + +def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64, + (add V8M8, V16M8, V24M8, V0M8)> { + let Size = 512; +} + +def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>; + +def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add + (sequence "V%u", 25, 31), + (sequence "V%u", 8, 24), + (sequence "V%u", 0, 7))> { + let Size = 64; +} + +def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> { + let Size = 64; +} diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket32.td b/llvm/lib/Target/RISCV/RISCVSchedRocket32.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket32.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket32.td @@ -17,6 +17,7 @@ let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = 1; + let UnsupportedFeatures = [HasStdExtV]; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket64.td b/llvm/lib/Target/RISCV/RISCVSchedRocket64.td --- a/llvm/lib/Target/RISCV/RISCVSchedRocket64.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket64.td @@ -16,6 +16,7 @@ let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. let LoadLatency = 3; let MispredictPenalty = 3; + let UnsupportedFeatures = [HasStdExtV]; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -50,6 +50,7 @@ bool HasStdExtZbs = false; bool HasStdExtZbt = false; bool HasStdExtZbproposedc = false; + bool HasStdExtV = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; @@ -110,6 +111,7 @@ bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; } + bool hasStdExtV() const { return HasStdExtV; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -353,8 +353,19 @@ //===----------------------------------------------- def : SysReg<"dcsr", 0x7B0>; def : SysReg<"dpc", 0x7B1>; + // "dscratch" is an alternative name for "dscratch0" which appeared in earlier // drafts of the RISC-V debug spec let AltName = "dscratch" in def : SysReg<"dscratch0", 0x7B2>; def : SysReg<"dscratch1", 0x7B3>; + +//===----------------------------------------------- +// User Vector CSRs +//===----------------------------------------------- +def : SysReg<"vstart", 0x008>; +def : SysReg<"vxsat", 0x009>; +def : SysReg<"vxrm", 0x00A>; +def : SysReg<"vl", 0xC20>; +def : SysReg<"vtype", 0xC21>; +def : SysReg<"vlenb", 0xC22>; diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -45,7 +45,7 @@ InstFormatCJ = 16, InstFormatOther = 17, - InstFormatMask = 31 + InstFormatMask = 31, }; // RISC-V Specific Machine Operand Flags diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/add.s @@ -0,0 +1,339 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vadd.vv v8, v4, v20, v0.t +# CHECK-INST: vadd.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 00 + +vadd.vv v8, v4, v20 +# CHECK-INST: vadd.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 02 + +vadd.vx v8, v4, a0, v0.t +# CHECK-INST: vadd.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 00 + +vadd.vx v8, v4, a0 +# CHECK-INST: vadd.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 02 + +vadd.vi v8, v4, 15, v0.t +# CHECK-INST: vadd.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 00 + +vadd.vi v8, v4, 15 +# CHECK-INST: vadd.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 02 + +vwaddu.vv v8, v4, v20, v0.t +# CHECK-INST: vwaddu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a c0 + +vwaddu.vv v8, v4, v20 +# CHECK-INST: vwaddu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a c2 + +vwaddu.vx v8, v4, a0, v0.t +# CHECK-INST: vwaddu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 c0 + +vwaddu.vx v8, v4, a0 +# CHECK-INST: vwaddu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 c2 + +vwadd.vv v8, v4, v20, v0.t +# CHECK-INST: vwadd.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xc4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a c4 + +vwadd.vv v8, v4, v20 +# CHECK-INST: vwadd.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xc6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a c6 + +vwadd.vx v8, v4, a0, v0.t +# CHECK-INST: vwadd.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xc4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 c4 + +vwadd.vx v8, v4, a0 +# CHECK-INST: vwadd.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xc6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 c6 + +vwaddu.wv v8, v4, v20, v0.t +# CHECK-INST: vwaddu.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a d0 + +vwaddu.wv v8, v4, v20 +# CHECK-INST: vwaddu.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a d2 + +vwaddu.wx v8, v4, a0, v0.t +# CHECK-INST: vwaddu.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 d0 + +vwaddu.wx v8, v4, a0 +# CHECK-INST: vwaddu.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 d2 + +vwadd.wv v8, v4, v20, v0.t +# CHECK-INST: vwadd.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xd4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a d4 + +vwadd.wv v8, v4, v20 +# CHECK-INST: vwadd.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xd6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a d6 + +vwadd.wx v8, v4, a0, v0.t +# CHECK-INST: vwadd.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xd4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 d4 + +vwadd.wx v8, v4, a0 +# CHECK-INST: vwadd.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xd6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 d6 + +vadc.vvm v8, v4, v20, v0 +# CHECK-INST: vadc.vvm v8, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 40 + +vadc.vxm v8, v4, a0, v0 +# CHECK-INST: vadc.vxm v8, v4, a0, v0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 40 + +vadc.vim v8, v4, 15, v0 +# CHECK-INST: vadc.vim v8, v4, 15, v0 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 40 + +vmadc.vvm v8, v4, v20, v0 +# CHECK-INST: vmadc.vvm v8, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x44] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 44 + +vmadc.vxm v8, v4, a0, v0 +# CHECK-INST: vmadc.vxm v8, v4, a0, v0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x44] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 44 + +vmadc.vim v8, v4, 15, v0 +# CHECK-INST: vmadc.vim v8, v4, 15, v0 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x44] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 44 + +vmadc.vv v8, v4, v20 +# CHECK-INST: vmadc.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x46] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 46 + +vmadc.vx v8, v4, a0 +# CHECK-INST: vmadc.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x46] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 46 + +vmadc.vi v8, v4, 15 +# CHECK-INST: vmadc.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x46] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 46 + +vsaddu.vv v8, v4, v20, v0.t +# CHECK-INST: vsaddu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 80 + +vsaddu.vv v8, v4, v20 +# CHECK-INST: vsaddu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 82 + +vsaddu.vx v8, v4, a0, v0.t +# CHECK-INST: vsaddu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 80 + +vsaddu.vx v8, v4, a0 +# CHECK-INST: vsaddu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 82 + +vsaddu.vi v8, v4, 15, v0.t +# CHECK-INST: vsaddu.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 80 + +vsaddu.vi v8, v4, 15 +# CHECK-INST: vsaddu.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 82 + +vsadd.vv v8, v4, v20, v0.t +# CHECK-INST: vsadd.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x84] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 84 + +vsadd.vv v8, v4, v20 +# CHECK-INST: vsadd.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x86] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 86 + +vsadd.vx v8, v4, a0, v0.t +# CHECK-INST: vsadd.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x84] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 84 + +vsadd.vx v8, v4, a0 +# CHECK-INST: vsadd.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x86] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 86 + +vsadd.vi v8, v4, 15, v0.t +# CHECK-INST: vsadd.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x84] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 84 + +vsadd.vi v8, v4, 15 +# CHECK-INST: vsadd.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x86] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 86 + +vaadd.vv v8, v4, v20, v0.t +# CHECK-INST: vaadd.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 24 + +vaadd.vv v8, v4, v20 +# CHECK-INST: vaadd.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 26 + +vaadd.vx v8, v4, a0, v0.t +# CHECK-INST: vaadd.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 24 + +vaadd.vx v8, v4, a0 +# CHECK-INST: vaadd.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 26 + +vaaddu.vv v8, v4, v20, v0.t +# CHECK-INST: vaaddu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 20 + +vaaddu.vv v8, v4, v20 +# CHECK-INST: vaaddu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 22 + +vaaddu.vx v8, v4, a0, v0.t +# CHECK-INST: vaaddu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 20 + +vaaddu.vx v8, v4, a0 +# CHECK-INST: vaaddu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 22 + +vwcvt.x.x.v v8, v4, v0.t +# CHECK-INST: vwcvt.x.x.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x40,0xc4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 40 c4 + +vwcvt.x.x.v v8, v4 +# CHECK-INST: vwadd.vx v8, v4, zero +# CHECK-ENCODING: [0x57,0x64,0x40,0xc6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 40 c6 + +vwcvtu.x.x.v v8, v4, v0.t +# CHECK-INST: vwcvtu.x.x.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x40,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 40 c0 + +vwcvtu.x.x.v v8, v4 +# CHECK-INST: vwaddu.vx v8, v4, zero +# CHECK-ENCODING: [0x57,0x64,0x40,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 40 c2 diff --git a/llvm/test/MC/RISCV/rvv/and.s b/llvm/test/MC/RISCV/rvv/and.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/and.s @@ -0,0 +1,45 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vand.vv v8, v4, v20, v0.t +# CHECK-INST: vand.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 24 + +vand.vv v8, v4, v20 +# CHECK-INST: vand.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 26 + +vand.vx v8, v4, a0, v0.t +# CHECK-INST: vand.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 24 + +vand.vx v8, v4, a0 +# CHECK-INST: vand.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 26 + +vand.vi v8, v4, 15, v0.t +# CHECK-INST: vand.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 24 + +vand.vi v8, v4, 15 +# CHECK-INST: vand.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 26 diff --git a/llvm/test/MC/RISCV/rvv/clip.s b/llvm/test/MC/RISCV/rvv/clip.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/clip.s @@ -0,0 +1,81 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vnclipu.wv v8, v4, v20, v0.t +# CHECK-INST: vnclipu.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a b8 + +vnclipu.wv v8, v4, v20 +# CHECK-INST: vnclipu.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a ba + +vnclipu.wx v8, v4, a0, v0.t +# CHECK-INST: vnclipu.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 b8 + +vnclipu.wx v8, v4, a0 +# CHECK-INST: vnclipu.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 ba + +vnclipu.wi v8, v4, 31, v0.t +# CHECK-INST: vnclipu.wi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f b8 + +vnclipu.wi v8, v4, 31 +# CHECK-INST: vnclipu.wi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f ba + +vnclip.wv v8, v4, v20, v0.t +# CHECK-INST: vnclip.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a bc + +vnclip.wv v8, v4, v20 +# CHECK-INST: vnclip.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a be + +vnclip.wx v8, v4, a0, v0.t +# CHECK-INST: vnclip.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 bc + +vnclip.wx v8, v4, a0 +# CHECK-INST: vnclip.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 be + +vnclip.wi v8, v4, 31, v0.t +# CHECK-INST: vnclip.wi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f bc + +vnclip.wi v8, v4, 31 +# CHECK-INST: vnclip.wi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f be diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/compare.s @@ -0,0 +1,345 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmseq.vv v8, v4, v20, v0.t +# CHECK-INST: vmseq.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 60 + +vmseq.vv v8, v4, v20 +# CHECK-INST: vmseq.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 62 + +vmseq.vx v8, v4, a0, v0.t +# CHECK-INST: vmseq.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 60 + +vmseq.vx v8, v4, a0 +# CHECK-INST: vmseq.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 62 + +vmseq.vi v8, v4, 15, v0.t +# CHECK-INST: vmseq.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 60 + +vmseq.vi v8, v4, 15 +# CHECK-INST: vmseq.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 62 + +vmsne.vv v8, v4, v20, v0.t +# CHECK-INST: vmsne.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x64] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 64 + +vmsne.vv v8, v4, v20 +# CHECK-INST: vmsne.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 66 + +vmsne.vx v8, v4, a0, v0.t +# CHECK-INST: vmsne.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x64] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 64 + +vmsne.vx v8, v4, a0 +# CHECK-INST: vmsne.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 66 + +vmsne.vi v8, v4, 15, v0.t +# CHECK-INST: vmsne.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x64] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 64 + +vmsne.vi v8, v4, 15 +# CHECK-INST: vmsne.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 66 + +vmsltu.vv v8, v4, v20, v0.t +# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 68 + +vmsltu.vv v8, v4, v20 +# CHECK-INST: vmsltu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 6a + +vmsltu.vx v8, v4, a0, v0.t +# CHECK-INST: vmsltu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 68 + +vmsltu.vx v8, v4, a0 +# CHECK-INST: vmsltu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 6a + +vmslt.vv v8, v4, v20, v0.t +# CHECK-INST: vmslt.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 6c + +vmslt.vv v8, v4, v20 +# CHECK-INST: vmslt.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 6e + +vmslt.vx v8, v4, a0, v0.t +# CHECK-INST: vmslt.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 6c + +vmslt.vx v8, v4, a0 +# CHECK-INST: vmslt.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 6e + +vmsleu.vv v8, v4, v20, v0.t +# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 70 + +vmsleu.vv v8, v4, v20 +# CHECK-INST: vmsleu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 72 + +vmsleu.vx v8, v4, a0, v0.t +# CHECK-INST: vmsleu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 70 + +vmsleu.vx v8, v4, a0 +# CHECK-INST: vmsleu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 72 + +vmsleu.vi v8, v4, 15, v0.t +# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 70 + +vmsleu.vi v8, v4, 15 +# CHECK-INST: vmsleu.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 72 + +vmsle.vv v8, v4, v20, v0.t +# CHECK-INST: vmsle.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x74] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 74 + +vmsle.vv v8, v4, v20 +# CHECK-INST: vmsle.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 76 + +vmsle.vx v8, v4, a0, v0.t +# CHECK-INST: vmsle.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x74] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 74 + +vmsle.vx v8, v4, a0 +# CHECK-INST: vmsle.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 76 + +vmsle.vi v8, v4, 15, v0.t +# CHECK-INST: vmsle.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x74] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 74 + +vmsle.vi v8, v4, 15 +# CHECK-INST: vmsle.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 76 + +vmsgtu.vx v8, v4, a0, v0.t +# CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 78 + +vmsgtu.vx v8, v4, a0 +# CHECK-INST: vmsgtu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 7a + +vmsgtu.vi v8, v4, 15, v0.t +# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 78 + +vmsgtu.vi v8, v4, 15 +# CHECK-INST: vmsgtu.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 7a + +vmsgt.vx v8, v4, a0, v0.t +# CHECK-INST: vmsgt.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 7c + +vmsgt.vx v8, v4, a0 +# CHECK-INST: vmsgt.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 7e + +vmsgt.vi v8, v4, 15, v0.t +# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 7c + +vmsgt.vi v8, v4, 15 +# CHECK-INST: vmsgt.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 7e + +vmsgtu.vv v8, v20, v4, v0.t +# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 68 + +vmsgtu.vv v8, v20, v4 +# CHECK-INST: vmsltu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 6a + +vmsgt.vv v8, v20, v4, v0.t +# CHECK-INST: vmslt.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 6c + +vmsgt.vv v8, v20, v4 +# CHECK-INST: vmslt.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 6e + +vmsgeu.vv v8, v20, v4, v0.t +# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 70 + +vmsgeu.vv v8, v20, v4 +# CHECK-INST: vmsleu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 72 + +vmsge.vv v8, v20, v4, v0.t +# CHECK-INST: vmsle.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x74] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 74 + +vmsge.vv v8, v20, v4 +# CHECK-INST: vmsle.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 76 + +vmsltu.vi v8, v4, 16, v0.t +# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 70 + +vmsltu.vi v8, v4, 16 +# CHECK-INST: vmsleu.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 72 + +vmslt.vi v8, v4, 16, v0.t +# CHECK-INST: vmsle.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x74] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 74 + +vmslt.vi v8, v4, 16 +# CHECK-INST: vmsle.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 76 + +vmsgeu.vi v8, v4, 16, v0.t +# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 78 + +vmsgeu.vi v8, v4, 16 +# CHECK-INST: vmsgtu.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 7a + +vmsge.vi v8, v4, 16, v0.t +# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 7c + +vmsge.vi v8, v4, 16 +# CHECK-INST: vmsgt.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 7e diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/convert.s @@ -0,0 +1,189 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfcvt.xu.f.v v8, v4, v0.t +# CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x40,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 40 88 + +vfcvt.xu.f.v v8, v4 +# CHECK-INST: vfcvt.xu.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x40,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 40 8a + +vfcvt.x.f.v v8, v4, v0.t +# CHECK-INST: vfcvt.x.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x40,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 40 88 + +vfcvt.x.f.v v8, v4 +# CHECK-INST: vfcvt.x.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x40,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 40 8a + +vfcvt.f.xu.v v8, v4, v0.t +# CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x41,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 41 88 + +vfcvt.f.xu.v v8, v4 +# CHECK-INST: vfcvt.f.xu.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x41,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 41 8a + +vfcvt.f.x.v v8, v4, v0.t +# CHECK-INST: vfcvt.f.x.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x41,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 41 88 + +vfcvt.f.x.v v8, v4 +# CHECK-INST: vfcvt.f.x.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x41,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 41 8a + +vfwcvt.xu.f.v v8, v4, v0.t +# CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x44,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 44 88 + +vfwcvt.xu.f.v v8, v4 +# CHECK-INST: vfwcvt.xu.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x44,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 44 8a + +vfwcvt.x.f.v v8, v4, v0.t +# CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x44,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 44 88 + +vfwcvt.x.f.v v8, v4 +# CHECK-INST: vfwcvt.x.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x44,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 44 8a + +vfwcvt.f.xu.v v8, v4, v0.t +# CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x45,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 45 88 + +vfwcvt.f.xu.v v8, v4 +# CHECK-INST: vfwcvt.f.xu.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x45,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 45 8a + +vfwcvt.f.x.v v8, v4, v0.t +# CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x45,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 45 88 + +vfwcvt.f.x.v v8, v4 +# CHECK-INST: vfwcvt.f.x.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x45,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 45 8a + +vfwcvt.f.f.v v8, v4, v0.t +# CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x46,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 46 88 + +vfwcvt.f.f.v v8, v4 +# CHECK-INST: vfwcvt.f.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x46,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 46 8a + +vfncvt.xu.f.w v8, v4, v0.t +# CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x48,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 48 88 + +vfncvt.xu.f.w v8, v4 +# CHECK-INST: vfncvt.xu.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x48,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 48 8a + +vfncvt.x.f.w v8, v4, v0.t +# CHECK-INST: vfncvt.x.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x48,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 48 88 + +vfncvt.x.f.w v8, v4 +# CHECK-INST: vfncvt.x.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x48,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 48 8a + +vfncvt.f.xu.w v8, v4, v0.t +# CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x49,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 49 88 + +vfncvt.f.xu.w v8, v4 +# CHECK-INST: vfncvt.f.xu.w v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x49,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 49 8a + +vfncvt.f.x.w v8, v4, v0.t +# CHECK-INST: vfncvt.f.x.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x49,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 49 88 + +vfncvt.f.x.w v8, v4 +# CHECK-INST: vfncvt.f.x.w v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x49,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 49 8a + +vfncvt.f.f.w v8, v4, v0.t +# CHECK-INST: vfncvt.f.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 88 + +vfncvt.f.f.w v8, v4 +# CHECK-INST: vfncvt.f.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 8a + +vfncvt.rod.f.f.w v8, v4, v0.t +# CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4a,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 4a 88 + +vfncvt.rod.f.f.w v8, v4 +# CHECK-INST: vfncvt.rod.f.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 4a 8a diff --git a/llvm/test/MC/RISCV/rvv/div.s b/llvm/test/MC/RISCV/rvv/div.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/div.s @@ -0,0 +1,105 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vdivu.vv v8, v4, v20, v0.t +# CHECK-INST: vdivu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 80 + +vdivu.vv v8, v4, v20 +# CHECK-INST: vdivu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 82 + +vdivu.vx v8, v4, a0, v0.t +# CHECK-INST: vdivu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 80 + +vdivu.vx v8, v4, a0 +# CHECK-INST: vdivu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 82 + +vdiv.vv v8, v4, v20, v0.t +# CHECK-INST: vdiv.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x84] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 84 + +vdiv.vv v8, v4, v20 +# CHECK-INST: vdiv.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x86] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 86 + +vdiv.vx v8, v4, a0, v0.t +# CHECK-INST: vdiv.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x84] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 84 + +vdiv.vx v8, v4, a0 +# CHECK-INST: vdiv.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x86] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 86 + +vremu.vv v8, v4, v20, v0.t +# CHECK-INST: vremu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 88 + +vremu.vv v8, v4, v20 +# CHECK-INST: vremu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 8a + +vremu.vx v8, v4, a0, v0.t +# CHECK-INST: vremu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 88 + +vremu.vx v8, v4, a0 +# CHECK-INST: vremu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 8a + +vrem.vv v8, v4, v20, v0.t +# CHECK-INST: vrem.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 8c + +vrem.vv v8, v4, v20 +# CHECK-INST: vrem.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 8e + +vrem.vx v8, v4, a0, v0.t +# CHECK-INST: vrem.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 8c + +vrem.vx v8, v4, a0 +# CHECK-INST: vrem.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 8e diff --git a/llvm/test/MC/RISCV/rvv/fadd.s b/llvm/test/MC/RISCV/rvv/fadd.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fadd.s @@ -0,0 +1,81 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfadd.vv v8, v4, v20, v0.t +# CHECK-INST: vfadd.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 00 + +vfadd.vv v8, v4, v20 +# CHECK-INST: vfadd.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 02 + +vfadd.vf v8, v4, fa0, v0.t +# CHECK-INST: vfadd.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 00 + +vfadd.vf v8, v4, fa0 +# CHECK-INST: vfadd.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 02 + +vfwadd.vv v8, v4, v20, v0.t +# CHECK-INST: vfwadd.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a c0 + +vfwadd.vv v8, v4, v20 +# CHECK-INST: vfwadd.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a c2 + +vfwadd.vf v8, v4, fa0, v0.t +# CHECK-INST: vfwadd.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 c0 + +vfwadd.vf v8, v4, fa0 +# CHECK-INST: vfwadd.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 c2 + +vfwadd.wv v8, v4, v20, v0.t +# CHECK-INST: vfwadd.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a d0 + +vfwadd.wv v8, v4, v20 +# CHECK-INST: vfwadd.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a d2 + +vfwadd.wf v8, v4, fa0, v0.t +# CHECK-INST: vfwadd.wf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 d0 + +vfwadd.wf v8, v4, fa0 +# CHECK-INST: vfwadd.wf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 d2 diff --git a/llvm/test/MC/RISCV/rvv/fcompare.s b/llvm/test/MC/RISCV/rvv/fcompare.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fcompare.s @@ -0,0 +1,153 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmfeq.vv v8, v4, v20, v0.t +# CHECK-INST: vmfeq.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 60 + +vmfeq.vv v8, v4, v20 +# CHECK-INST: vmfeq.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 62 + +vmfeq.vf v8, v4, fa0, v0.t +# CHECK-INST: vmfeq.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 60 + +vmfeq.vf v8, v4, fa0 +# CHECK-INST: vmfeq.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 62 + +vmfne.vv v8, v4, v20, v0.t +# CHECK-INST: vmfne.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 70 + +vmfne.vv v8, v4, v20 +# CHECK-INST: vmfne.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 72 + +vmfne.vf v8, v4, fa0, v0.t +# CHECK-INST: vmfne.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 70 + +vmfne.vf v8, v4, fa0 +# CHECK-INST: vmfne.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 72 + +vmflt.vv v8, v4, v20, v0.t +# CHECK-INST: vmflt.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 6c + +vmflt.vv v8, v4, v20 +# CHECK-INST: vmflt.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 6e + +vmflt.vf v8, v4, fa0, v0.t +# CHECK-INST: vmflt.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 6c + +vmflt.vf v8, v4, fa0 +# CHECK-INST: vmflt.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 6e + +vmfle.vv v8, v4, v20, v0.t +# CHECK-INST: vmfle.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x64] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 64 + +vmfle.vv v8, v4, v20 +# CHECK-INST: vmfle.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 66 + +vmfle.vf v8, v4, fa0, v0.t +# CHECK-INST: vmfle.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x64] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 64 + +vmfle.vf v8, v4, fa0 +# CHECK-INST: vmfle.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 66 + +vmfgt.vf v8, v4, fa0, v0.t +# CHECK-INST: vmfgt.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x74] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 74 + +vmfgt.vf v8, v4, fa0 +# CHECK-INST: vmfgt.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 76 + +vmfge.vf v8, v4, fa0, v0.t +# CHECK-INST: vmfge.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 7c + +vmfge.vf v8, v4, fa0 +# CHECK-INST: vmfge.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 7e + +vmfgt.vv v8, v20, v4, v0.t +# CHECK-INST: vmflt.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 6c + +vmfgt.vv v8, v20, v4 +# CHECK-INST: vmflt.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 6e + +vmfge.vv v8, v20, v4, v0.t +# CHECK-INST: vmfle.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x64] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 64 + +vmfge.vv v8, v20, v4 +# CHECK-INST: vmfle.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 66 diff --git a/llvm/test/MC/RISCV/rvv/fdiv.s b/llvm/test/MC/RISCV/rvv/fdiv.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fdiv.s @@ -0,0 +1,45 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfdiv.vv v8, v4, v20, v0.t +# CHECK-INST: vfdiv.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 80 + +vfdiv.vv v8, v4, v20 +# CHECK-INST: vfdiv.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 82 + +vfdiv.vf v8, v4, fa0, v0.t +# CHECK-INST: vfdiv.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 80 + +vfdiv.vf v8, v4, fa0 +# CHECK-INST: vfdiv.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 82 + +vfrdiv.vf v8, v4, fa0, v0.t +# CHECK-INST: vfrdiv.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x84] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 84 + +vfrdiv.vf v8, v4, fa0 +# CHECK-INST: vfrdiv.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x86] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 86 diff --git a/llvm/test/MC/RISCV/rvv/fmacc.s b/llvm/test/MC/RISCV/rvv/fmacc.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fmacc.s @@ -0,0 +1,297 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfmacc.vv v8, v20, v4, v0.t +# CHECK-INST: vfmacc.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a b0 + +vfmacc.vv v8, v20, v4 +# CHECK-INST: vfmacc.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a b2 + +vfmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 b0 + +vfmacc.vf v8, fa0, v4 +# CHECK-INST: vfmacc.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 b2 + +vfnmacc.vv v8, v20, v4, v0.t +# CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a b4 + +vfnmacc.vv v8, v20, v4 +# CHECK-INST: vfnmacc.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a b6 + +vfnmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 b4 + +vfnmacc.vf v8, fa0, v4 +# CHECK-INST: vfnmacc.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 b6 + +vfmsac.vv v8, v20, v4, v0.t +# CHECK-INST: vfmsac.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a b8 + +vfmsac.vv v8, v20, v4 +# CHECK-INST: vfmsac.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a ba + +vfmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 b8 + +vfmsac.vf v8, fa0, v4 +# CHECK-INST: vfmsac.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 ba + +vfnmsac.vv v8, v20, v4, v0.t +# CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a bc + +vfnmsac.vv v8, v20, v4 +# CHECK-INST: vfnmsac.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a be + +vfnmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 bc + +vfnmsac.vf v8, fa0, v4 +# CHECK-INST: vfnmsac.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 be + +vfmadd.vv v8, v20, v4, v0.t +# CHECK-INST: vfmadd.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a a0 + +vfmadd.vv v8, v20, v4 +# CHECK-INST: vfmadd.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a a2 + +vfmadd.vf v8, fa0, v4, v0.t +# CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 a0 + +vfmadd.vf v8, fa0, v4 +# CHECK-INST: vfmadd.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 a2 + +vfnmadd.vv v8, v20, v4, v0.t +# CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a a4 + +vfnmadd.vv v8, v20, v4 +# CHECK-INST: vfnmadd.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a a6 + +vfnmadd.vf v8, fa0, v4, v0.t +# CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 a4 + +vfnmadd.vf v8, fa0, v4 +# CHECK-INST: vfnmadd.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 a6 + +vfmsub.vv v8, v20, v4, v0.t +# CHECK-INST: vfmsub.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a a8 + +vfmsub.vv v8, v20, v4 +# CHECK-INST: vfmsub.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a aa + +vfmsub.vf v8, fa0, v4, v0.t +# CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 a8 + +vfmsub.vf v8, fa0, v4 +# CHECK-INST: vfmsub.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 aa + +vfnmsub.vv v8, v20, v4, v0.t +# CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a ac + +vfnmsub.vv v8, v20, v4 +# CHECK-INST: vfnmsub.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a ae + +vfnmsub.vf v8, fa0, v4, v0.t +# CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 ac + +vfnmsub.vf v8, fa0, v4 +# CHECK-INST: vfnmsub.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 ae + +vfwmacc.vv v8, v20, v4, v0.t +# CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a f0 + +vfwmacc.vv v8, v20, v4 +# CHECK-INST: vfwmacc.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a f2 + +vfwmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 f0 + +vfwmacc.vf v8, fa0, v4 +# CHECK-INST: vfwmacc.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 f2 + +vfwnmacc.vv v8, v20, v4, v0.t +# CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xf4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a f4 + +vfwnmacc.vv v8, v20, v4 +# CHECK-INST: vfwnmacc.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xf6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a f6 + +vfwnmacc.vf v8, fa0, v4, v0.t +# CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xf4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 f4 + +vfwnmacc.vf v8, fa0, v4 +# CHECK-INST: vfwnmacc.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xf6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 f6 + +vfwmsac.vv v8, v20, v4, v0.t +# CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a f8 + +vfwmsac.vv v8, v20, v4 +# CHECK-INST: vfwmsac.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a fa + +vfwmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 f8 + +vfwmsac.vf v8, fa0, v4 +# CHECK-INST: vfwmsac.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 fa + +vfwnmsac.vv v8, v20, v4, v0.t +# CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a fc + +vfwnmsac.vv v8, v20, v4 +# CHECK-INST: vfwnmsac.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a fe + +vfwnmsac.vf v8, fa0, v4, v0.t +# CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 fc + +vfwnmsac.vf v8, fa0, v4 +# CHECK-INST: vfwnmsac.vf v8, fa0, v4 +# CHECK-ENCODING: [0x57,0x54,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 fe diff --git a/llvm/test/MC/RISCV/rvv/fminmax.s b/llvm/test/MC/RISCV/rvv/fminmax.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fminmax.s @@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfmin.vv v8, v4, v20, v0.t +# CHECK-INST: vfmin.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 10 + +vfmin.vv v8, v4, v20 +# CHECK-INST: vfmin.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 12 + +vfmin.vf v8, v4, fa0, v0.t +# CHECK-INST: vfmin.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 10 + +vfmin.vf v8, v4, fa0 +# CHECK-INST: vfmin.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 12 + +vfmax.vv v8, v4, v20, v0.t +# CHECK-INST: vfmax.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 18 + +vfmax.vv v8, v4, v20 +# CHECK-INST: vfmax.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 1a + +vfmax.vf v8, v4, fa0, v0.t +# CHECK-INST: vfmax.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 18 + +vfmax.vf v8, v4, fa0 +# CHECK-INST: vfmax.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 1a diff --git a/llvm/test/MC/RISCV/rvv/fmul.s b/llvm/test/MC/RISCV/rvv/fmul.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fmul.s @@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfmul.vv v8, v4, v20, v0.t +# CHECK-INST: vfmul.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 90 + +vfmul.vv v8, v4, v20 +# CHECK-INST: vfmul.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 92 + +vfmul.vf v8, v4, fa0, v0.t +# CHECK-INST: vfmul.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 90 + +vfmul.vf v8, v4, fa0 +# CHECK-INST: vfmul.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 92 + +vfwmul.vv v8, v4, v20, v0.t +# CHECK-INST: vfwmul.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a e0 + +vfwmul.vv v8, v4, v20 +# CHECK-INST: vfwmul.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a e2 + +vfwmul.vf v8, v4, fa0, v0.t +# CHECK-INST: vfwmul.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 e0 + +vfwmul.vf v8, v4, fa0 +# CHECK-INST: vfwmul.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 e2 diff --git a/llvm/test/MC/RISCV/rvv/fmv.s b/llvm/test/MC/RISCV/rvv/fmv.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fmv.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfmv.v.f v8, fa0 +# CHECK-INST: vfmv.v.f v8, fa0 +# CHECK-ENCODING: [0x57,0x54,0x05,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 05 5e + +vfmv.f.s fa0, v4 +# CHECK-INST: vfmv.f.s fa0, v4 +# CHECK-ENCODING: [0x57,0x15,0x40,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 15 40 42 + +vfmv.s.f v8, fa0 +# CHECK-INST: vfmv.s.f v8, fa0 +# CHECK-ENCODING: [0x57,0x54,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 05 42 diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fothers.s @@ -0,0 +1,39 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfsqrt.v v8, v4, v0.t +# CHECK-INST: vfsqrt.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x40,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 40 8c + +vfsqrt.v v8, v4 +# CHECK-INST: vfsqrt.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x40,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 40 8e + +vfclass.v v8, v4, v0.t +# CHECK-INST: vfclass.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x48,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 48 8c + +vfclass.v v8, v4 +# CHECK-INST: vfclass.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x48,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 48 8e + +vfmerge.vfm v8, v4, fa0, v0 +# CHECK-INST: vfmerge.vfm v8, v4, fa0, v0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 5c diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/freduction.s @@ -0,0 +1,81 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfredosum.vs v8, v4, v20, v0.t +# CHECK-INST: vfredosum.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 0c + +vfredosum.vs v8, v4, v20 +# CHECK-INST: vfredosum.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 0e + +vfredsum.vs v8, v4, v20, v0.t +# CHECK-INST: vfredsum.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x04] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 04 + +vfredsum.vs v8, v4, v20 +# CHECK-INST: vfredsum.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x06] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 06 + +vfredmax.vs v8, v4, v20, v0.t +# CHECK-INST: vfredmax.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 1c + +vfredmax.vs v8, v4, v20 +# CHECK-INST: vfredmax.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 1e + +vfredmin.vs v8, v4, v20, v0.t +# CHECK-INST: vfredmin.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x14] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 14 + +vfredmin.vs v8, v4, v20 +# CHECK-INST: vfredmin.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x16] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 16 + +vfwredosum.vs v8, v4, v20, v0.t +# CHECK-INST: vfwredosum.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a cc + +vfwredosum.vs v8, v4, v20 +# CHECK-INST: vfwredosum.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a ce + +vfwredsum.vs v8, v4, v20, v0.t +# CHECK-INST: vfwredsum.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xc4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a c4 + +vfwredsum.vs v8, v4, v20 +# CHECK-INST: vfwredsum.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xc6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a c6 diff --git a/llvm/test/MC/RISCV/rvv/fsub.s b/llvm/test/MC/RISCV/rvv/fsub.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/fsub.s @@ -0,0 +1,93 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfsub.vv v8, v4, v20, v0.t +# CHECK-INST: vfsub.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 08 + +vfsub.vv v8, v4, v20 +# CHECK-INST: vfsub.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 0a + +vfsub.vf v8, v4, fa0, v0.t +# CHECK-INST: vfsub.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 08 + +vfsub.vf v8, v4, fa0 +# CHECK-INST: vfsub.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 0a + +vfrsub.vf v8, v4, fa0, v0.t +# CHECK-INST: vfrsub.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 9c + +vfrsub.vf v8, v4, fa0 +# CHECK-INST: vfrsub.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 9e + +vfwsub.vv v8, v4, v20, v0.t +# CHECK-INST: vfwsub.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a c8 + +vfwsub.vv v8, v4, v20 +# CHECK-INST: vfwsub.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a ca + +vfwsub.vf v8, v4, fa0, v0.t +# CHECK-INST: vfwsub.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 c8 + +vfwsub.vf v8, v4, fa0 +# CHECK-INST: vfwsub.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 ca + +vfwsub.wv v8, v4, v20, v0.t +# CHECK-INST: vfwsub.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a d8 + +vfwsub.wv v8, v4, v20 +# CHECK-INST: vfwsub.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a da + +vfwsub.wf v8, v4, fa0, v0.t +# CHECK-INST: vfwsub.wf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 d8 + +vfwsub.wf v8, v4, fa0 +# CHECK-INST: vfwsub.wf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 da diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/invalid.s @@ -0,0 +1,780 @@ +# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-v --mattr=+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vsetvli a2, a0, e31 +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] + +vsetvli a2, a0, e32,m3 +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] + +vsetvli a2, a0, m1,e32 +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] + +vsetvli a2, a0, e32,m16 +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] + +vsetvli a2, a0, e2048,m8 +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] + +vsetvli a2, a0, e1,m8 +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] + +vadd.vv v1, v3, v2, v4.t +# CHECK-ERROR: operand must be v0.t + +vadd.vv v1, v3, v2, v0 +# CHECK-ERROR: expected '.t' suffix + +vmslt.vi v1, v2, -16 +# CHECK-ERROR: immediate must be in the range [-15, 16] + +vmslt.vi v1, v2, 17 +# CHECK-ERROR: immediate must be in the range [-15, 16] + +viota.m v0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: viota.m v0, v2, v0.t + +viota.m v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: viota.m v2, v2 + +vfwcvt.xu.f.v v0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v0, v2, v0.t + +vfwcvt.xu.f.v v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v2 + +vfwcvt.xu.f.v v2, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v3 + +vfwcvt.x.f.v v0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwcvt.x.f.v v0, v2, v0.t + +vfwcvt.x.f.v v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v2 + +vfwcvt.x.f.v v2, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v3 + +vfwcvt.f.xu.v v0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v0, v2, v0.t + +vfwcvt.f.xu.v v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v2 + +vfwcvt.f.xu.v v2, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v3 + +vfwcvt.f.x.v v0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwcvt.f.x.v v0, v2, v0.t + +vfwcvt.f.x.v v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v2 + +vfwcvt.f.x.v v2, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v3 + +vfwcvt.f.f.v v0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwcvt.f.f.v v0, v2, v0.t + +vfwcvt.f.f.v v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v2 + +vfwcvt.f.f.v v2, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v3 + +vslideup.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vslideup.vx v0, v2, a0, v0.t + +vslideup.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vslideup.vx v2, v2, a0 + +vslideup.vi v0, v2, 31, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vslideup.vi v0, v2, 31, v0.t + +vslideup.vi v2, v2, 31 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vslideup.vi v2, v2, 31 + +vslide1up.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vslide1up.vx v0, v2, a0, v0.t + +vslide1up.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vslide1up.vx v2, v2, a0 + +vnsrl.wv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4 + +vnsrl.wv v3, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsrl.wv v3, v2, v4 + +vnsrl.wx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0 + +vnsrl.wi v2, v2, 31 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsrl.wi v2, v2, 31 + +vnsra.wv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4 + +vnsra.wv v3, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsra.wv v3, v2, v4 + +vnsra.wx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0 + +vnsra.wi v2, v2, 31 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnsra.wi v2, v2, 31 + +vnclipu.wv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4 + +vnclipu.wv v3, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclipu.wv v3, v2, v4 + +vnclipu.wx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0 + +vnclipu.wi v2, v2, 31 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclipu.wi v2, v2, 31 + +vnclip.wv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4 + +vnclip.wv v3, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclip.wv v3, v2, v4 + +vnclip.wx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0 + +vnclip.wi v2, v2, 31 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vnclip.wi v2, v2, 31 + +vfncvt.xu.f.w v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2 + +vfncvt.xu.f.w v3, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.xu.f.w v3, v2 + +vfncvt.x.f.w v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2 + +vfncvt.x.f.w v3, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.x.f.w v3, v2 + +vfncvt.f.xu.w v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2 + +vfncvt.f.xu.w v3, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.f.xu.w v3, v2 + +vfncvt.f.x.w v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2 + +vfncvt.f.x.w v3, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.f.x.w v3, v2 + +vfncvt.f.f.w v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2 + +vfncvt.f.f.w v3, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.f.f.w v3, v2 + +vfncvt.rod.f.f.w v2, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2 + +vfncvt.rod.f.f.w v3, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v3, v2 + +vrgather.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t + +vrgather.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vrgather.vv v2, v2, v4 + +vrgather.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vrgather.vx v0, v2, a0, v0.t + +vrgather.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vrgather.vx v2, v2, a0 + +vrgather.vi v0, v2, 31, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vrgather.vi v0, v2, 31, v0.t + +vrgather.vi v2, v2, 31 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vrgather.vi v2, v2, 31 + +vwaddu.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwaddu.vv v0, v2, v4, v0.t + +vwaddu.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwaddu.vv v2, v2, v4 + +vwaddu.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwaddu.vv v2, v3, v4 + +vwsubu.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsubu.vv v0, v2, v4, v0.t + +vwsubu.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsubu.vv v2, v2, v4 + +vwsubu.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsubu.vv v2, v3, v4 + +vwadd.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwadd.vv v0, v2, v4, v0.t + +vwadd.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwadd.vv v2, v2, v4 + +vwadd.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwadd.vv v2, v3, v4 + +vwsub.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsub.vv v0, v2, v4, v0.t + +vwsub.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsub.vv v2, v2, v4 + +vwsub.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsub.vv v2, v3, v4 + +vwmul.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmul.vv v0, v2, v4, v0.t + +vwmul.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmul.vv v2, v2, v4 + +vwmul.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmul.vv v2, v3, v4 + +vwmulu.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmulu.vv v0, v2, v4, v0.t + +vwmulu.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulu.vv v2, v2, v4 + +vwmulu.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulu.vv v2, v3, v4 + +vwmulsu.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmulsu.vv v0, v2, v4, v0.t + +vwmulsu.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulsu.vv v2, v2, v4 + +vwmulsu.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulsu.vv v2, v3, v4 + +vwmaccu.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmaccu.vv v0, v4, v2, v0.t + +vwmaccu.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v2 + +vwmaccu.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v3 + +vwmacc.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmacc.vv v0, v4, v2, v0.t + +vwmacc.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v2 + +vwmacc.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v3 + +vwmaccsu.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmaccsu.vv v0, v4, v2, v0.t + +vwmaccsu.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v2 + +vwmaccsu.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v3 + +vfwadd.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwadd.vv v0, v2, v4, v0.t + +vfwadd.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwadd.vv v2, v2, v4 + +vfwadd.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwadd.vv v2, v3, v4 + +vfwsub.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwsub.vv v0, v2, v4, v0.t + +vfwsub.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwsub.vv v2, v2, v4 + +vfwsub.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwsub.vv v2, v3, v4 + +vfwmul.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwmul.vv v0, v2, v4, v0.t + +vfwmul.vv v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmul.vv v2, v2, v4 + +vfwmul.vv v2, v3, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmul.vv v2, v3, v4 + +vfwmacc.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwmacc.vv v0, v4, v2, v0.t + +vfwmacc.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v2 + +vfwmacc.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v3 + +vfwnmacc.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwnmacc.vv v0, v4, v2, v0.t + +vfwnmacc.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v2 + +vfwnmacc.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v3 + +vfwmsac.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwmsac.vv v0, v4, v2, v0.t + +vfwmsac.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v2 + +vfwmsac.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v3 + +vfwnmsac.vv v0, v4, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwnmsac.vv v0, v4, v2, v0.t + +vfwnmsac.vv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v2 + +vfwnmsac.vv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v3 + +vwaddu.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwaddu.vx v0, v2, a0, v0.t + +vwaddu.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwaddu.vx v2, v2, a0 + +vwaddu.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwaddu.vx v2, v3, a0 + +vwsubu.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsubu.vx v0, v2, a0, v0.t + +vwsubu.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsubu.vx v2, v2, a0 + +vwsubu.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsubu.vx v2, v3, a0 + +vwadd.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwadd.vx v0, v2, a0, v0.t + +vwadd.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwadd.vx v2, v2, a0 + +vwadd.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwadd.vx v2, v3, a0 + +vwsub.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsub.vx v0, v2, a0, v0.t + +vwsub.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsub.vx v2, v2, a0 + +vwsub.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsub.vx v2, v3, a0 + +vwmul.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmul.vx v0, v2, a0, v0.t + +vwmul.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmul.vx v2, v2, a0 + +vwmul.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmul.vx v2, v3, a0 + +vwmulu.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmulu.vx v0, v2, a0, v0.t + +vwmulu.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulu.vx v2, v2, a0 + +vwmulu.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulu.vx v2, v3, a0 + +vwmulsu.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmulsu.vx v0, v2, a0, v0.t + +vwmulsu.vx v2, v2, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulsu.vx v2, v2, a0 + +vwmulsu.vx v2, v3, a0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmulsu.vx v2, v3, a0 + +vwmaccu.vx v0, a0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmaccu.vx v0, a0, v2, v0.t + +vwmaccu.vx v2, a0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v2 + +vwmaccu.vx v2, a0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v3 + +vwmacc.vx v0, a0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmacc.vx v0, a0, v2, v0.t + +vwmacc.vx v2, a0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v2 + +vwmacc.vx v2, a0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v3 + +vwmaccsu.vx v0, a0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmaccsu.vx v0, a0, v2, v0.t + +vwmaccsu.vx v2, a0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v2 + +vwmaccsu.vx v2, a0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v3 + +vwmaccus.vx v0, a0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwmaccus.vx v0, a0, v2, v0.t + +vwmaccus.vx v2, a0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v2 + +vwmaccus.vx v2, a0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v3 + +vfwadd.vf v0, v2, fa0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwadd.vf v0, v2, fa0, v0.t + +vfwadd.vf v2, v2, fa0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwadd.vf v2, v2, fa0 + +vfwadd.vf v2, v3, fa0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwadd.vf v2, v3, fa0 + +vfwsub.vf v0, v2, fa0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwsub.vf v0, v2, fa0, v0.t + +vfwsub.vf v2, v2, fa0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwsub.vf v2, v2, fa0 + +vfwsub.vf v2, v3, fa0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwsub.vf v2, v3, fa0 + +vfwmul.vf v0, v2, fa0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwmul.vf v0, v2, fa0, v0.t + +vfwmul.vf v2, v2, fa0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmul.vf v2, v2, fa0 + +vfwmul.vf v2, v3, fa0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmul.vf v2, v3, fa0 + +vfwmacc.vf v0, fa0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwmacc.vf v0, fa0, v2, v0.t + +vfwmacc.vf v2, fa0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v2 + +vfwmacc.vf v2, fa0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v3 + +vfwnmacc.vf v0, fa0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwnmacc.vf v0, fa0, v2, v0.t + +vfwnmacc.vf v2, fa0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v2 + +vfwnmacc.vf v2, fa0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v3 + +vfwmsac.vf v0, fa0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwmsac.vf v0, fa0, v2, v0.t + +vfwmsac.vf v2, fa0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v2 + +vfwmsac.vf v2, fa0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v3 + +vfwnmsac.vf v0, fa0, v2, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwnmsac.vf v0, fa0, v2, v0.t + +vfwnmsac.vf v2, fa0, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v2 + +vfwnmsac.vf v2, fa0, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v3 + +vcompress.vm v2, v2, v4 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vcompress.vm v2, v2, v4 + +vwaddu.wv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwaddu.wv v0, v2, v4, v0.t + +vwaddu.wv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v2 + +vwaddu.wv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v3 + +vwsubu.wv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsubu.wv v0, v2, v4, v0.t + +vwsubu.wv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v2 + +vwsubu.wv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v3 + +vwadd.wv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwadd.wv v0, v2, v4, v0.t + +vwadd.wv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v2 + +vwadd.wv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v3 + +vwsub.wv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsub.wv v0, v2, v4, v0.t + +vwsub.wv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v2 + +vwsub.wv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v3 + +vfwadd.wv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwadd.wv v0, v2, v4, v0.t + +vfwadd.wv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v2 + +vfwadd.wv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v3 + +vfwsub.wv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwsub.wv v0, v2, v4, v0.t + +vfwsub.wv v2, v4, v2 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v2 + +vfwsub.wv v2, v4, v3 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v3 + +vwaddu.wx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwaddu.wx v0, v2, a0, v0.t + +vwsubu.wx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsubu.wx v0, v2, a0, v0.t + +vwadd.wx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwadd.wx v0, v2, a0, v0.t + +vwsub.wx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vwsub.wx v0, v2, a0, v0.t + +vfwadd.wf v0, v2, fa0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwadd.wf v0, v2, fa0, v0.t + +vfwsub.wf v0, v2, fa0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/load.s @@ -0,0 +1,339 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vlb.v v8, (a0), v0.t +# CHECK-INST: vlb.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 10 + +vlb.v v8, (a0) +# CHECK-INST: vlb.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 12 + +vlh.v v8, (a0), v0.t +# CHECK-INST: vlh.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 10 + +vlh.v v8, (a0) +# CHECK-INST: vlh.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 12 + +vlw.v v8, (a0), v0.t +# CHECK-INST: vlw.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 10 + +vlw.v v8, (a0) +# CHECK-INST: vlw.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 12 + +vlbu.v v8, (a0), v0.t +# CHECK-INST: vlbu.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 00 + +vlbu.v v8, (a0) +# CHECK-INST: vlbu.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 02 + +vlhu.v v8, (a0), v0.t +# CHECK-INST: vlhu.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 00 + +vlhu.v v8, (a0) +# CHECK-INST: vlhu.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 02 + +vlwu.v v8, (a0), v0.t +# CHECK-INST: vlwu.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 00 + +vlwu.v v8, (a0) +# CHECK-INST: vlwu.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 02 + +vlbff.v v8, (a0), v0.t +# CHECK-INST: vlbff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x11] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 11 + +vlbff.v v8, (a0) +# CHECK-INST: vlbff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x13] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 13 + +vlhff.v v8, (a0), v0.t +# CHECK-INST: vlhff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x11] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 11 + +vlhff.v v8, (a0) +# CHECK-INST: vlhff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x13] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 13 + +vlwff.v v8, (a0), v0.t +# CHECK-INST: vlwff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x11] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 11 + +vlwff.v v8, (a0) +# CHECK-INST: vlwff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x13] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 13 + +vlbuff.v v8, (a0), v0.t +# CHECK-INST: vlbuff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x01] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 01 + +vlbuff.v v8, (a0) +# CHECK-INST: vlbuff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x03] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 05 03 + +vlhuff.v v8, (a0), v0.t +# CHECK-INST: vlhuff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x01] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 01 + +vlhuff.v v8, (a0) +# CHECK-INST: vlhuff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x03] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 05 03 + +vlwuff.v v8, (a0), v0.t +# CHECK-INST: vlwuff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x01] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 01 + +vlwuff.v v8, (a0) +# CHECK-INST: vlwuff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x03] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 03 + +vleff.v v8, (a0), v0.t +# CHECK-INST: vleff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x01] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 05 01 + +vleff.v v8, (a0) +# CHECK-INST: vleff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x03] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 05 03 + +vlsb.v v8, (a0), a1, v0.t +# CHECK-INST: vlsb.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 b5 18 + +vlsb.v v8, (a0), a1 +# CHECK-INST: vlsb.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 b5 1a + +vlsh.v v8, (a0), a1, v0.t +# CHECK-INST: vlsh.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 b5 18 + +vlsh.v v8, (a0), a1 +# CHECK-INST: vlsh.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 b5 1a + +vlsw.v v8, (a0), a1, v0.t +# CHECK-INST: vlsw.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 b5 18 + +vlsw.v v8, (a0), a1 +# CHECK-INST: vlsw.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 b5 1a + +vlsbu.v v8, (a0), a1, v0.t +# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 b5 08 + +vlsbu.v v8, (a0), a1 +# CHECK-INST: vlsbu.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 b5 0a + +vlshu.v v8, (a0), a1, v0.t +# CHECK-INST: vlshu.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 b5 08 + +vlshu.v v8, (a0), a1 +# CHECK-INST: vlshu.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 b5 0a + +vlswu.v v8, (a0), a1, v0.t +# CHECK-INST: vlswu.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 b5 08 + +vlswu.v v8, (a0), a1 +# CHECK-INST: vlswu.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 b5 0a + +vlse.v v8, (a0), a1, v0.t +# CHECK-INST: vlse.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 b5 08 + +vlse.v v8, (a0), a1 +# CHECK-INST: vlse.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 b5 0a + +vlxb.v v8, (a0), v4, v0.t +# CHECK-INST: vlxb.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 45 1c + +vlxb.v v8, (a0), v4 +# CHECK-INST: vlxb.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 45 1e + +vlxh.v v8, (a0), v4, v0.t +# CHECK-INST: vlxh.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 45 1c + +vlxh.v v8, (a0), v4 +# CHECK-INST: vlxh.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 45 1e + +vlxw.v v8, (a0), v4, v0.t +# CHECK-INST: vlxw.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 45 1c + +vlxw.v v8, (a0), v4 +# CHECK-INST: vlxw.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 45 1e + +vlxbu.v v8, (a0), v4, v0.t +# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 45 0c + +vlxbu.v v8, (a0), v4 +# CHECK-INST: vlxbu.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 45 0e + +vlxhu.v v8, (a0), v4, v0.t +# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 45 0c + +vlxhu.v v8, (a0), v4 +# CHECK-INST: vlxhu.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 45 0e + +vlxwu.v v8, (a0), v4, v0.t +# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 45 0c + +vlxwu.v v8, (a0), v4 +# CHECK-INST: vlxwu.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 45 0e + +vlxe.v v8, (a0), v4, v0.t +# CHECK-INST: vlxe.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 45 0c + +vlxe.v v8, (a0), v4 +# CHECK-INST: vlxe.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 45 0e + +vl1r.v v8, (a0) +# CHECK-INST: vl1r.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x85,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 85 02 diff --git a/llvm/test/MC/RISCV/rvv/macc.s b/llvm/test/MC/RISCV/rvv/macc.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/macc.s @@ -0,0 +1,189 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmacc.vv v8, v20, v4, v0.t +# CHECK-INST: vmacc.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a b4 + +vmacc.vv v8, v20, v4 +# CHECK-INST: vmacc.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a b6 + +vmacc.vx v8, a0, v4, v0.t +# CHECK-INST: vmacc.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 b4 + +vmacc.vx v8, a0, v4 +# CHECK-INST: vmacc.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 b6 + +vnmsac.vv v8, v20, v4, v0.t +# CHECK-INST: vnmsac.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a bc + +vnmsac.vv v8, v20, v4 +# CHECK-INST: vnmsac.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a be + +vnmsac.vx v8, a0, v4, v0.t +# CHECK-INST: vnmsac.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 bc + +vnmsac.vx v8, a0, v4 +# CHECK-INST: vnmsac.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 be + +vmadd.vv v8, v20, v4, v0.t +# CHECK-INST: vmadd.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a a4 + +vmadd.vv v8, v20, v4 +# CHECK-INST: vmadd.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a a6 + +vmadd.vx v8, a0, v4, v0.t +# CHECK-INST: vmadd.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 a4 + +vmadd.vx v8, a0, v4 +# CHECK-INST: vmadd.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 a6 + +vnmsub.vv v8, v20, v4, v0.t +# CHECK-INST: vnmsub.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ac + +vnmsub.vv v8, v20, v4 +# CHECK-INST: vnmsub.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ae + +vnmsub.vx v8, a0, v4, v0.t +# CHECK-INST: vnmsub.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ac + +vnmsub.vx v8, a0, v4 +# CHECK-INST: vnmsub.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ae + +vwmaccu.vv v8, v20, v4, v0.t +# CHECK-INST: vwmaccu.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a f0 + +vwmaccu.vv v8, v20, v4 +# CHECK-INST: vwmaccu.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a f2 + +vwmaccu.vx v8, a0, v4, v0.t +# CHECK-INST: vwmaccu.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 f0 + +vwmaccu.vx v8, a0, v4 +# CHECK-INST: vwmaccu.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 f2 + +vwmacc.vv v8, v20, v4, v0.t +# CHECK-INST: vwmacc.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xf4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a f4 + +vwmacc.vv v8, v20, v4 +# CHECK-INST: vwmacc.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xf6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a f6 + +vwmacc.vx v8, a0, v4, v0.t +# CHECK-INST: vwmacc.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xf4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 f4 + +vwmacc.vx v8, a0, v4 +# CHECK-INST: vwmacc.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xf6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 f6 + +vwmaccsu.vv v8, v20, v4, v0.t +# CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a fc + +vwmaccsu.vv v8, v20, v4 +# CHECK-INST: vwmaccsu.vv v8, v20, v4 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a fe + +vwmaccsu.vx v8, a0, v4, v0.t +# CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 fc + +vwmaccsu.vx v8, a0, v4 +# CHECK-INST: vwmaccsu.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 fe + +vwmaccus.vx v8, a0, v4, v0.t +# CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 f8 + +vwmaccus.vx v8, a0, v4 +# CHECK-INST: vwmaccus.vx v8, a0, v4 +# CHECK-ENCODING: [0x57,0x64,0x45,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 fa diff --git a/llvm/test/MC/RISCV/rvv/mask.s b/llvm/test/MC/RISCV/rvv/mask.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/mask.s @@ -0,0 +1,165 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmand.mm v8, v4, v20 +# CHECK-INST: vmand.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 66 + +vmnand.mm v8, v4, v20 +# CHECK-INST: vmnand.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 76 + +vmandnot.mm v8, v4, v20 +# CHECK-INST: vmandnot.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 62 + +vmxor.mm v8, v4, v20 +# CHECK-INST: vmxor.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 6e + +vmor.mm v8, v4, v20 +# CHECK-INST: vmor.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 6a + +vmnor.mm v8, v4, v20 +# CHECK-INST: vmnor.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 7a + +vmornot.mm v8, v4, v20 +# CHECK-INST: vmornot.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 72 + +vmxnor.mm v8, v4, v20 +# CHECK-INST: vmxnor.mm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 7e + +vpopc.m a2, v4, v0.t +# CHECK-INST: vpopc.m a2, v4, v0.t +# CHECK-ENCODING: [0x57,0x26,0x48,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 26 48 40 + +vpopc.m a2, v4 +# CHECK-INST: vpopc.m a2, v4 +# CHECK-ENCODING: [0x57,0x26,0x48,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 26 48 42 + +vfirst.m a2, v4, v0.t +# CHECK-INST: vfirst.m a2, v4, v0.t +# CHECK-ENCODING: [0x57,0xa6,0x48,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a6 48 40 + +vfirst.m a2, v4 +# CHECK-INST: vfirst.m a2, v4 +# CHECK-ENCODING: [0x57,0xa6,0x48,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a6 48 42 + +vmsbf.m v8, v4, v0.t +# CHECK-INST: vmsbf.m v8, v4, v0.t +# CHECK-ENCODING: [0x57,0xa4,0x40,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 40 50 + +vmsbf.m v8, v4 +# CHECK-INST: vmsbf.m v8, v4 +# CHECK-ENCODING: [0x57,0xa4,0x40,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 40 52 + +vmsif.m v8, v4, v0.t +# CHECK-INST: vmsif.m v8, v4, v0.t +# CHECK-ENCODING: [0x57,0xa4,0x41,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 41 50 + +vmsif.m v8, v4 +# CHECK-INST: vmsif.m v8, v4 +# CHECK-ENCODING: [0x57,0xa4,0x41,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 41 52 + +vmsof.m v8, v4, v0.t +# CHECK-INST: vmsof.m v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x41,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 41 50 + +vmsof.m v8, v4 +# CHECK-INST: vmsof.m v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x41,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 41 52 + +viota.m v8, v4, v0.t +# CHECK-INST: viota.m v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x48,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 48 50 + +viota.m v8, v4 +# CHECK-INST: viota.m v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x48,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 48 52 + +vid.v v8, v0.t +# CHECK-INST: vid.v v8, v0.t +# CHECK-ENCODING: [0x57,0xa4,0x08,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 08 50 + +vid.v v8 +# CHECK-INST: vid.v v8 +# CHECK-ENCODING: [0x57,0xa4,0x08,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 08 52 + +vmcpy.m v8, v4 +# CHECK-INST: vmcpy.m v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x42,0x66] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 42 66 + +vmclr.m v8 +# CHECK-INST: vmclr.m v8 +# CHECK-ENCODING: [0x57,0x24,0x84,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 84 6e + +vmset.m v8 +# CHECK-INST: vmset.m v8 +# CHECK-ENCODING: [0x57,0x24,0x84,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 84 7e + +vmnot.m v8, v4 +# CHECK-INST: vmnot.m v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x42,0x76] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 42 76 diff --git a/llvm/test/MC/RISCV/rvv/minmax.s b/llvm/test/MC/RISCV/rvv/minmax.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/minmax.s @@ -0,0 +1,105 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vminu.vv v8, v4, v20, v0.t +# CHECK-INST: vminu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 10 + +vminu.vv v8, v4, v20 +# CHECK-INST: vminu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 12 + +vminu.vx v8, v4, a0, v0.t +# CHECK-INST: vminu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 10 + +vminu.vx v8, v4, a0 +# CHECK-INST: vminu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 12 + +vmin.vv v8, v4, v20, v0.t +# CHECK-INST: vmin.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x14] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 14 + +vmin.vv v8, v4, v20 +# CHECK-INST: vmin.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x16] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 16 + +vmin.vx v8, v4, a0, v0.t +# CHECK-INST: vmin.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x14] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 14 + +vmin.vx v8, v4, a0 +# CHECK-INST: vmin.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x16] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 16 + +vmaxu.vv v8, v4, v20, v0.t +# CHECK-INST: vmaxu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 18 + +vmaxu.vv v8, v4, v20 +# CHECK-INST: vmaxu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 1a + +vmaxu.vx v8, v4, a0, v0.t +# CHECK-INST: vmaxu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 18 + +vmaxu.vx v8, v4, a0 +# CHECK-INST: vmaxu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 1a + +vmax.vv v8, v4, v20, v0.t +# CHECK-INST: vmax.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 1c + +vmax.vv v8, v4, v20 +# CHECK-INST: vmax.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 1e + +vmax.vx v8, v4, a0, v0.t +# CHECK-INST: vmax.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 1c + +vmax.vx v8, v4, a0 +# CHECK-INST: vmax.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 1e diff --git a/llvm/test/MC/RISCV/rvv/mul.s b/llvm/test/MC/RISCV/rvv/mul.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/mul.s @@ -0,0 +1,201 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmul.vv v8, v4, v20, v0.t +# CHECK-INST: vmul.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x94] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 94 + +vmul.vv v8, v4, v20 +# CHECK-INST: vmul.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x96] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 96 + +vmul.vx v8, v4, a0, v0.t +# CHECK-INST: vmul.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x94] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 94 + +vmul.vx v8, v4, a0 +# CHECK-INST: vmul.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x96] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 96 + +vmulh.vv v8, v4, v20, v0.t +# CHECK-INST: vmulh.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 9c + +vmulh.vv v8, v4, v20 +# CHECK-INST: vmulh.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 9e + +vmulh.vx v8, v4, a0, v0.t +# CHECK-INST: vmulh.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 9c + +vmulh.vx v8, v4, a0 +# CHECK-INST: vmulh.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 9e + +vmulhu.vv v8, v4, v20, v0.t +# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 90 + +vmulhu.vv v8, v4, v20 +# CHECK-INST: vmulhu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 92 + +vmulhu.vx v8, v4, a0, v0.t +# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 90 + +vmulhu.vx v8, v4, a0 +# CHECK-INST: vmulhu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 92 + +vmulhsu.vv v8, v4, v20, v0.t +# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 98 + +vmulhsu.vv v8, v4, v20 +# CHECK-INST: vmulhsu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 9a + +vmulhsu.vx v8, v4, a0, v0.t +# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 98 + +vmulhsu.vx v8, v4, a0 +# CHECK-INST: vmulhsu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 9a + +vwmul.vv v8, v4, v20, v0.t +# CHECK-INST: vwmul.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ec + +vwmul.vv v8, v4, v20 +# CHECK-INST: vwmul.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ee + +vwmul.vx v8, v4, a0, v0.t +# CHECK-INST: vwmul.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ec + +vwmul.vx v8, v4, a0 +# CHECK-INST: vwmul.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ee + +vwmulu.vv v8, v4, v20, v0.t +# CHECK-INST: vwmulu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a e0 + +vwmulu.vv v8, v4, v20 +# CHECK-INST: vwmulu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a e2 + +vwmulu.vx v8, v4, a0, v0.t +# CHECK-INST: vwmulu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 e0 + +vwmulu.vx v8, v4, a0 +# CHECK-INST: vwmulu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 e2 + +vwmulsu.vv v8, v4, v20, v0.t +# CHECK-INST: vwmulsu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a e8 + +vwmulsu.vv v8, v4, v20 +# CHECK-INST: vwmulsu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ea + +vwmulsu.vx v8, v4, a0, v0.t +# CHECK-INST: vwmulsu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 e8 + +vwmulsu.vx v8, v4, a0 +# CHECK-INST: vwmulsu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ea + +vsmul.vv v8, v4, v20, v0.t +# CHECK-INST: vsmul.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 9c + +vsmul.vv v8, v4, v20 +# CHECK-INST: vsmul.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 9e + +vsmul.vx v8, v4, a0, v0.t +# CHECK-INST: vsmul.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 9c + +vsmul.vx v8, v4, a0 +# CHECK-INST: vsmul.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 9e diff --git a/llvm/test/MC/RISCV/rvv/mv.s b/llvm/test/MC/RISCV/rvv/mv.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/mv.s @@ -0,0 +1,63 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmv.v.v v8, v20 +# CHECK-INST: vmv.v.v v8, v20 +# CHECK-ENCODING: [0x57,0x04,0x0a,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 0a 5e + +vmv.v.x v8, a0 +# CHECK-INST: vmv.v.x v8, a0 +# CHECK-ENCODING: [0x57,0x44,0x05,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 05 5e + +vmv.v.i v8, 15 +# CHECK-INST: vmv.v.i v8, 15 +# CHECK-ENCODING: [0x57,0xb4,0x07,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 07 5e + +vmv.x.s a2, v4 +# CHECK-INST: vmv.x.s a2, v4 +# CHECK-ENCODING: [0x57,0x26,0x40,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 26 40 42 + +vmv.s.x v8, a0 +# CHECK-INST: vmv.s.x v8, a0 +# CHECK-ENCODING: [0x57,0x64,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 05 42 + +vmv1r.v v8, v4 +# CHECK-INST: vmv1r.v v8, v4 +# CHECK-ENCODING: [0x57,0x34,0x40,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 34 40 9e + +vmv2r.v v8, v4 +# CHECK-INST: vmv2r.v v8, v4 +# CHECK-ENCODING: [0x57,0xb4,0x40,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 40 9e + +vmv4r.v v8, v4 +# CHECK-INST: vmv4r.v v8, v4 +# CHECK-ENCODING: [0x57,0xb4,0x41,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 41 9e + +vmv8r.v v8, v24 +# CHECK-INST: vmv8r.v v8, v24 +# CHECK-ENCODING: [0x57,0xb4,0x83,0x9f] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 83 9f diff --git a/llvm/test/MC/RISCV/rvv/or.s b/llvm/test/MC/RISCV/rvv/or.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/or.s @@ -0,0 +1,45 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vor.vv v8, v4, v20, v0.t +# CHECK-INST: vor.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 28 + +vor.vv v8, v4, v20 +# CHECK-INST: vor.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 2a + +vor.vx v8, v4, a0, v0.t +# CHECK-INST: vor.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 28 + +vor.vx v8, v4, a0 +# CHECK-INST: vor.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 2a + +vor.vi v8, v4, 15, v0.t +# CHECK-INST: vor.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 28 + +vor.vi v8, v4, 15 +# CHECK-INST: vor.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 2a diff --git a/llvm/test/MC/RISCV/rvv/others.s b/llvm/test/MC/RISCV/rvv/others.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/others.s @@ -0,0 +1,141 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vmerge.vvm v8, v4, v20, v0 +# CHECK-INST: vmerge.vvm v8, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 5c + +vmerge.vxm v8, v4, a0, v0 +# CHECK-INST: vmerge.vxm v8, v4, a0, v0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 5c + +vmerge.vim v8, v4, 15, v0 +# CHECK-INST: vmerge.vim v8, v4, 15, v0 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 5c + +vslideup.vx v8, v4, a0, v0.t +# CHECK-INST: vslideup.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 38 + +vslideup.vx v8, v4, a0 +# CHECK-INST: vslideup.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 3a + +vslideup.vi v8, v4, 31, v0.t +# CHECK-INST: vslideup.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 38 + +vslideup.vi v8, v4, 31 +# CHECK-INST: vslideup.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 3a + +vslidedown.vx v8, v4, a0, v0.t +# CHECK-INST: vslidedown.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 3c + +vslidedown.vx v8, v4, a0 +# CHECK-INST: vslidedown.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 3e + +vslidedown.vi v8, v4, 31, v0.t +# CHECK-INST: vslidedown.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 3c + +vslidedown.vi v8, v4, 31 +# CHECK-INST: vslidedown.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 3e + +vslide1up.vx v8, v4, a0, v0.t +# CHECK-INST: vslide1up.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 38 + +vslide1up.vx v8, v4, a0 +# CHECK-INST: vslide1up.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 3a + +vslide1down.vx v8, v4, a0, v0.t +# CHECK-INST: vslide1down.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 3c + +vslide1down.vx v8, v4, a0 +# CHECK-INST: vslide1down.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 3e + +vrgather.vv v8, v4, v20, v0.t +# CHECK-INST: vrgather.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 30 + +vrgather.vv v8, v4, v20 +# CHECK-INST: vrgather.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 32 + +vrgather.vx v8, v4, a0, v0.t +# CHECK-INST: vrgather.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 30 + +vrgather.vx v8, v4, a0 +# CHECK-INST: vrgather.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 32 + +vrgather.vi v8, v4, 31, v0.t +# CHECK-INST: vrgather.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 30 + +vrgather.vi v8, v4, 31 +# CHECK-INST: vrgather.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 32 + +vcompress.vm v8, v4, v20 +# CHECK-INST: vcompress.vm v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 5e diff --git a/llvm/test/MC/RISCV/rvv/reduction.s b/llvm/test/MC/RISCV/rvv/reduction.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/reduction.s @@ -0,0 +1,129 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vredsum.vs v8, v4, v20, v0.t +# CHECK-INST: vredsum.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 00 + +vredsum.vs v8, v4, v20 +# CHECK-INST: vredsum.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 02 + +vredmaxu.vs v8, v4, v20, v0.t +# CHECK-INST: vredmaxu.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 18 + +vredmaxu.vs v8, v4, v20 +# CHECK-INST: vredmaxu.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 1a + +vredmax.vs v8, v4, v20, v0.t +# CHECK-INST: vredmax.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 1c + +vredmax.vs v8, v4, v20 +# CHECK-INST: vredmax.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 1e + +vredminu.vs v8, v4, v20, v0.t +# CHECK-INST: vredminu.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 10 + +vredminu.vs v8, v4, v20 +# CHECK-INST: vredminu.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 12 + +vredmin.vs v8, v4, v20, v0.t +# CHECK-INST: vredmin.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x14] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 14 + +vredmin.vs v8, v4, v20 +# CHECK-INST: vredmin.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x16] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 16 + +vredand.vs v8, v4, v20, v0.t +# CHECK-INST: vredand.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x04] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 04 + +vredand.vs v8, v4, v20 +# CHECK-INST: vredand.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x06] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 06 + +vredor.vs v8, v4, v20, v0.t +# CHECK-INST: vredor.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 08 + +vredor.vs v8, v4, v20 +# CHECK-INST: vredor.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 0a + +vredxor.vs v8, v4, v20, v0.t +# CHECK-INST: vredxor.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 0c + +vredxor.vs v8, v4, v20 +# CHECK-INST: vredxor.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 0e + +vwredsumu.vs v8, v4, v20, v0.t +# CHECK-INST: vwredsumu.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a c0 + +vwredsumu.vs v8, v4, v20 +# CHECK-INST: vwredsumu.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a c2 + +vwredsum.vs v8, v4, v20, v0.t +# CHECK-INST: vwredsum.vs v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xc4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a c4 + +vwredsum.vs v8, v4, v20 +# CHECK-INST: vwredsum.vs v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xc6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a c6 diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/shift.s @@ -0,0 +1,261 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsll.vv v8, v4, v20, v0.t +# CHECK-INST: vsll.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x94] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 94 + +vsll.vv v8, v4, v20 +# CHECK-INST: vsll.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x96] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 96 + +vsll.vx v8, v4, a0, v0.t +# CHECK-INST: vsll.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x94] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 94 + +vsll.vx v8, v4, a0 +# CHECK-INST: vsll.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x96] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 96 + +vsll.vi v8, v4, 31, v0.t +# CHECK-INST: vsll.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x94] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 94 + +vsll.vi v8, v4, 31 +# CHECK-INST: vsll.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x96] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 96 + +vsrl.vv v8, v4, v20, v0.t +# CHECK-INST: vsrl.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a a0 + +vsrl.vv v8, v4, v20 +# CHECK-INST: vsrl.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a a2 + +vsrl.vx v8, v4, a0, v0.t +# CHECK-INST: vsrl.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 a0 + +vsrl.vx v8, v4, a0 +# CHECK-INST: vsrl.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 a2 + +vsrl.vi v8, v4, 31, v0.t +# CHECK-INST: vsrl.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f a0 + +vsrl.vi v8, v4, 31 +# CHECK-INST: vsrl.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f a2 + +vsra.vv v8, v4, v20, v0.t +# CHECK-INST: vsra.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a a4 + +vsra.vv v8, v4, v20 +# CHECK-INST: vsra.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a a6 + +vsra.vx v8, v4, a0, v0.t +# CHECK-INST: vsra.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 a4 + +vsra.vx v8, v4, a0 +# CHECK-INST: vsra.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 a6 + +vsra.vi v8, v4, 31, v0.t +# CHECK-INST: vsra.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f a4 + +vsra.vi v8, v4, 31 +# CHECK-INST: vsra.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f a6 + +vnsrl.wv v8, v4, v20, v0.t +# CHECK-INST: vnsrl.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a b0 + +vnsrl.wv v8, v4, v20 +# CHECK-INST: vnsrl.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a b2 + +vnsrl.wx v8, v4, a0, v0.t +# CHECK-INST: vnsrl.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 b0 + +vnsrl.wx v8, v4, a0 +# CHECK-INST: vnsrl.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 b2 + +vnsrl.wi v8, v4, 31, v0.t +# CHECK-INST: vnsrl.wi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f b0 + +vnsrl.wi v8, v4, 31 +# CHECK-INST: vnsrl.wi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f b2 + +vnsra.wv v8, v4, v20, v0.t +# CHECK-INST: vnsra.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a b4 + +vnsra.wv v8, v4, v20 +# CHECK-INST: vnsra.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a b6 + +vnsra.wx v8, v4, a0, v0.t +# CHECK-INST: vnsra.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 b4 + +vnsra.wx v8, v4, a0 +# CHECK-INST: vnsra.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 b6 + +vnsra.wi v8, v4, 31, v0.t +# CHECK-INST: vnsra.wi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f b4 + +vnsra.wi v8, v4, 31 +# CHECK-INST: vnsra.wi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f b6 + +vssrl.vv v8, v4, v20, v0.t +# CHECK-INST: vssrl.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a a8 + +vssrl.vv v8, v4, v20 +# CHECK-INST: vssrl.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a aa + +vssrl.vx v8, v4, a0, v0.t +# CHECK-INST: vssrl.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 a8 + +vssrl.vx v8, v4, a0 +# CHECK-INST: vssrl.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 aa + +vssrl.vi v8, v4, 31, v0.t +# CHECK-INST: vssrl.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f a8 + +vssrl.vi v8, v4, 31 +# CHECK-INST: vssrl.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f aa + +vssra.vv v8, v4, v20, v0.t +# CHECK-INST: vssra.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a ac + +vssra.vv v8, v4, v20 +# CHECK-INST: vssra.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a ae + +vssra.vx v8, v4, a0, v0.t +# CHECK-INST: vssra.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 ac + +vssra.vx v8, v4, a0 +# CHECK-INST: vssra.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 ae + +vssra.vi v8, v4, 31, v0.t +# CHECK-INST: vssra.vi v8, v4, 31, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f ac + +vssra.vi v8, v4, 31 +# CHECK-INST: vssra.vi v8, v4, 31 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f ae diff --git a/llvm/test/MC/RISCV/rvv/sign-injection.s b/llvm/test/MC/RISCV/rvv/sign-injection.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/sign-injection.s @@ -0,0 +1,81 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vfsgnj.vv v8, v4, v20, v0.t +# CHECK-INST: vfsgnj.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 20 + +vfsgnj.vv v8, v4, v20 +# CHECK-INST: vfsgnj.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 22 + +vfsgnj.vf v8, v4, fa0, v0.t +# CHECK-INST: vfsgnj.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 20 + +vfsgnj.vf v8, v4, fa0 +# CHECK-INST: vfsgnj.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 22 + +vfsgnjn.vv v8, v4, v20, v0.t +# CHECK-INST: vfsgnjn.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 24 + +vfsgnjn.vv v8, v4, v20 +# CHECK-INST: vfsgnjn.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 26 + +vfsgnjn.vf v8, v4, fa0, v0.t +# CHECK-INST: vfsgnjn.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x24] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 24 + +vfsgnjn.vf v8, v4, fa0 +# CHECK-INST: vfsgnjn.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x26] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 26 + +vfsgnjx.vv v8, v4, v20, v0.t +# CHECK-INST: vfsgnjx.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4a,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 28 + +vfsgnjx.vv v8, v4, v20 +# CHECK-INST: vfsgnjx.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x14,0x4a,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4a 2a + +vfsgnjx.vf v8, v4, fa0, v0.t +# CHECK-INST: vfsgnjx.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 28 + +vfsgnjx.vf v8, v4, fa0 +# CHECK-INST: vfsgnjx.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 2a diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/snippet.s @@ -0,0 +1,32 @@ +## A snippet from https://github.com/riscv/riscv-v-spec. + +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST + +loop: + vsetvli a3, a0, e16,m4 # vtype = 16-bit integer vectors +# CHECK-INST: d7 76 65 00 vsetvli a3, a0, e16,m4 + vlh.v v4, (a1) # Get 16b vector +# CHECK-INST: 07 d2 05 12 vlh.v v4, (a1) + slli t1, a3, 1 # Multiply length by two bytes/element +# CHECK-INST: 13 93 16 00 slli t1, a3, 1 + add a1, a1, t1 # Bump pointer +# CHECK-INST: b3 85 65 00 add a1, a1, t1 + vwmul.vx v8, v4, x10 # 32b in +# CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0 + + vsetvli x0, a0, e32,m8 # Operate on 32b values +# CHECK-INST: 57 70 b5 00 vsetvli zero, a0, e32,m8 + vsrl.vi v8, v8, 3 +# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3 + vsw.v v8, (a2) # Store vector of 32b +# CHECK-INST: 27 64 06 02 vsw.v v8, (a2) + slli t1, a3, 2 # Multiply length by four bytes/element +# CHECK-INST: 13 93 26 00 slli t1, a3, 2 + add a2, a2, t1 # Bump pointer +# CHECK-INST: 33 06 66 00 add a2, a2, t1 + sub a0, a0, a3 # Decrement count +# CHECK-INST: 33 05 d5 40 sub a0, a0, a3 + bnez a0, loop # Any more? +# CHECK-INST: e3 1a 05 fc bnez a0, -44 diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/store.s @@ -0,0 +1,207 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsb.v v24, (a0), v0.t +# CHECK-INST: vsb.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 05 00 + +vsb.v v24, (a0) +# CHECK-INST: vsb.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 05 02 + +vsh.v v24, (a0), v0.t +# CHECK-INST: vsh.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 05 00 + +vsh.v v24, (a0) +# CHECK-INST: vsh.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 05 02 + +vsw.v v24, (a0), v0.t +# CHECK-INST: vsw.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 05 00 + +vsw.v v24, (a0) +# CHECK-INST: vsw.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 05 02 + +vse.v v24, (a0), v0.t +# CHECK-INST: vse.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 05 00 + +vse.v v24, (a0) +# CHECK-INST: vse.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 05 02 + +vssb.v v24, (a0), a1, v0.t +# CHECK-INST: vssb.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c b5 08 + +vssb.v v24, (a0), a1 +# CHECK-INST: vssb.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c b5 0a + +vssh.v v24, (a0), a1, v0.t +# CHECK-INST: vssh.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c b5 08 + +vssh.v v24, (a0), a1 +# CHECK-INST: vssh.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c b5 0a + +vssw.v v24, (a0), a1, v0.t +# CHECK-INST: vssw.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c b5 08 + +vssw.v v24, (a0), a1 +# CHECK-INST: vssw.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c b5 0a + +vsse.v v24, (a0), a1, v0.t +# CHECK-INST: vsse.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c b5 08 + +vsse.v v24, (a0), a1 +# CHECK-INST: vsse.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c b5 0a + +vsxb.v v24, (a0), v4, v0.t +# CHECK-INST: vsxb.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 45 0c + +vsxb.v v24, (a0), v4 +# CHECK-INST: vsxb.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 45 0e + +vsxh.v v24, (a0), v4, v0.t +# CHECK-INST: vsxh.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 45 0c + +vsxh.v v24, (a0), v4 +# CHECK-INST: vsxh.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 45 0e + +vsxw.v v24, (a0), v4, v0.t +# CHECK-INST: vsxw.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 45 0c + +vsxw.v v24, (a0), v4 +# CHECK-INST: vsxw.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 45 0e + +vsxe.v v24, (a0), v4, v0.t +# CHECK-INST: vsxe.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 45 0c + +vsxe.v v24, (a0), v4 +# CHECK-INST: vsxe.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 45 0e + +vsuxb.v v24, (a0), v4, v0.t +# CHECK-INST: vsuxb.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 45 1c + +vsuxb.v v24, (a0), v4 +# CHECK-INST: vsuxb.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 45 1e + +vsuxh.v v24, (a0), v4, v0.t +# CHECK-INST: vsuxh.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 45 1c + +vsuxh.v v24, (a0), v4 +# CHECK-INST: vsuxh.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 45 1e + +vsuxw.v v24, (a0), v4, v0.t +# CHECK-INST: vsuxw.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 45 1c + +vsuxw.v v24, (a0), v4 +# CHECK-INST: vsuxw.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 45 1e + +vsuxe.v v24, (a0), v4, v0.t +# CHECK-INST: vsuxe.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 45 1c + +vsuxe.v v24, (a0), v4 +# CHECK-INST: vsuxe.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 45 1e + +vs1r.v v24, (a0) +# CHECK-INST: vs1r.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x85,0x02] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 85 02 diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/sub.s @@ -0,0 +1,285 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsub.vv v8, v4, v20, v0.t +# CHECK-INST: vsub.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 08 + +vsub.vv v8, v4, v20 +# CHECK-INST: vsub.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 0a + +vsub.vx v8, v4, a0, v0.t +# CHECK-INST: vsub.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 08 + +vsub.vx v8, v4, a0 +# CHECK-INST: vsub.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x0a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 0a + +vrsub.vx v8, v4, a0, v0.t +# CHECK-INST: vrsub.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 0c + +vrsub.vx v8, v4, a0 +# CHECK-INST: vrsub.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 0e + +vrsub.vi v8, v4, 15, v0.t +# CHECK-INST: vrsub.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 0c + +vrsub.vi v8, v4, 15 +# CHECK-INST: vrsub.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 0e + +vwsubu.vv v8, v4, v20, v0.t +# CHECK-INST: vwsubu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a c8 + +vwsubu.vv v8, v4, v20 +# CHECK-INST: vwsubu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ca + +vwsubu.vx v8, v4, a0, v0.t +# CHECK-INST: vwsubu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 c8 + +vwsubu.vx v8, v4, a0 +# CHECK-INST: vwsubu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ca + +vwsub.vv v8, v4, v20, v0.t +# CHECK-INST: vwsub.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a cc + +vwsub.vv v8, v4, v20 +# CHECK-INST: vwsub.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a ce + +vwsub.vx v8, v4, a0, v0.t +# CHECK-INST: vwsub.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 cc + +vwsub.vx v8, v4, a0 +# CHECK-INST: vwsub.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 ce + +vwsubu.wv v8, v4, v20, v0.t +# CHECK-INST: vwsubu.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a d8 + +vwsubu.wv v8, v4, v20 +# CHECK-INST: vwsubu.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a da + +vwsubu.wx v8, v4, a0, v0.t +# CHECK-INST: vwsubu.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 d8 + +vwsubu.wx v8, v4, a0 +# CHECK-INST: vwsubu.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 da + +vwsub.wv v8, v4, v20, v0.t +# CHECK-INST: vwsub.wv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a dc + +vwsub.wv v8, v4, v20 +# CHECK-INST: vwsub.wv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a de + +vwsub.wx v8, v4, a0, v0.t +# CHECK-INST: vwsub.wx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 dc + +vwsub.wx v8, v4, a0 +# CHECK-INST: vwsub.wx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 de + +vsbc.vvm v8, v4, v20, v0 +# CHECK-INST: vsbc.vvm v8, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 48 + +vsbc.vxm v8, v4, a0, v0 +# CHECK-INST: vsbc.vxm v8, v4, a0, v0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 48 + +vmsbc.vvm v8, v4, v20, v0 +# CHECK-INST: vmsbc.vvm v8, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 4c + +vmsbc.vxm v8, v4, a0, v0 +# CHECK-INST: vmsbc.vxm v8, v4, a0, v0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 4c + +vmsbc.vv v8, v4, v20 +# CHECK-INST: vmsbc.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 4e + +vmsbc.vx v8, v4, a0 +# CHECK-INST: vmsbc.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 4e + +vssubu.vv v8, v4, v20, v0.t +# CHECK-INST: vssubu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 88 + +vssubu.vv v8, v4, v20 +# CHECK-INST: vssubu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 8a + +vssubu.vx v8, v4, a0, v0.t +# CHECK-INST: vssubu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 88 + +vssubu.vx v8, v4, a0 +# CHECK-INST: vssubu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 8a + +vssub.vv v8, v4, v20, v0.t +# CHECK-INST: vssub.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 8c + +vssub.vv v8, v4, v20 +# CHECK-INST: vssub.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 8e + +vssub.vx v8, v4, a0, v0.t +# CHECK-INST: vssub.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 8c + +vssub.vx v8, v4, a0 +# CHECK-INST: vssub.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 8e + +vasub.vv v8, v4, v20, v0.t +# CHECK-INST: vasub.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 2c + +vasub.vv v8, v4, v20 +# CHECK-INST: vasub.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 2e + +vasub.vx v8, v4, a0, v0.t +# CHECK-INST: vasub.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 2c + +vasub.vx v8, v4, a0 +# CHECK-INST: vasub.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 2e + +vasubu.vv v8, v4, v20, v0.t +# CHECK-INST: vasubu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 28 + +vasubu.vv v8, v4, v20 +# CHECK-INST: vasubu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 4a 2a + +vasubu.vx v8, v4, a0, v0.t +# CHECK-INST: vasubu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 28 + +vasubu.vx v8, v4, a0 +# CHECK-INST: vasubu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 64 45 2a diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/vsetvl.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsetvli a2, a0, e32,m4 +# CHECK-INST: vsetvli a2, a0, e32,m4 +# CHECK-ENCODING: [0x57,0x76,0xa5,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 a5 00 + +vsetvl a2, a0, a1 +# CHECK-INST: vsetvl a2, a0, a1 +# CHECK-ENCODING: [0x57,0x76,0xb5,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 b5 80 diff --git a/llvm/test/MC/RISCV/rvv/xor.s b/llvm/test/MC/RISCV/rvv/xor.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/xor.s @@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vxor.vv v8, v4, v20, v0.t +# CHECK-INST: vxor.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x04,0x4a,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 2c + +vxor.vv v8, v4, v20 +# CHECK-INST: vxor.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x04,0x4a,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 4a 2e + +vxor.vx v8, v4, a0, v0.t +# CHECK-INST: vxor.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x44,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 2c + +vxor.vx v8, v4, a0 +# CHECK-INST: vxor.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x44,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 44 45 2e + +vxor.vi v8, v4, 15, v0.t +# CHECK-INST: vxor.vi v8, v4, 15, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x47,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 2c + +vxor.vi v8, v4, 15 +# CHECK-INST: vxor.vi v8, v4, 15 +# CHECK-ENCODING: [0x57,0xb4,0x47,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 47 2e + +vnot.v v8, v4, v0.t +# CHECK-INST: vnot.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 2c + +vnot.v v8, v4 +# CHECK-INST: vxor.vi v8, v4, -1 +# CHECK-ENCODING: [0x57,0xb4,0x4f,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 b4 4f 2e