Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -14,6 +14,7 @@
 #include "Utils/RISCVBaseInfo.h"
 #include "Utils/RISCVMatInt.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/Register.h"
@@ -112,6 +113,9 @@
   // 'add' is an overloaded mnemonic.
   bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands);
 
+  // Check instruction constraints.
+  bool validateInstruction(MCInst &Inst, OperandVector &Operands);
+
   /// Helper for processing MC instructions that have been successfully matched
   /// by MatchAndEmitInstruction. Modifications to the emitted instructions,
   /// like the expansion of pseudo instructions (e.g., "li"), can be performed
@@ -133,6 +137,8 @@
   OperandMatchResultTy parseBareSymbol(OperandVector &Operands);
   OperandMatchResultTy parseCallSymbol(OperandVector &Operands);
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
+  OperandMatchResultTy parseVTypeIAsmOperand(OperandVector &Operands);
+  OperandMatchResultTy parseMaskRegister(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
@@ -168,6 +174,9 @@
 
     return false;
   }
+
+  std::unique_ptr<RISCVOperand> defaultRVVMaskRegOp() const;
+
 public:
   enum RISCVMatchResultTy {
     Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
@@ -199,7 +208,8 @@
     Token,
     Register,
     Immediate,
-    SystemRegister
+    SystemRegister,
+    VType,
   } Kind;
 
   bool IsRV64;
@@ -220,12 +230,32 @@
     // e.g.: read/write or user/supervisor/machine privileges.
   };
 
+  enum class VSEW {
+    SEW_8 = 0,
+    SEW_16,
+    SEW_32,
+    SEW_64,
+    SEW_128,
+    SEW_256,
+    SEW_512,
+    SEW_1024,
+  };
+
+  enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 };
+
+  struct VTypeOp {
+    VSEW sew;
+    VLMUL lmul;
+    unsigned Encoding;
+  };
+
   SMLoc StartLoc, EndLoc;
   union {
     StringRef Tok;
     RegOp Reg;
     ImmOp Imm;
     struct SysRegOp SysReg;
+    struct VTypeOp VType;
   };
 
   RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
@@ -249,14 +279,21 @@
     case KindTy::SystemRegister:
       SysReg = o.SysReg;
       break;
+    case KindTy::VType:
+      VType = o.VType;
+      break;
     }
   }
 
   bool isToken() const override { return Kind == KindTy::Token; }
   bool isReg() const override { return Kind == KindTy::Register; }
+  bool isV0Reg() const {
+    return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
+  }
   bool isImm() const override { return Kind == KindTy::Immediate; }
   bool isMem() const override { return false; }
   bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
+  bool isVType() const { return Kind == KindTy::VType; }
 
   static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
                                   RISCVMCExpr::VariantKind &VK) {
@@ -325,6 +362,8 @@
 
   bool isCSRSystemRegister() const { return isSystemRegister(); }
 
+  bool isVTypeI() const { return isVType(); }
+
   /// Return true if the operand is a valid for the fence instruction e.g.
   /// ('iorw').
   bool isFenceArg() const {
@@ -421,6 +460,15 @@
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm5() const {
+    if (!isImm())
+      return false;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isSImm6() const {
     if (!isImm())
       return false;
@@ -613,6 +661,51 @@
     return Tok;
   }
 
+  static StringRef getSEWStr(VSEW sew) {
+    switch (sew) {
+    case VSEW::SEW_8:
+      return "e8";
+    case VSEW::SEW_16:
+      return "e16";
+    case VSEW::SEW_32:
+      return "e32";
+    case VSEW::SEW_64:
+      return "e64";
+    case VSEW::SEW_128:
+      return "e128";
+    case VSEW::SEW_256:
+      return "e256";
+    case VSEW::SEW_512:
+      return "e512";
+    case VSEW::SEW_1024:
+      return "e1024";
+    }
+    llvm_unreachable("SEW must be [8|16|32|64|128|256|512|1024]");
+  }
+
+  static StringRef getLMULStr(VLMUL lmul) {
+    switch (lmul) {
+    case VLMUL::LMUL_1:
+      return "m1";
+    case VLMUL::LMUL_2:
+      return "m2";
+    case VLMUL::LMUL_4:
+      return "m4";
+    case VLMUL::LMUL_8:
+      return "m8";
+    }
+    llvm_unreachable("LMUL must be [1|2|4|8]");
+  }
+
+  StringRef getVType(SmallVectorImpl<char> &Out) const {
+    assert(Kind == KindTy::VType && "Invalid access!");
+    Twine vtype(getSEWStr(VType.sew));
+    vtype.concat(Twine(","));
+    vtype.concat(Twine(getLMULStr(VType.lmul)));
+
+    return vtype.toStringRef(Out);
+  }
+
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case KindTy::Immediate:
@@ -628,6 +721,10 @@
     case KindTy::SystemRegister:
       OS << "<sysreg: " << getSysReg() << '>';
       break;
+    case KindTy::VType:
+      SmallVector<char, 8> VTypeBuf;
+      OS << "<vtype: " << getVType(VTypeBuf) << '>';
+      break;
     }
   }
 
@@ -672,6 +769,18 @@
     return Op;
   }
 
+  static std::unique_ptr<RISCVOperand> createVType(APInt sew, APInt lmul,
+                                                   SMLoc S, bool IsRV64) {
+    auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
+    sew.ashrInPlace(3);
+    Op->VType.sew = static_cast<VSEW>(sew.logBase2());
+    Op->VType.lmul = static_cast<VLMUL>(lmul.logBase2());
+    Op->VType.Encoding = (sew.logBase2() << 2) | lmul.logBase2();
+    Op->StartLoc = S;
+    Op->IsRV64 = IsRV64;
+    return Op;
+  }
+
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     assert(Expr && "Expr shouldn't be null!");
     int64_t Imm = 0;
@@ -719,6 +828,11 @@
     Inst.addOperand(MCOperand::createImm(SysReg.Encoding));
   }
 
+  void addVTypeIOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createImm(VType.Encoding));
+  }
+
   // Returns the rounding mode represented by this RISCVOperand. Should only
   // be called after checking isFRMArg.
   RISCVFPRndMode::RoundingMode getRoundingMode() const {
@@ -788,6 +902,8 @@
   default:
     break;
   case Match_Success:
+    if (validateInstruction(Inst, Operands))
+      return true;
     return processInstruction(Inst, IDLoc, Operands, Out);
   case Match_MissingFeature:
     return Error(IDLoc, "instruction use requires an option to be enabled");
@@ -937,6 +1053,11 @@
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
   }
+  case Match_InvalidVTypeIAsmOperand: {
+    SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+    return Error(ErrorLoc,
+                 "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]");
+  }
   }
 
   llvm_unreachable("Unknown match type detected!");
@@ -1258,6 +1379,73 @@
 }
 
 OperandMatchResultTy
+RISCVAsmParser::parseVTypeIAsmOperand(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  if (getLexer().getKind() != AsmToken::Identifier)
+    return MatchOperand_NoMatch;
+
+  // Parse "e8,m1"
+  StringRef Name = getLexer().getTok().getIdentifier();
+  if (!Name.consume_front("e"))
+    return MatchOperand_NoMatch;
+  APInt sew(16, Name, 10);
+  if (sew != 8 && sew != 16 && sew != 32 && sew != 64 && sew != 128 &&
+      sew != 256 && sew != 512 && sew != 1024)
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
+  if (getLexer().getKind() == AsmToken::EndOfStatement) {
+    Operands.push_back(RISCVOperand::createVType(sew, APInt(16, 1), S, isRV64()));
+
+    return MatchOperand_Success;
+  }
+
+  if (!getLexer().is(AsmToken::Comma))
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
+  Name = getLexer().getTok().getIdentifier();
+  if (!Name.consume_front("m"))
+    return MatchOperand_NoMatch;
+  APInt lmul(16, Name, 10);
+  if (lmul != 1 && lmul != 2 && lmul != 4 && lmul != 8)
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
+  if (getLexer().getKind() != AsmToken::EndOfStatement)
+    return MatchOperand_NoMatch;
+
+  Operands.push_back(RISCVOperand::createVType(sew, lmul, S, isRV64()));
+
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy
+RISCVAsmParser::parseMaskRegister(OperandVector &Operands) {
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::Identifier:
+    StringRef Name = getLexer().getTok().getIdentifier();
+    if (!Name.consume_back(".t"))
+      return MatchOperand_NoMatch;
+    Register RegNo;
+    matchRegisterNameHelper(isRV32E(), RegNo, Name);
+
+    if (RegNo == RISCV::NoRegister)
+      return MatchOperand_NoMatch;
+    if (RegNo != RISCV::V0)
+      return MatchOperand_NoMatch;
+    SMLoc S = getLoc();
+    SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+    getLexer().Lex();
+    Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64()));
+  }
+
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy
 RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
   if (getLexer().isNot(AsmToken::LParen)) {
     Error(getLoc(), "expected '('");
@@ -1741,6 +1929,133 @@
   return false;
 }
 
+std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultRVVMaskRegOp() const {
+  return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(),
+                                 llvm::SMLoc(), isRV64());
+}
+
+bool RISCVAsmParser::validateInstruction(MCInst &Inst,
+                                         OperandVector &Operands) {
+  SMLoc Loc = Operands[1]->getStartLoc();
+  const unsigned Opcode = Inst.getOpcode();
+  switch (Opcode) {
+  case RISCV::VWADDU_VV:
+  case RISCV::VWADDU_VX:
+  case RISCV::VWSUBU_VV:
+  case RISCV::VWSUBU_VX:
+  case RISCV::VWADD_VV:
+  case RISCV::VWADD_VX:
+  case RISCV::VWSUB_VV:
+  case RISCV::VWSUB_VX:
+  case RISCV::VWMUL_VV:
+  case RISCV::VWMUL_VX:
+  case RISCV::VWMULU_VV:
+  case RISCV::VWMULU_VX:
+  case RISCV::VWMULSU_VV:
+  case RISCV::VWMULSU_VX:
+  case RISCV::VWMACCU_VV:
+  case RISCV::VWMACCU_VX:
+  case RISCV::VWMACC_VV:
+  case RISCV::VWMACC_VX:
+  case RISCV::VWMACCSU_VV:
+  case RISCV::VWMACCSU_VX:
+  case RISCV::VWMACCUS_VX:
+  case RISCV::VWSMACCU_VV:
+  case RISCV::VWSMACCU_VX:
+  case RISCV::VWSMACC_VV:
+  case RISCV::VWSMACC_VX:
+  case RISCV::VWSMACCSU_VV:
+  case RISCV::VWSMACCSU_VX:
+  case RISCV::VWSMACCUS_VX:
+  case RISCV::VFWADD_VV:
+  case RISCV::VFWADD_VF:
+  case RISCV::VFWSUB_VV:
+  case RISCV::VFWSUB_VF:
+  case RISCV::VFWMUL_VV:
+  case RISCV::VFWMUL_VF:
+  case RISCV::VFWMACC_VV:
+  case RISCV::VFWMACC_VF:
+  case RISCV::VFWNMACC_VV:
+  case RISCV::VFWNMACC_VF:
+  case RISCV::VFWMSAC_VV:
+  case RISCV::VFWMSAC_VF:
+  case RISCV::VFWNMSAC_VV:
+  case RISCV::VFWNMSAC_VF:
+  case RISCV::VSLIDEUP_VX:
+  case RISCV::VSLIDEUP_VI:
+  case RISCV::VSLIDE1UP_VX:
+  case RISCV::VRGATHER_VV:
+  case RISCV::VRGATHER_VX:
+  case RISCV::VRGATHER_VI:
+  case RISCV::VCOMPRESS_VM: {
+    unsigned DestReg = Inst.getOperand(0).getReg();
+    if (Inst.getNumOperands() == 4) {
+      unsigned MaskReg = Inst.getOperand(3).getReg();
+
+      if (DestReg == MaskReg)
+        return Error(Loc, "The destination vector register group cannot overlap"
+                          " the mask register.");
+    }
+    if (Inst.getOperand(2).isReg()) {
+      unsigned Src1Reg = Inst.getOperand(2).getReg();
+      if (DestReg == Src1Reg)
+        return Error(Loc, "The destination vector register group cannot overlap"
+                          " the source vector register group.");
+    }
+    unsigned Src2Reg = Inst.getOperand(1).getReg();
+    if (DestReg == Src2Reg)
+      return Error(Loc, "The destination vector register group cannot overlap"
+                        " the source vector register group.");
+    break;
+  }
+  case RISCV::VFWCVT_XU_F_V:
+  case RISCV::VFWCVT_X_F_V:
+  case RISCV::VFWCVT_F_XU_V:
+  case RISCV::VFWCVT_F_X_V:
+  case RISCV::VFWCVT_F_F_V:
+  case RISCV::VIOTA_M: {
+    if (Inst.getNumOperands() == 3) {
+      unsigned DestReg = Inst.getOperand(0).getReg();
+      unsigned MaskReg = Inst.getOperand(2).getReg();
+
+      if (DestReg == MaskReg)
+        return Error(Loc, "The destination vector register group cannot overlap"
+                          " the mask register.");
+    }
+    LLVM_FALLTHROUGH;
+  }
+  case RISCV::VNSRL_WV:
+  case RISCV::VNSRL_WX:
+  case RISCV::VNSRL_WI:
+  case RISCV::VNSRA_WV:
+  case RISCV::VNSRA_WX:
+  case RISCV::VNSRA_WI:
+  case RISCV::VNCLIPU_WV:
+  case RISCV::VNCLIPU_WX:
+  case RISCV::VNCLIPU_WI:
+  case RISCV::VNCLIP_WV:
+  case RISCV::VNCLIP_WX:
+  case RISCV::VNCLIP_WI:
+  case RISCV::VFNCVT_XU_F_W:
+  case RISCV::VFNCVT_X_F_W:
+  case RISCV::VFNCVT_F_XU_W:
+  case RISCV::VFNCVT_F_X_W:
+  case RISCV::VFNCVT_F_F_W:
+  case RISCV::VFNCVT_ROD_F_F_W: {
+    unsigned DestReg = Inst.getOperand(0).getReg();
+    unsigned Src2Reg = Inst.getOperand(1).getReg();
+
+    if (DestReg == Src2Reg)
+      return Error(Loc, "The destination vector register group cannot overlap"
+                        " the source vector register group.");
+    break;
+  }
+  default:
+    return false;
+  }
+  return false;
+}
+
 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                         OperandVector &Operands,
                                         MCStreamer &Out) {
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -18,6 +18,7 @@
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Endian.h"
@@ -31,10 +32,12 @@
 
 namespace {
 class RISCVDisassembler : public MCDisassembler {
+  std::unique_ptr<MCInstrInfo const> const MCII;
 
 public:
-  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
-      : MCDisassembler(STI, Ctx) {}
+  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+                    MCInstrInfo const *MCII)
+      : MCDisassembler(STI, Ctx), MCII(MCII) {}
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -46,7 +49,7 @@
 static MCDisassembler *createRISCVDisassembler(const Target &T,
                                                const MCSubtargetInfo &STI,
                                                MCContext &Ctx) {
-  return new RISCVDisassembler(STI, Ctx);
+  return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
 }
 
 extern "C" void LLVMInitializeRISCVDisassembler() {
@@ -149,6 +152,33 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  if (RegNo >= 32)
+    return MCDisassembler::Fail;
+
+  Register Reg = RISCV::V0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeVRMaskOp(MCInst &Inst, uint64_t RegNo,
+                                   uint64_t Address, const void *Decoder) {
+  Register Reg = RISCV::NoRegister;
+  switch (RegNo) {
+  default:
+    return MCDisassembler::Fail;
+  case 0:
+    Reg = RISCV::V0;
+    break;
+  case 1:
+    break;
+  }
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 // Add implied SP operand for instructions *SP compressed instructions. The SP
 // operand isn't explicitly encoded in the instruction.
 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -41,6 +41,10 @@
                    raw_ostream &O);
   void printAtomicMemOp(const MCInst *MI, unsigned OpNo,
                         const MCSubtargetInfo &STI, raw_ostream &O);
+  void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
+  void printVRMaskOp(const MCInst *MI, unsigned OpNo,
+                     const MCSubtargetInfo &STI, raw_ostream &O);
 
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -149,6 +149,30 @@
   return;
 }
 
+void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
+  unsigned Imm = MI->getOperand(OpNo).getImm();
+  unsigned sew = (Imm >> 2) & 0x7;
+  unsigned lmul = Imm & 0x3;
+
+  lmul = 0x1 << lmul;
+  sew = 0x1 << (sew + 3);
+  O << "e" << sew << ",m" << lmul;
+}
+
+void RISCVInstPrinter::printVRMaskOp(const MCInst *MI, unsigned OpNo,
+                                     const MCSubtargetInfo &STI,
+                                     raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNo);
+
+  assert(MO.isReg() && "printVRMaskOp can only print register operands");
+  if (MO.getReg() == RISCV::NoRegister)
+    return;
+  O << ", ";
+  printRegName(O, MO.getReg());
+  O << ".t";
+}
+
 const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
   return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
                                              : RISCV::ABIRegAltName);
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -80,6 +80,10 @@
   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const;
+
+  unsigned getVRMaskOp(const MCInst &MI, unsigned OpNo,
+                       SmallVectorImpl<MCFixup> &Fixups,
+                       const MCSubtargetInfo &STI) const;
 };
 } // end anonymous namespace
 
@@ -368,4 +372,20 @@
   return 0;
 }
 
+unsigned RISCVMCCodeEmitter::getVRMaskOp(const MCInst &MI, unsigned OpNo,
+                                         SmallVectorImpl<MCFixup> &Fixups,
+                                         const MCSubtargetInfo &STI) const {
+  MCOperand MO = MI.getOperand(OpNo);
+  assert(MO.isReg() && "Expected a register.");
+
+  switch (MO.getReg()) {
+  default:
+    llvm_unreachable("Invalid mask register.");
+  case RISCV::V0:
+    return 0;
+  case RISCV::NoRegister:
+    return 1;
+  }
+}
+
 #include "RISCVGenMCCodeEmitter.inc"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -49,6 +49,12 @@
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                             AssemblerPredicate<"FeatureRVCHints">;
 
+def FeatureStdExtV
+    : SubtargetFeature<"v", "HasStdExtV", "true",
+                       "'V' (Vector Instructions)">;
+def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
+                           AssemblerPredicate<"FeatureStdExtV">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -71,6 +71,7 @@
 def OPC_NMSUB     : RISCVOpcode<0b1001011>;
 def OPC_NMADD     : RISCVOpcode<0b1001111>;
 def OPC_OP_FP     : RISCVOpcode<0b1010011>;
+def OPC_OP_V      : RISCVOpcode<0b1010111>;
 def OPC_BRANCH    : RISCVOpcode<0b1100011>;
 def OPC_JALR      : RISCVOpcode<0b1100111>;
 def OPC_JAL       : RISCVOpcode<0b1101111>;
Index: llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -0,0 +1,272 @@
+//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file describes the RISC-V V extension instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class RISCVVFormat<bits<3> val> {
+  bits<3> Value = val;
+}
+def OPIVV : RISCVVFormat<0b000>;
+def OPFVV : RISCVVFormat<0b001>;
+def OPMVV : RISCVVFormat<0b010>;
+def OPIVI : RISCVVFormat<0b011>;
+def OPIVX : RISCVVFormat<0b100>;
+def OPFVF : RISCVVFormat<0b101>;
+def OPMVX : RISCVVFormat<0b110>;
+
+class RISCVMOP<bits<3> val> {
+  bits<3> Value = val;
+}
+def MOPLDUnitStrideU : RISCVMOP<0b000>;
+def MOPLDStridedU    : RISCVMOP<0b010>;
+def MOPLDIndexedU    : RISCVMOP<0b011>;
+def MOPLDUnitStrideS : RISCVMOP<0b100>;
+def MOPLDStridedS    : RISCVMOP<0b110>;
+def MOPLDIndexedS    : RISCVMOP<0b111>;
+
+def MOPSTUnitStride  : RISCVMOP<0b000>;
+def MOPSTStrided     : RISCVMOP<0b010>;
+def MOPSTIndexedOrder: RISCVMOP<0b011>;
+def MOPSTIndexedUnOrd: RISCVMOP<0b111>;
+
+class RISCVLSUMOP<bits<5> val> {
+  bits<5> Value = val;
+}
+def LUMOPUnitStride  : RISCVLSUMOP<0b00000>;
+def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
+def SUMOPUnitStride  : RISCVLSUMOP<0b00000>;
+
+class RISCVWidth<bits<3> val> {
+  bits<3> Value = val;
+}
+def LSWidthVByte : RISCVWidth<0b000>;
+def LSWidthVHalf : RISCVWidth<0b101>;
+def LSWidthVWord : RISCVWidth<0b110>;
+def LSWidthVSEW  : RISCVWidth<0b111>;
+
+class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+  bits<5> rs1;
+  bits<5> rd;
+  bits<11> vtypei;
+
+  let Inst{31} = 0;
+  let Inst{30-20} = vtypei;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b111;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31} = 1;
+  let Inst{30-25} = 0b000000;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b111;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+               string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> vs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
+                string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> imm;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = imm;
+  let Inst{14-12} = 0b011;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-26} = funct6;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+  let Inst{14-12} = opv.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+}
+
+class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
+                RISCVWidth width, dag outs, dag ins, string opcodestr,
+                string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = lumop.Value;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_LOAD_FP.Value;
+}
+
+class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_LOAD_FP.Value;
+}
+
+class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_LOAD_FP.Value;
+}
+
+class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
+                RISCVWidth width, dag outs, dag ins, string opcodestr,
+                string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> vs3;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = sumop.Value;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vs3;
+  let Opcode = OPC_STORE_FP.Value;
+}
+
+class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> vs3;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vs3;
+  let Opcode = OPC_STORE_FP.Value;
+}
+
+class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bits<5> vs3;
+  bit vm;
+
+  let Inst{31-29} = nf;
+  let Inst{28-26} = mop.Value;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width.Value;
+  let Inst{11-7} = vs3;
+  let Opcode = OPC_STORE_FP.Value;
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1116,3 +1116,4 @@
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
+include "RISCVInstrInfoV.td"
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -0,0 +1,720 @@
+//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'V',
+// Vector instruction set extension.
+//
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrFormatsV.td"
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def VTypeIAsmOperand : AsmOperandClass {
+  let Name = "VTypeI";
+  let ParserMethod = "parseVTypeIAsmOperand";
+  let DiagnosticType = "InvalidVTypeIAsmOperand";
+}
+
+def VTypeIOp : Operand<XLenVT> {
+  let ParserMatchClass = VTypeIAsmOperand;
+  let PrintMethod = "printVTypeI";
+  let DecoderMethod = "decodeUImmOperand<11>";
+}
+
+def VRAsmOperand : AsmOperandClass {
+  let Name = "RVVRegOpOperand";
+  let RenderMethod = "addRegOperands";
+  let PredicateMethod = "isReg";
+  let ParserMethod = "parseRegister";
+}
+
+def VRRegOp: RegisterOperand<VR> {
+  let ParserMatchClass = VRAsmOperand;
+  let PrintMethod = "printOperand";
+}
+
+def VRMaskAsmOperand : AsmOperandClass {
+  let Name = "RVVMaskRegOpOperand";
+  let RenderMethod = "addRegOperands";
+  let PredicateMethod = "isV0Reg";
+  let ParserMethod = "parseMaskRegister";
+  let IsOptional = 1;
+  let DefaultMethod = "defaultRVVMaskRegOp";
+}
+
+def VRMaskRegOp: RegisterOperand<VRV0> {
+  let ParserMatchClass = VRMaskAsmOperand;
+  let PrintMethod = "printVRMaskOp";
+  let EncoderMethod = "getVRMaskOp";
+  let DecoderMethod = "decodeVRMaskOp";
+}
+
+def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
+  let ParserMatchClass = SImmAsmOperand<5>;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeSImmOperand<5>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (MCOp.evaluateAsConstantImm(Imm))
+      return isInt<5>(Imm);
+    return MCOp.isBareSymbolRef();
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+// load vd, (rs1), vm
+class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
+                        string opcodestr>
+    : RVInstVLU<0b000, mop, lumop, width, (outs VRRegOp:$vd),
+                (ins GPR:$rs1, VRMaskRegOp:$vm), opcodestr, "$vd, (${rs1})${vm}">;
+
+// load vd, (rs1), rs2, vm
+class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVLS<0b000, mop, width, (outs VRRegOp:$vd),
+                (ins GPR:$rs1, GPR:$rs2, VRMaskRegOp:$vm), opcodestr,
+                "$vd, (${rs1}), $rs2${vm}">;
+
+// load vd, (rs1), vs2, vm
+class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVLX<0b000, mop, width, (outs VRRegOp:$vd),
+                (ins GPR:$rs1, VRRegOp:$vs2, VRMaskRegOp:$vm), opcodestr,
+                "$vd, (${rs1}), $vs2${vm}">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+// store vd, vs3, (rs1), vm
+class VUnitStrideStore<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
+                         string opcodestr>
+    : RVInstVSU<0b000, mop, sumop, width, (outs),
+                (ins VRRegOp:$vs3, GPR:$rs1, VRMaskRegOp:$vm), opcodestr,
+                "$vs3, (${rs1})${vm}">;
+
+// store vd, vs3, (rs1), rs2, vm
+class VStridedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVSS<0b000, mop, width, (outs),
+                (ins VRRegOp:$vs3, GPR:$rs1, GPR:$rs2, VRMaskRegOp:$vm),
+                opcodestr, "$vs3, (${rs1}), $rs2${vm}">;
+
+// store vd, vs3, (rs1), vs2, vm
+class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVSX<0b000, mop, width, (outs),
+                (ins VRRegOp:$vs3, GPR:$rs1, VRRegOp:$vs2, VRMaskRegOp:$vm),
+                opcodestr, "$vs3, (${rs1}), $vs2${vm}">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs2, vs1, vm
+class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVV<funct6, opv, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, VRRegOp:$vs1, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $vs2, $vs1${vm}">;
+
+// op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
+class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVV<funct6, opv, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, VRRegOp:$vs1, VRV0:$v0),
+                opcodestr, "$vd, $vs2, $vs1, v0"> {
+  let vm = 0;
+}
+
+// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
+class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVV<funct6, opv, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs1, VRRegOp:$vs2, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $vs1, $vs2${vm}">;
+
+// op vd, vs1, vs2
+class VALUMask<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVV<funct6, opv, (outs VRRegOp:$vd),
+               (ins VRRegOp:$vs2, VRRegOp:$vs1),
+               opcodestr, "$vd, $vs2, $vs1">;
+
+// op vd, vs2, rs1, vm
+class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVX<funct6, opv, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, GPR:$rs1, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $vs2, $rs1${vm}">;
+
+// op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
+class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVX<funct6, opv, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, GPR:$rs1, VRV0:$v0),
+                opcodestr, "$vd, $vs2, $rs1, v0"> {
+  let vm = 0;
+}
+
+// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
+class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVX<funct6, opv, (outs VRRegOp:$vd),
+                (ins GPR:$rs1, VRRegOp:$vs2, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $rs1, $vs2${vm}">;
+
+// op vd, vs2, imm, vm
+class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+    : RVInstIVI<funct6, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, optype:$imm, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $vs2, $imm${vm}">;
+
+// op vd, vs2, imm, v0 (without mask, use v0 as carry input)
+class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+    : RVInstIVI<funct6, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, optype:$imm, VRV0:$v0),
+                opcodestr, "$vd, $vs2, $imm, v0"> {
+  let vm = 0;
+}
+
+// op vd, vs2, rs1, vm (Float)
+class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVX<funct6, opv, (outs VRRegOp:$vd),
+                (ins VRRegOp:$vs2, FPR32:$rs1, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $vs2, $rs1${vm}">;
+
+// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
+class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : RVInstVX<funct6, opv, (outs VRRegOp:$vd),
+                (ins FPR32:$rs1, VRRegOp:$vs2, VRMaskRegOp:$vm),
+                opcodestr, "$vd, $rs1, $vs2${vm}">;
+
+// op vd, vs2, vm (use vs1 as instruction encoding)
+class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+    : RVInstV<funct6, vs1, opv, (outs VRRegOp:$vd),
+               (ins VRRegOp:$vs2, VRMaskRegOp:$vm),
+               opcodestr, "$vd, $vs2${vm}">;
+}
+
+//===----------------------------------------------------------------------===//
+// Combination of instruction classes.
+// Use these multiclasses to define instructions more easily.
+//===----------------------------------------------------------------------===//
+multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
+  def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
+  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+  def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;
+}
+
+multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
+  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALUr_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V : VALUrVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
+  def X : VALUrVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
+  def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+  def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;
+}
+
+multiclass VALU_IV_V<string opcodestr, bits<6> funct6> {
+  def _VS  : VALUVV<funct6, OPIVV, opcodestr # ".vs">;
+}
+
+multiclass VALUr_IV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def X : VALUrVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">;
+  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_MV_V<string opcodestr, bits<6> funct6> {
+  def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">;
+}
+
+multiclass VALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
+  def M : VALUMask<funct6, OPMVV, opcodestr # "." # vm # "m">;
+}
+
+multiclass VALU_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALUr_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">;
+  def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALUr_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
+  def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>;
+}
+
+multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> {
+  def _VVM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">;
+  def _VXM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">;
+  def _VIM : VALUmVI<funct6, opcodestr # ".vim">;
+}
+
+multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
+  def _VVM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">;
+  def _VXM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">;
+}
+
+multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
+  def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+}
+
+multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+}
+
+multiclass VALUr_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
+  def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+}
+
+multiclass VALU_FV_V<string opcodestr, bits<6> funct6> {
+  def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">;
+}
+
+multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
+  def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtV] in {
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei),
+                           "vsetvli", "$rd, $rs1, $vtypei">;
+def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                         "vsetvl", "$rd, $rs1, $rs2">;
+}
+
+// Vector Unit-Stride Instructions
+def VLB_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVByte, "vlb.v">;
+def VLH_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVHalf, "vlh.v">;
+def VLW_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVWord, "vlw.v">;
+
+def VLBU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVByte, "vlbu.v">;
+def VLHU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVHalf, "vlhu.v">;
+def VLWU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVWord, "vlwu.v">;
+
+def VLE_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVSEW, "vle.v">;
+
+def VLBFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVByte, "vlbff.v">;
+def VLHFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVHalf, "vlhff.v">;
+def VLWFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVWord, "vlwff.v">;
+
+def VLBUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVByte, "vlbuff.v">;
+def VLHUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVHalf, "vlhuff.v">;
+def VLWUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVWord, "vlwuff.v">;
+
+def VLEFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVSEW, "vleff.v">;
+
+def VSB_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVByte, "vsb.v">;
+def VSH_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVHalf, "vsh.v">;
+def VSW_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVWord, "vsw.v">;
+
+def VSE_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVSEW, "vse.v">;
+
+// Vector Strided Instructions
+def VLSB_V : VStridedLoad<MOPLDStridedS, LSWidthVByte, "vlsb.v">;
+def VLSH_V : VStridedLoad<MOPLDStridedS, LSWidthVHalf, "vlsh.v">;
+def VLSW_V : VStridedLoad<MOPLDStridedS, LSWidthVWord, "vlsw.v">;
+
+def VLSBU_V : VStridedLoad<MOPLDStridedU, LSWidthVByte, "vlsbu.v">;
+def VLSHU_V : VStridedLoad<MOPLDStridedU, LSWidthVHalf, "vlshu.v">;
+def VLSWU_V : VStridedLoad<MOPLDStridedU, LSWidthVWord, "vlswu.v">;
+
+def VLSE_V : VStridedLoad<MOPLDStridedU, LSWidthVSEW, "vlse.v">;
+
+def VSSB_V : VStridedStore<MOPSTStrided, LSWidthVByte, "vssb.v">;
+def VSSH_V : VStridedStore<MOPSTStrided, LSWidthVHalf, "vssh.v">;
+def VSSW_V : VStridedStore<MOPSTStrided, LSWidthVWord, "vssw.v">;
+def VSSE_V : VStridedStore<MOPSTStrided, LSWidthVSEW, "vsse.v">;
+
+// Vector Indexed Instructions
+def VLXB_V : VIndexedLoad<MOPLDIndexedS, LSWidthVByte, "vlxb.v">;
+def VLXH_V : VIndexedLoad<MOPLDIndexedS, LSWidthVHalf, "vlxh.v">;
+def VLXW_V : VIndexedLoad<MOPLDIndexedS, LSWidthVWord, "vlxw.v">;
+
+def VLXBU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVByte, "vlxbu.v">;
+def VLXHU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVHalf, "vlxhu.v">;
+def VLXWU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVWord, "vlxwu.v">;
+
+def VLXE_V : VIndexedLoad<MOPLDIndexedU, LSWidthVSEW, "vlxe.v">;
+
+def VSXB_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVByte, "vsxb.v">;
+def VSXH_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVHalf, "vsxh.v">;
+def VSXW_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVWord, "vsxw.v">;
+def VSXE_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVSEW, "vsxe.v">;
+
+def VSUXB_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVByte, "vsuxb.v">;
+def VSUXH_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVHalf, "vsuxh.v">;
+def VSUXW_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVWord, "vsuxw.v">;
+def VSUXE_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVSEW, "vsuxe.v">;
+
+// Vector Single-Width Integer Add and Subtract
+defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
+defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
+defm VRSUB_V: VALU_IV_X_I<"vrsub", 0b000011>;
+
+// Vector Widening Integer Add/Subtract
+let Constraints = "@earlyclobber $vd" in {
+defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>;
+defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>;
+defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>;
+defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>;
+}
+defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">;
+defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">;
+defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
+defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
+
+// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+// TODO: Fix it.
+defm VADC : VALUm_IV_V_X_I<"vadc", 0b010000>;
+defm VMADC : VALUm_IV_V_X_I<"vmadc", 0b010001>;
+defm VSBC : VALUm_IV_V_X<"vsbc", 0b010010>;
+defm VMSBC : VALUm_IV_V_X<"vmsbc", 0b010011>;
+
+// Vector Bitwise Logical Instructions
+defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
+defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
+defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
+
+// Vector Single-Width Bit Shift Instructions
+defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>;
+defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>;
+defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>;
+
+// Vector Narrowing Integer Right Shift Instructions
+defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
+defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
+
+// Vector Integer Comparison Instructions
+defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>;
+defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>;
+defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>;
+defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>;
+defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>;
+defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>;
+defm VMSGTU_V : VALU_IV_X_I<"vmsgtu", 0b011110>;
+defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>;
+
+// Vector Integer Min/Max Instructions
+defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>;
+defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>;
+defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>;
+defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>;
+
+// Vector Single-Width Integer Multiply Instructions
+defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>;
+defm VMULH_V: VALU_MV_V_X<"vmulh", 0b100111>;
+defm VMULHU_V : VALU_MV_V_X<"vmulhu", 0b100100>;
+defm VMULHSU_V : VALU_MV_V_X<"vmulhsu", 0b100110>;
+
+// Vector Integer Divide Instructions
+defm VDIVU_V : VALU_MV_V_X<"vdivu", 0b100000>;
+defm VDIV_V : VALU_MV_V_X<"vdiv", 0b100001>;
+defm VREMU_V : VALU_MV_V_X<"vremu", 0b100010>;
+defm VREM_V : VALU_MV_V_X<"vrem", 0b100011>;
+
+// Vector Widening Integer Multiply Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011>;
+defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000>;
+defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010>;
+}
+
+// Vector Single-Width Integer Multiply-Add Instructions
+defm VMACC_V : VALUr_MV_V_X<"vmacc", 0b101101>;
+defm VNMSAC_V : VALUr_MV_V_X<"vnmsac", 0b101111>;
+defm VMADD_V : VALUr_MV_V_X<"vmadd", 0b101001>;
+defm VNMSUB_V : VALUr_MV_V_X<"vnmsub", 0b101011>;
+
+// Vector Widening Integer Multiply-Add Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100>;
+defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101>;
+defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111>;
+defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>;
+}
+
+// Vector Integer Merge Instructions
+defm VMERGE : VALUm_IV_V_X_I<"vmerge", 0b010111>;
+
+// Vector Integer Move Instructions
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs1
+def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VRRegOp:$vd),
+                       (ins VRRegOp:$vs1), "vmv.v.v", "$vd, $vs1"> {
+  let vs2 = 0;
+  let vm = 1;
+}
+// op vd, rs1
+def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VRRegOp:$vd),
+                       (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1"> {
+  let vs2 = 0;
+  let vm = 1;
+}
+// op vd, imm
+def VMV_V_I : RVInstIVI<0b010111, (outs VRRegOp:$vd),
+                       (ins simm5:$imm), "vmv.v.i", "$vd, $imm"> {
+  let vs2 = 0;
+  let vm = 1;
+}
+}
+
+// Vector Fixed-Point Arithmetic Instructions
+defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>;
+defm VSADD_V : VALU_IV_V_X_I<"vsadd", 0b100001>;
+defm VSSUBU_V : VALU_IV_V_X<"vssubu", 0b100010>;
+defm VSSUB_V : VALU_IV_V_X<"vssub", 0b100011>;
+
+// Vector Single-Width Averaging Add and Subtract
+defm VAADD_V : VALU_IV_V_X_I<"vaadd", 0b100100>;
+defm VASUB_V : VALU_IV_V_X<"vasub", 0b100110>;
+
+// Vector Single-Width Fractional Multiply with Rounding and Saturation
+defm VSMUL_V : VALU_IV_V_X<"vsmul", 0b100111>;
+
+// Vector Widening Saturating Scaled Multiply-Add
+let Constraints = "@earlyclobber $vd" in {
+defm VWSMACCU_V : VALUr_IV_V_X<"vwsmaccu", 0b111100>;
+defm VWSMACC_V : VALUr_IV_V_X<"vwsmacc", 0b111101>;
+defm VWSMACCSU_V : VALUr_IV_V_X<"vwsmaccsu", 0b111111>;
+defm VWSMACCUS_V : VALUr_IV_X<"vwsmaccus", 0b111110>;
+}
+
+// Vector Single-Width Scaling Shift Instructions
+defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>;
+defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>;
+
+// Vector Narrowing Fixed-Point Clip Instructions
+defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">;
+defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
+
+// Vector Single-Width Floating-Point Add/Subtract Instructions
+defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
+defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>;
+defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
+
+// Vector Widening Floating-Point Add/Subtract Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000>;
+defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010>;
+}
+
+defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, "w">;
+defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, "w">;
+
+// Vector Single-Width Floating-Point Multiply/Divide Instructions
+defm VFMUL_V : VALU_FV_V_F<"vfmul", 0b100100>;
+defm VFDIV_V : VALU_FV_V_F<"vfdiv", 0b100000>;
+defm VFRDIV_V : VALU_FV_F<"vfrdiv", 0b100001>;
+
+// Vector Widening Floating-Point Multiply
+let Constraints = "@earlyclobber $vd" in {
+defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000>;
+}
+
+// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+defm VFMACC_V: VALUr_FV_V_F<"vfmacc", 0b101100>;
+defm VFNMACC_V : VALUr_FV_V_F<"vfnmacc", 0b101101>;
+defm VFMSAC_V : VALUr_FV_V_F<"vfmsac", 0b101110>;
+defm VFNMSAC_V : VALUr_FV_V_F<"vfnmsac", 0b101111>;
+defm VFMADD_V : VALUr_FV_V_F<"vfmadd", 0b101000>;
+defm VFNMADD_V : VALUr_FV_V_F<"vfnmadd", 0b101001>;
+defm VFMSUB_V : VALUr_FV_V_F<"vfmsub", 0b101010>;
+defm VFNMSUB_V : VALUr_FV_V_F<"vfnmsub", 0b101011>;
+
+// Vector Widening Floating-Point Fused Multiply-Add Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>;
+defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>;
+defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>;
+defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
+}
+
+// Vector Floating-Point Square-Root Instruction
+defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+
+// Vector Floating-Point MIN/MAX Instructions
+defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
+defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>;
+
+// Vector Floating-Point Sign-Injection Instructions
+defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>;
+defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
+defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
+
+// Vector Floating-Point Compare Instructions
+defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
+defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>;
+defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>;
+defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>;
+defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
+defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
+
+// Vector Floating-Point Classify Instruction
+defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Vector Floating-Point Merge Instruction
+def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VRRegOp:$vd),
+                           (ins VRRegOp:$vs2, FPR32:$rs1, VRV0:$v0),
+                           "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
+  let vm = 0;
+}
+
+// Vector Floating-Point Move Instruction
+def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRRegOp:$vd),
+                       (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
+  let vs2 = 0;
+  let vm = 1;
+}
+}
+
+// Single-Width Floating-Point/Integer Type-Convert Instructions
+defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
+defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
+defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
+defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+
+// Widening Floating-Point/Integer Type-Convert Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
+defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
+defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
+defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
+defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+}
+
+// Narrowing Floating-Point/Integer Type-Convert Instructions
+defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>;
+defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>;
+defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>;
+defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>;
+defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>;
+defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>;
+
+// Vector Single-Width Integer Reduction Instructions
+defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>;
+defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>;
+defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>;
+defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>;
+defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>;
+defm VREDAND : VALU_MV_V<"vredand", 0b000001>;
+defm VREDOR : VALU_MV_V<"vredor", 0b000010>;
+defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>;
+
+// Vector Widening Integer Reduction Instructions
+defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>;
+defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>;
+
+// Vector Single-Width Floating-Point Reduction Instructions
+defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>;
+defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>;
+defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>;
+defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>;
+
+// Vector Widening Floating-Point Reduction Instructions
+defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>;
+defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>;
+
+// Vector Mask-Register Logical Instructions
+let vm = 1 in {
+defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">;
+defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">;
+defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">;
+defm VMXOR_M : VALU_MV_Mask<"vmxor", 0b011011, "m">;
+defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">;
+defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">;
+defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
+defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Vector mask population count vpopc
+def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
+                        (ins VRRegOp:$vs2, VRMaskRegOp:$vm),
+                        "vpopc.m", "$vd, $vs2${vm}">;
+
+// vfirst find-first-set mask bit
+def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
+                        (ins VRRegOp:$vs2, VRMaskRegOp:$vm),
+                        "vfirst.m", "$vd, $vs2${vm}">;
+}
+
+// vmsbf.m set-before-first mask bit
+defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>;
+
+// vmsif.m set-including-first mask bit
+defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
+
+// vmsof.m set-only-first mask bit
+defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
+
+// Vector Iota Instruction
+let Constraints = "@earlyclobber $vd" in {
+defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
+}
+
+// Vector Element Index Instruction
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VRRegOp:$vd),
+                      (ins VRMaskRegOp:$vm), "vid.v", "$vd${vm}"> {
+  let vs2 = 0;
+}
+
+// Integer Scalar Move Instructions
+let vm = 1 in {
+def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
+                      (ins VRRegOp:$vs2), "vmv.x.s", "$vd, $vs2">;
+def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VRRegOp:$vd),
+                      (ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">;
+
+// Floating-Point Scalar Move Instructions
+def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
+                      (ins VRRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
+def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRRegOp:$vd),
+                      (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
+}
+}
+
+// Vector Slide Instructions
+let Constraints = "@earlyclobber $vd" in {
+defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
+}
+defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
+
+let Constraints = "@earlyclobber $vd" in {
+defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
+}
+defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
+
+// Vector Register Gather Instruction
+let Constraints = "@earlyclobber $vd" in {
+defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>;
+}
+
+// Vector Compress Instruction
+let Constraints = "@earlyclobber $vd", vm = 1 in {
+defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
+}
+
+} // Predicates = [HasStdExtV]
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -233,3 +233,28 @@
   (sequence "F%u_D", 10, 15),
   (sequence "F%u_D", 8, 9)
 )>;
+
+// Vector registers
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = 0-31 in {
+    def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>;
+  }
+}
+
+class RegisterTypes<list<ValueType> reg_types> {
+  list<ValueType> types = reg_types;
+}
+
+def VLenVT : RegisterTypes<[nxv16i8, nxv8i16, nxv4i32, nxv2i64]>;
+
+// The order of registers represents the preferred allocation sequence,
+// meaning caller-save regs are listed before callee-save.
+def VR : RegisterClass<"RISCV", VLenVT.types,
+                        128, (add
+    (sequence "V%u", 25, 31),
+    (sequence "V%u", 8, 24),
+    (sequence "V%u", 0, 7)
+  )> {
+}
+
+def VRV0 : RegisterClass<"RISCV", VLenVT.types, 128, (add V0)>;
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -39,6 +39,7 @@
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
+  bool HasStdExtV = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -87,6 +88,7 @@
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
+  bool hasStdExtV() const { return HasStdExtV; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -44,7 +44,9 @@
   InstFormatCJ = 16,
   InstFormatOther = 17,
 
-  InstFormatMask = 31
+  InstFormatMask = 31,
+
+  InstVectorWithMask = (0x1 << 5),
 };
 
 enum {
Index: llvm/test/MC/RISCV/rvv/add.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/add.s
@@ -0,0 +1,331 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vadd.vv v1, v3, v2, v0.t
+// CHECK-INST: vadd.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 00 <unknown>
+
+vadd.vv v1, v3, v2
+// CHECK-INST: vadd.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 02 <unknown>
+
+vadd.vx v1, v3, a0, v0.t
+// CHECK-INST: vadd.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 00 <unknown>
+
+vadd.vx v1, v3, a0
+// CHECK-INST: vadd.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 02 <unknown>
+
+vadd.vi v1, v3, 15, v0.t
+// CHECK-INST: vadd.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 00 <unknown>
+
+vadd.vi v1, v3, 15
+// CHECK-INST: vadd.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 02 <unknown>
+
+vwaddu.vv v1, v3, v2, v0.t
+// CHECK-INST: vwaddu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xc0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 c0 <unknown>
+
+vwaddu.vv v1, v3, v2
+// CHECK-INST: vwaddu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xc2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 c2 <unknown>
+
+vwaddu.vx v1, v3, a0, v0.t
+// CHECK-INST: vwaddu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xc0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 c0 <unknown>
+
+vwaddu.vx v1, v3, a0
+// CHECK-INST: vwaddu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xc2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 c2 <unknown>
+
+vwadd.vv v1, v3, v2, v0.t
+// CHECK-INST: vwadd.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xc4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 c4 <unknown>
+
+vwadd.vv v1, v3, v2
+// CHECK-INST: vwadd.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xc6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 c6 <unknown>
+
+vwadd.vx v1, v3, a0, v0.t
+// CHECK-INST: vwadd.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xc4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 c4 <unknown>
+
+vwadd.vx v1, v3, a0
+// CHECK-INST: vwadd.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xc6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 c6 <unknown>
+
+vwaddu.wv v1, v3, v2, v0.t
+// CHECK-INST: vwaddu.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xd0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 d0 <unknown>
+
+vwaddu.wv v1, v3, v2
+// CHECK-INST: vwaddu.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xd2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 d2 <unknown>
+
+vwaddu.wx v1, v3, a0, v0.t
+// CHECK-INST: vwaddu.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xd0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 d0 <unknown>
+
+vwaddu.wx v1, v3, a0
+// CHECK-INST: vwaddu.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xd2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 d2 <unknown>
+
+vwadd.wv v1, v3, v2, v0.t
+// CHECK-INST: vwadd.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xd4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 d4 <unknown>
+
+vwadd.wv v1, v3, v2
+// CHECK-INST: vwadd.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xd6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 d6 <unknown>
+
+vwadd.wx v1, v3, a0, v0.t
+// CHECK-INST: vwadd.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xd4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 d4 <unknown>
+
+vwadd.wx v1, v3, a0
+// CHECK-INST: vwadd.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xd6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 d6 <unknown>
+
+vadc.vvm v1, v3, v2, v0
+// CHECK-INST: vadc.vvm v1, v3, v2, v0
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x40]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 40 <unknown>
+
+vadc.vxm v1, v3, a0, v0
+// CHECK-INST: vadc.vxm v1, v3, a0, v0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x40]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 40 <unknown>
+
+vadc.vim v1, v3, 15, v0
+// CHECK-INST: vadc.vim v1, v3, 15, v0
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x40]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 40 <unknown>
+
+vmadc.vvm v1, v3, v2, v0
+// CHECK-INST: vmadc.vvm v1, v3, v2, v0
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x44]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 44 <unknown>
+
+vmadc.vxm v1, v3, a0, v0
+// CHECK-INST: vmadc.vxm v1, v3, a0, v0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x44]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 44 <unknown>
+
+vmadc.vim v1, v3, 15, v0
+// CHECK-INST: vmadc.vim v1, v3, 15, v0
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x44]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 44 <unknown>
+
+vsaddu.vv v1, v3, v2, v0.t
+// CHECK-INST: vsaddu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 80 <unknown>
+
+vsaddu.vv v1, v3, v2
+// CHECK-INST: vsaddu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 82 <unknown>
+
+vsaddu.vx v1, v3, a0, v0.t
+// CHECK-INST: vsaddu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 80 <unknown>
+
+vsaddu.vx v1, v3, a0
+// CHECK-INST: vsaddu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 82 <unknown>
+
+vsaddu.vi v1, v3, 15, v0.t
+// CHECK-INST: vsaddu.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 80 <unknown>
+
+vsaddu.vi v1, v3, 15
+// CHECK-INST: vsaddu.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 82 <unknown>
+
+vsadd.vv v1, v3, v2, v0.t
+// CHECK-INST: vsadd.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x84]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 84 <unknown>
+
+vsadd.vv v1, v3, v2
+// CHECK-INST: vsadd.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x86]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 86 <unknown>
+
+vsadd.vx v1, v3, a0, v0.t
+// CHECK-INST: vsadd.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x84]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 84 <unknown>
+
+vsadd.vx v1, v3, a0
+// CHECK-INST: vsadd.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x86]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 86 <unknown>
+
+vsadd.vi v1, v3, 15, v0.t
+// CHECK-INST: vsadd.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x84]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 84 <unknown>
+
+vsadd.vi v1, v3, 15
+// CHECK-INST: vsadd.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x86]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 86 <unknown>
+
+vaadd.vv v1, v3, v2, v0.t
+// CHECK-INST: vaadd.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 90 <unknown>
+
+vaadd.vv v1, v3, v2
+// CHECK-INST: vaadd.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 92 <unknown>
+
+vaadd.vx v1, v3, a0, v0.t
+// CHECK-INST: vaadd.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 90 <unknown>
+
+vaadd.vx v1, v3, a0
+// CHECK-INST: vaadd.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 92 <unknown>
+
+vaadd.vi v1, v3, 15, v0.t
+// CHECK-INST: vaadd.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 90 <unknown>
+
+vaadd.vi v1, v3, 15
+// CHECK-INST: vaadd.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 92 <unknown>
+
+vfadd.vv v1, v3, v2, v0.t
+// CHECK-INST: vfadd.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 00 <unknown>
+
+vfadd.vv v1, v3, v2
+// CHECK-INST: vfadd.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 02 <unknown>
+
+vfadd.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfadd.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 00 <unknown>
+
+vfadd.vf v1, v3, fa0
+// CHECK-INST: vfadd.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 02 <unknown>
+
+vfwadd.vv v1, v3, v2, v0.t
+// CHECK-INST: vfwadd.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xc0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 c0 <unknown>
+
+vfwadd.vv v1, v3, v2
+// CHECK-INST: vfwadd.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xc2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 c2 <unknown>
+
+vfwadd.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfwadd.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xc0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 c0 <unknown>
+
+vfwadd.vf v1, v3, fa0
+// CHECK-INST: vfwadd.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xc2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 c2 <unknown>
Index: llvm/test/MC/RISCV/rvv/and.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/and.s
@@ -0,0 +1,43 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vand.vv v1, v3, v2, v0.t
+// CHECK-INST: vand.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x24]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 24 <unknown>
+
+vand.vv v1, v3, v2
+// CHECK-INST: vand.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x26]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 26 <unknown>
+
+vand.vx v1, v3, a0, v0.t
+// CHECK-INST: vand.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x24]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 24 <unknown>
+
+vand.vx v1, v3, a0
+// CHECK-INST: vand.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x26]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 26 <unknown>
+
+vand.vi v1, v3, 15, v0.t
+// CHECK-INST: vand.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x24]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 24 <unknown>
+
+vand.vi v1, v3, 15
+// CHECK-INST: vand.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x26]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 26 <unknown>
Index: llvm/test/MC/RISCV/rvv/clip.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/clip.s
@@ -0,0 +1,79 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vnclipu.wv v1, v3, v2, v0.t
+// CHECK-INST: vnclipu.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xb8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 b8 <unknown>
+
+vnclipu.wv v1, v3, v2
+// CHECK-INST: vnclipu.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xba]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 ba <unknown>
+
+vnclipu.wx v1, v3, a0, v0.t
+// CHECK-INST: vnclipu.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xb8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 b8 <unknown>
+
+vnclipu.wx v1, v3, a0
+// CHECK-INST: vnclipu.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xba]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 ba <unknown>
+
+vnclipu.wi v1, v3, 31, v0.t
+// CHECK-INST: vnclipu.wi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f b8 <unknown>
+
+vnclipu.wi v1, v3, 31
+// CHECK-INST: vnclipu.wi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xba]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f ba <unknown>
+
+vnclip.wv v1, v3, v2, v0.t
+// CHECK-INST: vnclip.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 bc <unknown>
+
+vnclip.wv v1, v3, v2
+// CHECK-INST: vnclip.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 be <unknown>
+
+vnclip.wx v1, v3, a0, v0.t
+// CHECK-INST: vnclip.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 bc <unknown>
+
+vnclip.wx v1, v3, a0
+// CHECK-INST: vnclip.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 be <unknown>
+
+vnclip.wi v1, v3, 31, v0.t
+// CHECK-INST: vnclip.wi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f bc <unknown>
+
+vnclip.wi v1, v3, 31
+// CHECK-INST: vnclip.wi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f be <unknown>
Index: llvm/test/MC/RISCV/rvv/compare.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/compare.s
@@ -0,0 +1,367 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmseq.vv v1, v3, v2, v0.t
+// CHECK-INST: vmseq.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x60]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 60 <unknown>
+
+vmseq.vv v1, v3, v2
+// CHECK-INST: vmseq.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x62]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 62 <unknown>
+
+vmseq.vx v1, v3, a0, v0.t
+// CHECK-INST: vmseq.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x60]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 60 <unknown>
+
+vmseq.vx v1, v3, a0
+// CHECK-INST: vmseq.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x62]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 62 <unknown>
+
+vmseq.vi v1, v3, 15, v0.t
+// CHECK-INST: vmseq.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x60]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 60 <unknown>
+
+vmseq.vi v1, v3, 15
+// CHECK-INST: vmseq.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x62]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 62 <unknown>
+
+vmsne.vv v1, v3, v2, v0.t
+// CHECK-INST: vmsne.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x64]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 64 <unknown>
+
+vmsne.vv v1, v3, v2
+// CHECK-INST: vmsne.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x66]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 66 <unknown>
+
+vmsne.vx v1, v3, a0, v0.t
+// CHECK-INST: vmsne.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x64]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 64 <unknown>
+
+vmsne.vx v1, v3, a0
+// CHECK-INST: vmsne.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x66]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 66 <unknown>
+
+vmsne.vi v1, v3, 15, v0.t
+// CHECK-INST: vmsne.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x64]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 64 <unknown>
+
+vmsne.vi v1, v3, 15
+// CHECK-INST: vmsne.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x66]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 66 <unknown>
+
+vmsltu.vv v1, v3, v2, v0.t
+// CHECK-INST: vmsltu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x68]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 68 <unknown>
+
+vmsltu.vv v1, v3, v2
+// CHECK-INST: vmsltu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x6a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 6a <unknown>
+
+vmsltu.vx v1, v3, a0, v0.t
+// CHECK-INST: vmsltu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x68]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 68 <unknown>
+
+vmsltu.vx v1, v3, a0
+// CHECK-INST: vmsltu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x6a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 6a <unknown>
+
+vmslt.vv v1, v3, v2, v0.t
+// CHECK-INST: vmslt.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x6c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 6c <unknown>
+
+vmslt.vv v1, v3, v2
+// CHECK-INST: vmslt.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x6e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 6e <unknown>
+
+vmslt.vx v1, v3, a0, v0.t
+// CHECK-INST: vmslt.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x6c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 6c <unknown>
+
+vmslt.vx v1, v3, a0
+// CHECK-INST: vmslt.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x6e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 6e <unknown>
+
+vmsleu.vv v1, v3, v2, v0.t
+// CHECK-INST: vmsleu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x70]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 70 <unknown>
+
+vmsleu.vv v1, v3, v2
+// CHECK-INST: vmsleu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x72]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 72 <unknown>
+
+vmsleu.vx v1, v3, a0, v0.t
+// CHECK-INST: vmsleu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x70]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 70 <unknown>
+
+vmsleu.vx v1, v3, a0
+// CHECK-INST: vmsleu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x72]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 72 <unknown>
+
+vmsleu.vi v1, v3, 15, v0.t
+// CHECK-INST: vmsleu.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x70]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 70 <unknown>
+
+vmsleu.vi v1, v3, 15
+// CHECK-INST: vmsleu.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x72]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 72 <unknown>
+
+vmsle.vv v1, v3, v2, v0.t
+// CHECK-INST: vmsle.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x74]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 74 <unknown>
+
+vmsle.vv v1, v3, v2
+// CHECK-INST: vmsle.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x76]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 76 <unknown>
+
+vmsle.vx v1, v3, a0, v0.t
+// CHECK-INST: vmsle.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x74]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 74 <unknown>
+
+vmsle.vx v1, v3, a0
+// CHECK-INST: vmsle.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x76]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 76 <unknown>
+
+vmsle.vi v1, v3, 15, v0.t
+// CHECK-INST: vmsle.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x74]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 74 <unknown>
+
+vmsle.vi v1, v3, 15
+// CHECK-INST: vmsle.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x76]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 76 <unknown>
+
+vmsgtu.vx v1, v3, a0, v0.t
+// CHECK-INST: vmsgtu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x78]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 78 <unknown>
+
+vmsgtu.vx v1, v3, a0
+// CHECK-INST: vmsgtu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x7a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 7a <unknown>
+
+vmsgtu.vi v1, v3, 15, v0.t
+// CHECK-INST: vmsgtu.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x78]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 78 <unknown>
+
+vmsgtu.vi v1, v3, 15
+// CHECK-INST: vmsgtu.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x7a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 7a <unknown>
+
+vmsgt.vx v1, v3, a0, v0.t
+// CHECK-INST: vmsgt.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x7c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 7c <unknown>
+
+vmsgt.vx v1, v3, a0
+// CHECK-INST: vmsgt.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x7e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 7e <unknown>
+
+vmsgt.vi v1, v3, 15, v0.t
+// CHECK-INST: vmsgt.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x7c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 7c <unknown>
+
+vmsgt.vi v1, v3, 15
+// CHECK-INST: vmsgt.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x7e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 7e <unknown>
+
+vmfeq.vv v1, v3, v2, v0.t
+// CHECK-INST: vmfeq.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x60]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 60 <unknown>
+
+vmfeq.vv v1, v3, v2
+// CHECK-INST: vmfeq.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x62]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 62 <unknown>
+
+vmfeq.vf v1, v3, fa0, v0.t
+// CHECK-INST: vmfeq.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x60]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 60 <unknown>
+
+vmfeq.vf v1, v3, fa0
+// CHECK-INST: vmfeq.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x62]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 62 <unknown>
+
+vmfne.vv v1, v3, v2, v0.t
+// CHECK-INST: vmfne.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x70]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 70 <unknown>
+
+vmfne.vv v1, v3, v2
+// CHECK-INST: vmfne.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x72]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 72 <unknown>
+
+vmfne.vf v1, v3, fa0, v0.t
+// CHECK-INST: vmfne.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x70]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 70 <unknown>
+
+vmfne.vf v1, v3, fa0
+// CHECK-INST: vmfne.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x72]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 72 <unknown>
+
+vmflt.vv v1, v3, v2, v0.t
+// CHECK-INST: vmflt.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x6c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 6c <unknown>
+
+vmflt.vv v1, v3, v2
+// CHECK-INST: vmflt.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x6e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 6e <unknown>
+
+vmflt.vf v1, v3, fa0, v0.t
+// CHECK-INST: vmflt.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x6c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 6c <unknown>
+
+vmflt.vf v1, v3, fa0
+// CHECK-INST: vmflt.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x6e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 6e <unknown>
+
+vmfle.vv v1, v3, v2, v0.t
+// CHECK-INST: vmfle.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x64]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 64 <unknown>
+
+vmfle.vv v1, v3, v2
+// CHECK-INST: vmfle.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x66]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 66 <unknown>
+
+vmfle.vf v1, v3, fa0, v0.t
+// CHECK-INST: vmfle.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x64]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 64 <unknown>
+
+vmfle.vf v1, v3, fa0
+// CHECK-INST: vmfle.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x66]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 66 <unknown>
+
+vmfgt.vf v1, v3, fa0, v0.t
+// CHECK-INST: vmfgt.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x74]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 74 <unknown>
+
+vmfgt.vf v1, v3, fa0
+// CHECK-INST: vmfgt.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x76]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 76 <unknown>
+
+vmfge.vf v1, v3, fa0, v0.t
+// CHECK-INST: vmfge.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x7c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 7c <unknown>
+
+vmfge.vf v1, v3, fa0
+// CHECK-INST: vmfge.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x7e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 7e <unknown>
Index: llvm/test/MC/RISCV/rvv/convert.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/convert.s
@@ -0,0 +1,187 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vfcvt.xu.f.v v1, v3, v0.t
+// CHECK-INST: vfcvt.xu.f.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x30,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 30 88 <unknown>
+
+vfcvt.xu.f.v v1, v3
+// CHECK-INST: vfcvt.xu.f.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x30,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 30 8a <unknown>
+
+vfcvt.x.f.v v1, v3, v0.t
+// CHECK-INST: vfcvt.x.f.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x30,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 30 88 <unknown>
+
+vfcvt.x.f.v v1, v3
+// CHECK-INST: vfcvt.x.f.v v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x30,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 30 8a <unknown>
+
+vfcvt.f.xu.v v1, v3, v0.t
+// CHECK-INST: vfcvt.f.xu.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 88 <unknown>
+
+vfcvt.f.xu.v v1, v3
+// CHECK-INST: vfcvt.f.xu.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 8a <unknown>
+
+vfcvt.f.x.v v1, v3, v0.t
+// CHECK-INST: vfcvt.f.x.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x31,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 31 88 <unknown>
+
+vfcvt.f.x.v v1, v3
+// CHECK-INST: vfcvt.f.x.v v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x31,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 31 8a <unknown>
+
+vfwcvt.xu.f.v v1, v3, v0.t
+// CHECK-INST: vfwcvt.xu.f.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x34,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 34 88 <unknown>
+
+vfwcvt.xu.f.v v1, v3
+// CHECK-INST: vfwcvt.xu.f.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x34,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 34 8a <unknown>
+
+vfwcvt.x.f.v v1, v3, v0.t
+// CHECK-INST: vfwcvt.x.f.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x34,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 34 88 <unknown>
+
+vfwcvt.x.f.v v1, v3
+// CHECK-INST: vfwcvt.x.f.v v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x34,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 34 8a <unknown>
+
+vfwcvt.f.xu.v v1, v3, v0.t
+// CHECK-INST: vfwcvt.f.xu.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x35,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 35 88 <unknown>
+
+vfwcvt.f.xu.v v1, v3
+// CHECK-INST: vfwcvt.f.xu.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x35,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 35 8a <unknown>
+
+vfwcvt.f.x.v v1, v3, v0.t
+// CHECK-INST: vfwcvt.f.x.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x35,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 35 88 <unknown>
+
+vfwcvt.f.x.v v1, v3
+// CHECK-INST: vfwcvt.f.x.v v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x35,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 35 8a <unknown>
+
+vfwcvt.f.f.v v1, v3, v0.t
+// CHECK-INST: vfwcvt.f.f.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x36,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 36 88 <unknown>
+
+vfwcvt.f.f.v v1, v3
+// CHECK-INST: vfwcvt.f.f.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x36,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 36 8a <unknown>
+
+vfncvt.xu.f.w v1, v3, v0.t
+// CHECK-INST: vfncvt.xu.f.w v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x38,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 38 88 <unknown>
+
+vfncvt.xu.f.w v1, v3
+// CHECK-INST: vfncvt.xu.f.w v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x38,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 38 8a <unknown>
+
+vfncvt.x.f.w v1, v3, v0.t
+// CHECK-INST: vfncvt.x.f.w v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x38,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 38 88 <unknown>
+
+vfncvt.x.f.w v1, v3
+// CHECK-INST: vfncvt.x.f.w v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x38,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 38 8a <unknown>
+
+vfncvt.f.xu.w v1, v3, v0.t
+// CHECK-INST: vfncvt.f.xu.w v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x39,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 39 88 <unknown>
+
+vfncvt.f.xu.w v1, v3
+// CHECK-INST: vfncvt.f.xu.w v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x39,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 39 8a <unknown>
+
+vfncvt.f.x.w v1, v3, v0.t
+// CHECK-INST: vfncvt.f.x.w v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x39,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 39 88 <unknown>
+
+vfncvt.f.x.w v1, v3
+// CHECK-INST: vfncvt.f.x.w v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x39,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 39 8a <unknown>
+
+vfncvt.f.f.w v1, v3, v0.t
+// CHECK-INST: vfncvt.f.f.w v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x3a,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 3a 88 <unknown>
+
+vfncvt.f.f.w v1, v3
+// CHECK-INST: vfncvt.f.f.w v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x3a,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 3a 8a <unknown>
+
+vfncvt.rod.f.f.w v1, v3, v0.t
+// CHECK-INST: vfncvt.rod.f.f.w v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x90,0x3a,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 3a 88 <unknown>
+
+vfncvt.rod.f.f.w v1, v3
+// CHECK-INST: vfncvt.rod.f.f.w v1, v3
+// CHECK-ENCODING: [0xd7,0x90,0x3a,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 90 3a 8a <unknown>
Index: llvm/test/MC/RISCV/rvv/div.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/div.s
@@ -0,0 +1,139 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vdivu.vv v1, v3, v2, v0.t
+// CHECK-INST: vdivu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 80 <unknown>
+
+vdivu.vv v1, v3, v2
+// CHECK-INST: vdivu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 82 <unknown>
+
+vdivu.vx v1, v3, a0, v0.t
+// CHECK-INST: vdivu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 80 <unknown>
+
+vdivu.vx v1, v3, a0
+// CHECK-INST: vdivu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 82 <unknown>
+
+vdiv.vv v1, v3, v2, v0.t
+// CHECK-INST: vdiv.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x84]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 84 <unknown>
+
+vdiv.vv v1, v3, v2
+// CHECK-INST: vdiv.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x86]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 86 <unknown>
+
+vdiv.vx v1, v3, a0, v0.t
+// CHECK-INST: vdiv.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x84]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 84 <unknown>
+
+vdiv.vx v1, v3, a0
+// CHECK-INST: vdiv.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x86]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 86 <unknown>
+
+vremu.vv v1, v3, v2, v0.t
+// CHECK-INST: vremu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 88 <unknown>
+
+vremu.vv v1, v3, v2
+// CHECK-INST: vremu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 8a <unknown>
+
+vremu.vx v1, v3, a0, v0.t
+// CHECK-INST: vremu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 88 <unknown>
+
+vremu.vx v1, v3, a0
+// CHECK-INST: vremu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 8a <unknown>
+
+vrem.vv v1, v3, v2, v0.t
+// CHECK-INST: vrem.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x8c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 8c <unknown>
+
+vrem.vv v1, v3, v2
+// CHECK-INST: vrem.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x8e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 8e <unknown>
+
+vrem.vx v1, v3, a0, v0.t
+// CHECK-INST: vrem.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x8c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 8c <unknown>
+
+vrem.vx v1, v3, a0
+// CHECK-INST: vrem.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x8e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 8e <unknown>
+
+vfdiv.vv v1, v3, v2, v0.t
+// CHECK-INST: vfdiv.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 80 <unknown>
+
+vfdiv.vv v1, v3, v2
+// CHECK-INST: vfdiv.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 82 <unknown>
+
+vfdiv.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfdiv.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 80 <unknown>
+
+vfdiv.vf v1, v3, fa0
+// CHECK-INST: vfdiv.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x82]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 82 <unknown>
+
+vfrdiv.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfrdiv.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x84]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 84 <unknown>
+
+vfrdiv.vf v1, v3, fa0
+// CHECK-INST: vfrdiv.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x86]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 86 <unknown>
Index: llvm/test/MC/RISCV/rvv/invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/invalid.s
@@ -0,0 +1,689 @@
+// RUN: not llvm-mc -triple=riscv64 -mattr=+v < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+vsetvli a2, a0, e31
+// CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e32,m3
+// CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, m1,e32
+// CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e32,m16
+// CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e2048,m8
+// CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e1,m8
+// CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vadd.vv v1, v3, v2, v4.t
+// CHECK-ERROR: invalid operand for instruction
+
+vwaddu.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwaddu.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsubu.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsubu.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwadd.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwadd.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsub.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsub.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmul.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmul.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmulu.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmulu.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmulsu.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmulsu.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmaccu.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmaccu.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmacc.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmacc.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmaccsu.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmaccsu.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwmaccus.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmaccu.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmaccu.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmacc.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmacc.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmaccsu.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmaccsu.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwsmaccus.vx v0, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwadd.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwadd.vf v0, v1, fa0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwsub.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwsub.vf v0, v1, fa0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwmul.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwmul.vf v0, v1, fa0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwmacc.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwmacc.vf v0, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwnmacc.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwnmacc.vf v0, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwmsac.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwmsac.vf v0, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwnmsac.vv v0, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwnmsac.vf v0, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vrgather.vv v0, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vrgather.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vrgather.vi v0, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vwaddu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwaddu.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsubu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsubu.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwadd.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwadd.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsub.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsub.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmul.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmul.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulu.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulsu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulsu.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccu.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmacc.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmacc.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccsu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccsu.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccus.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccu.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmacc.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmacc.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccsu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccsu.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccus.vx v1, a0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwadd.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwadd.vf v1, v1, fa0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwsub.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwsub.vf v1, v1, fa0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmul.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmul.vf v1, v1, fa0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmacc.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmacc.vf v1, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmacc.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmacc.vf v1, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmsac.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmsac.vf v1, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmsac.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmsac.vf v1, fa0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwaddu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsubu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwadd.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsub.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmul.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulsu.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmacc.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccsu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmacc.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccsu.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwadd.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwsub.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmul.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmacc.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmacc.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmsac.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmsac.vv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vv v1, v2, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwaddu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsubu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwadd.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsub.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmul.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulsu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmacc.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccsu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmacc.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccsu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwadd.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwsub.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmul.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmacc.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmacc.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmsac.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmsac.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vi v1, v1, 31
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwaddu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsubu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwadd.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsub.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmul.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmulsu.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmacc.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwmaccsu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmacc.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vwsmaccsu.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwadd.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwsub.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmul.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmacc.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmacc.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwmsac.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwnmsac.vv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vv v1, v2, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vcompress.vm v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vcompress.vm v2, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vrgather.vi v0, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwcvt.xu.f.v v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.x.f.v v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.f.xu.v v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.f.x.v v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.f.f.v v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+viota.m v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsrl.wv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsrl.wx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsrl.wi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsra.wv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsra.wx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsra.wi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclipu.wv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclipu.wx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclipu.wi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclip.wv v1, v1, v2, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclip.wx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclip.wi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.xu.f.w v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.x.f.w v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.f.xu.w v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.f.x.w v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.f.f.w v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.rod.f.f.w v1, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.xu.f.v v0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwcvt.x.f.v v0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwcvt.f.xu.v v0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwcvt.f.x.v v0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwcvt.f.f.v v0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+viota.m v0, v1, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vfwcvt.xu.f.v v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.x.f.v v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.f.xu.v v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.f.x.v v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfwcvt.f.f.v v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+viota.m v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsrl.wv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsrl.wx v1, v1, a0
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsrl.wi v1, v1, 31
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsra.wv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsra.wx v1, v1, a0
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnsra.wi v1, v1, 31
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclipu.wv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclipu.wx v1, v1, a0
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclipu.wi v1, v1, 31
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclip.wv v1, v1, v2
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclip.wx v1, v1, a0
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vnclip.wi v1, v1, 31
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.xu.f.w v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.x.f.w v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.f.xu.w v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.f.x.w v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.f.f.w v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vfncvt.rod.f.f.w v1, v1
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vslideup.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vslideup.vi v0, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vslide1up.vx v0, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+
+vslideup.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vslideup.vi v1, v1, 31, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vslide1up.vx v1, v1, a0, v0.t
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vslideup.vx v1, v1, a0
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vslideup.vi v1, v1, 31
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+
+vslide1up.vx v1, v1, a0
+// CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
Index: llvm/test/MC/RISCV/rvv/load.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/load.s
@@ -0,0 +1,331 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vlb.v v1, (a0), v0.t
+// CHECK-INST: vlb.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x00,0x05,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 10 <unknown>
+
+vlb.v v1, (a0)
+// CHECK-INST: vlb.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x00,0x05,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 12 <unknown>
+
+vlh.v v1, (a0), v0.t
+// CHECK-INST: vlh.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x50,0x05,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 10 <unknown>
+
+vlh.v v1, (a0)
+// CHECK-INST: vlh.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x50,0x05,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 12 <unknown>
+
+vlw.v v1, (a0), v0.t
+// CHECK-INST: vlw.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x60,0x05,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 10 <unknown>
+
+vlw.v v1, (a0)
+// CHECK-INST: vlw.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x60,0x05,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 12 <unknown>
+
+vlbu.v v1, (a0), v0.t
+// CHECK-INST: vlbu.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x00,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 00 <unknown>
+
+vlbu.v v1, (a0)
+// CHECK-INST: vlbu.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x00,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 02 <unknown>
+
+vlhu.v v1, (a0), v0.t
+// CHECK-INST: vlhu.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x50,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 00 <unknown>
+
+vlhu.v v1, (a0)
+// CHECK-INST: vlhu.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x50,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 02 <unknown>
+
+vlwu.v v1, (a0), v0.t
+// CHECK-INST: vlwu.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x60,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 00 <unknown>
+
+vlwu.v v1, (a0)
+// CHECK-INST: vlwu.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x60,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 02 <unknown>
+
+vlbff.v v1, (a0), v0.t
+// CHECK-INST: vlbff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x00,0x05,0x11]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 11 <unknown>
+
+vlbff.v v1, (a0)
+// CHECK-INST: vlbff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x00,0x05,0x13]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 13 <unknown>
+
+vlhff.v v1, (a0), v0.t
+// CHECK-INST: vlhff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x50,0x05,0x11]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 11 <unknown>
+
+vlhff.v v1, (a0)
+// CHECK-INST: vlhff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x50,0x05,0x13]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 13 <unknown>
+
+vlwff.v v1, (a0), v0.t
+// CHECK-INST: vlwff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x60,0x05,0x11]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 11 <unknown>
+
+vlwff.v v1, (a0)
+// CHECK-INST: vlwff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x60,0x05,0x13]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 13 <unknown>
+
+vlbuff.v v1, (a0), v0.t
+// CHECK-INST: vlbuff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x00,0x05,0x01]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 01 <unknown>
+
+vlbuff.v v1, (a0)
+// CHECK-INST: vlbuff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x00,0x05,0x03]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 05 03 <unknown>
+
+vlhuff.v v1, (a0), v0.t
+// CHECK-INST: vlhuff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x50,0x05,0x01]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 01 <unknown>
+
+vlhuff.v v1, (a0)
+// CHECK-INST: vlhuff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x50,0x05,0x03]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 05 03 <unknown>
+
+vlwuff.v v1, (a0), v0.t
+// CHECK-INST: vlwuff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x60,0x05,0x01]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 01 <unknown>
+
+vlwuff.v v1, (a0)
+// CHECK-INST: vlwuff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x60,0x05,0x03]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 05 03 <unknown>
+
+vleff.v v1, (a0), v0.t
+// CHECK-INST: vleff.v v1, (a0), v0.t
+// CHECK-ENCODING: [0x87,0x70,0x05,0x01]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 70 05 01 <unknown>
+
+vleff.v v1, (a0)
+// CHECK-INST: vleff.v v1, (a0)
+// CHECK-ENCODING: [0x87,0x70,0x05,0x03]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 70 05 03 <unknown>
+
+vlsb.v v1, (a0), a1, v0.t
+// CHECK-INST: vlsb.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x00,0xb5,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 b5 18 <unknown>
+
+vlsb.v v1, (a0), a1
+// CHECK-INST: vlsb.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x00,0xb5,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 b5 1a <unknown>
+
+vlsh.v v1, (a0), a1, v0.t
+// CHECK-INST: vlsh.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x50,0xb5,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 b5 18 <unknown>
+
+vlsh.v v1, (a0), a1
+// CHECK-INST: vlsh.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x50,0xb5,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 b5 1a <unknown>
+
+vlsw.v v1, (a0), a1, v0.t
+// CHECK-INST: vlsw.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x60,0xb5,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 b5 18 <unknown>
+
+vlsw.v v1, (a0), a1
+// CHECK-INST: vlsw.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x60,0xb5,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 b5 1a <unknown>
+
+vlsbu.v v1, (a0), a1, v0.t
+// CHECK-INST: vlsbu.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x00,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 b5 08 <unknown>
+
+vlsbu.v v1, (a0), a1
+// CHECK-INST: vlsbu.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x00,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 b5 0a <unknown>
+
+vlshu.v v1, (a0), a1, v0.t
+// CHECK-INST: vlshu.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x50,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 b5 08 <unknown>
+
+vlshu.v v1, (a0), a1
+// CHECK-INST: vlshu.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x50,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 b5 0a <unknown>
+
+vlswu.v v1, (a0), a1, v0.t
+// CHECK-INST: vlswu.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x60,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 b5 08 <unknown>
+
+vlswu.v v1, (a0), a1
+// CHECK-INST: vlswu.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x60,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 b5 0a <unknown>
+
+vlse.v v1, (a0), a1, v0.t
+// CHECK-INST: vlse.v v1, (a0), a1, v0.t
+// CHECK-ENCODING: [0x87,0x70,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 70 b5 08 <unknown>
+
+vlse.v v1, (a0), a1
+// CHECK-INST: vlse.v v1, (a0), a1
+// CHECK-ENCODING: [0x87,0x70,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 70 b5 0a <unknown>
+
+vlxb.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxb.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x00,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 35 1c <unknown>
+
+vlxb.v v1, (a0), v3
+// CHECK-INST: vlxb.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x00,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 35 1e <unknown>
+
+vlxh.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxh.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x50,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 35 1c <unknown>
+
+vlxh.v v1, (a0), v3
+// CHECK-INST: vlxh.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x50,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 35 1e <unknown>
+
+vlxw.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxw.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x60,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 35 1c <unknown>
+
+vlxw.v v1, (a0), v3
+// CHECK-INST: vlxw.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x60,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 35 1e <unknown>
+
+vlxbu.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxbu.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x00,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 35 0c <unknown>
+
+vlxbu.v v1, (a0), v3
+// CHECK-INST: vlxbu.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x00,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 00 35 0e <unknown>
+
+vlxhu.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxhu.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x50,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 35 0c <unknown>
+
+vlxhu.v v1, (a0), v3
+// CHECK-INST: vlxhu.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x50,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 50 35 0e <unknown>
+
+vlxwu.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxwu.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x60,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 35 0c <unknown>
+
+vlxwu.v v1, (a0), v3
+// CHECK-INST: vlxwu.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x60,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 60 35 0e <unknown>
+
+vlxe.v v1, (a0), v3, v0.t
+// CHECK-INST: vlxe.v v1, (a0), v3, v0.t
+// CHECK-ENCODING: [0x87,0x70,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 70 35 0c <unknown>
+
+vlxe.v v1, (a0), v3
+// CHECK-INST: vlxe.v v1, (a0), v3
+// CHECK-ENCODING: [0x87,0x70,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 87 70 35 0e <unknown>
Index: llvm/test/MC/RISCV/rvv/macc.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/macc.s
@@ -0,0 +1,559 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 b4 <unknown>
+
+vmacc.vv v1, v2, v3
+// CHECK-INST: vmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 b6 <unknown>
+
+vmacc.vx v1, a0, v3, v0.t
+// CHECK-INST: vmacc.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 b4 <unknown>
+
+vmacc.vx v1, a0, v3
+// CHECK-INST: vmacc.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 b6 <unknown>
+
+vnmsac.vv v1, v2, v3, v0.t
+// CHECK-INST: vnmsac.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 bc <unknown>
+
+vnmsac.vv v1, v2, v3
+// CHECK-INST: vnmsac.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 be <unknown>
+
+vnmsac.vx v1, a0, v3, v0.t
+// CHECK-INST: vnmsac.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 bc <unknown>
+
+vnmsac.vx v1, a0, v3
+// CHECK-INST: vnmsac.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 be <unknown>
+
+vmadd.vv v1, v2, v3, v0.t
+// CHECK-INST: vmadd.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 a4 <unknown>
+
+vmadd.vv v1, v2, v3
+// CHECK-INST: vmadd.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 a6 <unknown>
+
+vmadd.vx v1, a0, v3, v0.t
+// CHECK-INST: vmadd.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 a4 <unknown>
+
+vmadd.vx v1, a0, v3
+// CHECK-INST: vmadd.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 a6 <unknown>
+
+vnmsub.vv v1, v2, v3, v0.t
+// CHECK-INST: vnmsub.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ac <unknown>
+
+vnmsub.vv v1, v2, v3
+// CHECK-INST: vnmsub.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ae <unknown>
+
+vnmsub.vx v1, a0, v3, v0.t
+// CHECK-INST: vnmsub.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ac <unknown>
+
+vnmsub.vx v1, a0, v3
+// CHECK-INST: vnmsub.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ae <unknown>
+
+vwmaccu.vv v1, v2, v3, v0.t
+// CHECK-INST: vwmaccu.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xf0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 f0 <unknown>
+
+vwmaccu.vv v1, v2, v3
+// CHECK-INST: vwmaccu.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xf2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 f2 <unknown>
+
+vwmaccu.vx v1, a0, v3, v0.t
+// CHECK-INST: vwmaccu.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xf0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 f0 <unknown>
+
+vwmaccu.vx v1, a0, v3
+// CHECK-INST: vwmaccu.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xf2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 f2 <unknown>
+
+vwmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vwmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xf4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 f4 <unknown>
+
+vwmacc.vv v1, v2, v3
+// CHECK-INST: vwmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xf6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 f6 <unknown>
+
+vwmacc.vx v1, a0, v3, v0.t
+// CHECK-INST: vwmacc.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xf4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 f4 <unknown>
+
+vwmacc.vx v1, a0, v3
+// CHECK-INST: vwmacc.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xf6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 f6 <unknown>
+
+vwmaccsu.vv v1, v2, v3, v0.t
+// CHECK-INST: vwmaccsu.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xfc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 fc <unknown>
+
+vwmaccsu.vv v1, v2, v3
+// CHECK-INST: vwmaccsu.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xfe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 fe <unknown>
+
+vwmaccsu.vx v1, a0, v3, v0.t
+// CHECK-INST: vwmaccsu.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xfc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 fc <unknown>
+
+vwmaccsu.vx v1, a0, v3
+// CHECK-INST: vwmaccsu.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xfe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 fe <unknown>
+
+vwmaccus.vx v1, a0, v3, v0.t
+// CHECK-INST: vwmaccus.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xf8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 f8 <unknown>
+
+vwmaccus.vx v1, a0, v3
+// CHECK-INST: vwmaccus.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xfa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 fa <unknown>
+
+vwsmaccu.vv v1, v2, v3, v0.t
+// CHECK-INST: vwsmaccu.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xf0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 f0 <unknown>
+
+vwsmaccu.vv v1, v2, v3
+// CHECK-INST: vwsmaccu.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xf2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 f2 <unknown>
+
+vwsmaccu.vx v1, a0, v3, v0.t
+// CHECK-INST: vwsmaccu.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xf0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 f0 <unknown>
+
+vwsmaccu.vx v1, a0, v3
+// CHECK-INST: vwsmaccu.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xf2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 f2 <unknown>
+
+vwsmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vwsmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xf4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 f4 <unknown>
+
+vwsmacc.vv v1, v2, v3
+// CHECK-INST: vwsmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xf6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 f6 <unknown>
+
+vwsmacc.vx v1, a0, v3, v0.t
+// CHECK-INST: vwsmacc.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xf4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 f4 <unknown>
+
+vwsmacc.vx v1, a0, v3
+// CHECK-INST: vwsmacc.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xf6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 f6 <unknown>
+
+vwsmaccsu.vv v1, v2, v3, v0.t
+// CHECK-INST: vwsmaccsu.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xfc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 fc <unknown>
+
+vwsmaccsu.vv v1, v2, v3
+// CHECK-INST: vwsmaccsu.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xfe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 fe <unknown>
+
+vwsmaccsu.vx v1, a0, v3, v0.t
+// CHECK-INST: vwsmaccsu.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xfc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 fc <unknown>
+
+vwsmaccsu.vx v1, a0, v3
+// CHECK-INST: vwsmaccsu.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xfe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 fe <unknown>
+
+vwsmaccus.vx v1, a0, v3, v0.t
+// CHECK-INST: vwsmaccus.vx v1, a0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xf8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 f8 <unknown>
+
+vwsmaccus.vx v1, a0, v3
+// CHECK-INST: vwsmaccus.vx v1, a0, v3
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xfa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 fa <unknown>
+
+vfmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vfmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xb0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 b0 <unknown>
+
+vfmacc.vv v1, v2, v3
+// CHECK-INST: vfmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xb2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 b2 <unknown>
+
+vfmacc.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfmacc.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xb0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 b0 <unknown>
+
+vfmacc.vf v1, fa0, v3
+// CHECK-INST: vfmacc.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xb2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 b2 <unknown>
+
+vfnmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vfnmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 b4 <unknown>
+
+vfnmacc.vv v1, v2, v3
+// CHECK-INST: vfnmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 b6 <unknown>
+
+vfnmacc.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfnmacc.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 b4 <unknown>
+
+vfnmacc.vf v1, fa0, v3
+// CHECK-INST: vfnmacc.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 b6 <unknown>
+
+vfmsac.vv v1, v2, v3, v0.t
+// CHECK-INST: vfmsac.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xb8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 b8 <unknown>
+
+vfmsac.vv v1, v2, v3
+// CHECK-INST: vfmsac.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xba]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 ba <unknown>
+
+vfmsac.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfmsac.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xb8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 b8 <unknown>
+
+vfmsac.vf v1, fa0, v3
+// CHECK-INST: vfmsac.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xba]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 ba <unknown>
+
+vfnmsac.vv v1, v2, v3, v0.t
+// CHECK-INST: vfnmsac.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 bc <unknown>
+
+vfnmsac.vv v1, v2, v3
+// CHECK-INST: vfnmsac.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 be <unknown>
+
+vfnmsac.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfnmsac.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xbc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 bc <unknown>
+
+vfnmsac.vf v1, fa0, v3
+// CHECK-INST: vfnmsac.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xbe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 be <unknown>
+
+vfmadd.vv v1, v2, v3, v0.t
+// CHECK-INST: vfmadd.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xa0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 a0 <unknown>
+
+vfmadd.vv v1, v2, v3
+// CHECK-INST: vfmadd.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xa2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 a2 <unknown>
+
+vfmadd.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfmadd.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xa0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 a0 <unknown>
+
+vfmadd.vf v1, fa0, v3
+// CHECK-INST: vfmadd.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xa2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 a2 <unknown>
+
+vfnmadd.vv v1, v2, v3, v0.t
+// CHECK-INST: vfnmadd.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 a4 <unknown>
+
+vfnmadd.vv v1, v2, v3
+// CHECK-INST: vfnmadd.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 a6 <unknown>
+
+vfnmadd.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfnmadd.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 a4 <unknown>
+
+vfnmadd.vf v1, fa0, v3
+// CHECK-INST: vfnmadd.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 a6 <unknown>
+
+vfmsub.vv v1, v2, v3, v0.t
+// CHECK-INST: vfmsub.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xa8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 a8 <unknown>
+
+vfmsub.vv v1, v2, v3
+// CHECK-INST: vfmsub.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xaa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 aa <unknown>
+
+vfmsub.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfmsub.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xa8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 a8 <unknown>
+
+vfmsub.vf v1, fa0, v3
+// CHECK-INST: vfmsub.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xaa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 aa <unknown>
+
+vfnmsub.vv v1, v2, v3, v0.t
+// CHECK-INST: vfnmsub.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 ac <unknown>
+
+vfnmsub.vv v1, v2, v3
+// CHECK-INST: vfnmsub.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 ae <unknown>
+
+vfnmsub.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfnmsub.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 ac <unknown>
+
+vfnmsub.vf v1, fa0, v3
+// CHECK-INST: vfnmsub.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 ae <unknown>
+
+vfwmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vfwmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xf0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 f0 <unknown>
+
+vfwmacc.vv v1, v2, v3
+// CHECK-INST: vfwmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xf2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 f2 <unknown>
+
+vfwmacc.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfwmacc.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xf0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 f0 <unknown>
+
+vfwmacc.vf v1, fa0, v3
+// CHECK-INST: vfwmacc.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xf2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 f2 <unknown>
+
+vfwnmacc.vv v1, v2, v3, v0.t
+// CHECK-INST: vfwnmacc.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xf4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 f4 <unknown>
+
+vfwnmacc.vv v1, v2, v3
+// CHECK-INST: vfwnmacc.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xf6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 f6 <unknown>
+
+vfwnmacc.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfwnmacc.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xf4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 f4 <unknown>
+
+vfwnmacc.vf v1, fa0, v3
+// CHECK-INST: vfwnmacc.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xf6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 f6 <unknown>
+
+vfwmsac.vv v1, v2, v3, v0.t
+// CHECK-INST: vfwmsac.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xf8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 f8 <unknown>
+
+vfwmsac.vv v1, v2, v3
+// CHECK-INST: vfwmsac.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xfa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 fa <unknown>
+
+vfwmsac.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfwmsac.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xf8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 f8 <unknown>
+
+vfwmsac.vf v1, fa0, v3
+// CHECK-INST: vfwmsac.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xfa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 fa <unknown>
+
+vfwnmsac.vv v1, v2, v3, v0.t
+// CHECK-INST: vfwnmsac.vv v1, v2, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xfc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 fc <unknown>
+
+vfwnmsac.vv v1, v2, v3
+// CHECK-INST: vfwnmsac.vv v1, v2, v3
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xfe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 fe <unknown>
+
+vfwnmsac.vf v1, fa0, v3, v0.t
+// CHECK-INST: vfwnmsac.vf v1, fa0, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xfc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 fc <unknown>
+
+vfwnmsac.vf v1, fa0, v3
+// CHECK-INST: vfwnmsac.vf v1, fa0, v3
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xfe]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 fe <unknown>
Index: llvm/test/MC/RISCV/rvv/mask.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/mask.s
@@ -0,0 +1,139 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmand.mm v1, v3, v2
+// CHECK-INST: vmand.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x66]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 66 <unknown>
+
+vmnand.mm v1, v3, v2
+// CHECK-INST: vmnand.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x76]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 76 <unknown>
+
+vmandnot.mm v1, v3, v2
+// CHECK-INST: vmandnot.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x62]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 62 <unknown>
+
+vmxor.mm v1, v3, v2
+// CHECK-INST: vmxor.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x6e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 6e <unknown>
+
+vmor.mm v1, v3, v2
+// CHECK-INST: vmor.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x6a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 6a <unknown>
+
+vmnor.mm v1, v3, v2
+// CHECK-INST: vmnor.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x7a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 7a <unknown>
+
+vmornot.mm v1, v3, v2
+// CHECK-INST: vmornot.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x72]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 72 <unknown>
+
+vmxnor.mm v1, v3, v2
+// CHECK-INST: vmxnor.mm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x7e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 7e <unknown>
+
+vpopc.m a2, v3, v0.t
+// CHECK-INST: vpopc.m a2, v3, v0.t
+// CHECK-ENCODING: [0x57,0x26,0x38,0x40]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 26 38 40 <unknown>
+
+vpopc.m a2, v3
+// CHECK-INST: vpopc.m a2, v3
+// CHECK-ENCODING: [0x57,0x26,0x38,0x42]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 26 38 42 <unknown>
+
+vfirst.m a2, v3, v0.t
+// CHECK-INST: vfirst.m a2, v3, v0.t
+// CHECK-ENCODING: [0x57,0xa6,0x38,0x40]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 a6 38 40 <unknown>
+
+vfirst.m a2, v3
+// CHECK-INST: vfirst.m a2, v3
+// CHECK-ENCODING: [0x57,0xa6,0x38,0x42]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 a6 38 42 <unknown>
+
+vmsbf.m v1, v3, v0.t
+// CHECK-INST: vmsbf.m v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0xa0,0x30,0x50]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 a0 30 50 <unknown>
+
+vmsbf.m v1, v3
+// CHECK-INST: vmsbf.m v1, v3
+// CHECK-ENCODING: [0xd7,0xa0,0x30,0x52]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 a0 30 52 <unknown>
+
+vmsif.m v1, v3, v0.t
+// CHECK-INST: vmsif.m v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0xa0,0x31,0x50]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 a0 31 50 <unknown>
+
+vmsif.m v1, v3
+// CHECK-INST: vmsif.m v1, v3
+// CHECK-ENCODING: [0xd7,0xa0,0x31,0x52]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 a0 31 52 <unknown>
+
+vmsof.m v1, v3, v0.t
+// CHECK-INST: vmsof.m v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x50]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 50 <unknown>
+
+vmsof.m v1, v3
+// CHECK-INST: vmsof.m v1, v3
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x52]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 52 <unknown>
+
+viota.m v1, v3, v0.t
+// CHECK-INST: viota.m v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x38,0x50]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 38 50 <unknown>
+
+viota.m v1, v3
+// CHECK-INST: viota.m v1, v3
+// CHECK-ENCODING: [0xd7,0x20,0x38,0x52]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 38 52 <unknown>
+
+vid.v v1, v0.t
+// CHECK-INST: vid.v v1, v0.t
+// CHECK-ENCODING: [0xd7,0xa0,0x08,0x50]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 a0 08 50 <unknown>
+
+vid.v v1
+// CHECK-INST: vid.v v1
+// CHECK-ENCODING: [0xd7,0xa0,0x08,0x52]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 a0 08 52 <unknown>
Index: llvm/test/MC/RISCV/rvv/minmax.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/minmax.s
@@ -0,0 +1,151 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vminu.vv v1, v3, v2, v0.t
+// CHECK-INST: vminu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 10 <unknown>
+
+vminu.vv v1, v3, v2
+// CHECK-INST: vminu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 12 <unknown>
+
+vminu.vx v1, v3, a0, v0.t
+// CHECK-INST: vminu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 10 <unknown>
+
+vminu.vx v1, v3, a0
+// CHECK-INST: vminu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 12 <unknown>
+
+vmin.vv v1, v3, v2, v0.t
+// CHECK-INST: vmin.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x14]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 14 <unknown>
+
+vmin.vv v1, v3, v2
+// CHECK-INST: vmin.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x16]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 16 <unknown>
+
+vmin.vx v1, v3, a0, v0.t
+// CHECK-INST: vmin.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x14]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 14 <unknown>
+
+vmin.vx v1, v3, a0
+// CHECK-INST: vmin.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x16]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 16 <unknown>
+
+vmaxu.vv v1, v3, v2, v0.t
+// CHECK-INST: vmaxu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 18 <unknown>
+
+vmaxu.vv v1, v3, v2
+// CHECK-INST: vmaxu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 1a <unknown>
+
+vmaxu.vx v1, v3, a0, v0.t
+// CHECK-INST: vmaxu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 18 <unknown>
+
+vmaxu.vx v1, v3, a0
+// CHECK-INST: vmaxu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 1a <unknown>
+
+vmax.vv v1, v3, v2, v0.t
+// CHECK-INST: vmax.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 1c <unknown>
+
+vmax.vv v1, v3, v2
+// CHECK-INST: vmax.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 1e <unknown>
+
+vmax.vx v1, v3, a0, v0.t
+// CHECK-INST: vmax.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 1c <unknown>
+
+vmax.vx v1, v3, a0
+// CHECK-INST: vmax.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 1e <unknown>
+
+vfmin.vv v1, v3, v2, v0.t
+// CHECK-INST: vfmin.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 10 <unknown>
+
+vfmin.vv v1, v3, v2
+// CHECK-INST: vfmin.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 12 <unknown>
+
+vfmin.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfmin.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 10 <unknown>
+
+vfmin.vf v1, v3, fa0
+// CHECK-INST: vfmin.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 12 <unknown>
+
+vfmax.vv v1, v3, v2, v0.t
+// CHECK-INST: vfmax.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 18 <unknown>
+
+vfmax.vv v1, v3, v2
+// CHECK-INST: vfmax.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 1a <unknown>
+
+vfmax.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfmax.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 18 <unknown>
+
+vfmax.vf v1, v3, fa0
+// CHECK-INST: vfmax.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 1a <unknown>
Index: llvm/test/MC/RISCV/rvv/mul.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/mul.s
@@ -0,0 +1,247 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmul.vv v1, v3, v2, v0.t
+// CHECK-INST: vmul.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x94]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 94 <unknown>
+
+vmul.vv v1, v3, v2
+// CHECK-INST: vmul.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x96]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 96 <unknown>
+
+vmul.vx v1, v3, a0, v0.t
+// CHECK-INST: vmul.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x94]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 94 <unknown>
+
+vmul.vx v1, v3, a0
+// CHECK-INST: vmul.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x96]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 96 <unknown>
+
+vmulh.vv v1, v3, v2, v0.t
+// CHECK-INST: vmulh.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x9c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 9c <unknown>
+
+vmulh.vv v1, v3, v2
+// CHECK-INST: vmulh.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x9e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 9e <unknown>
+
+vmulh.vx v1, v3, a0, v0.t
+// CHECK-INST: vmulh.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x9c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 9c <unknown>
+
+vmulh.vx v1, v3, a0
+// CHECK-INST: vmulh.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x9e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 9e <unknown>
+
+vmulhu.vv v1, v3, v2, v0.t
+// CHECK-INST: vmulhu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 90 <unknown>
+
+vmulhu.vv v1, v3, v2
+// CHECK-INST: vmulhu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 92 <unknown>
+
+vmulhu.vx v1, v3, a0, v0.t
+// CHECK-INST: vmulhu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 90 <unknown>
+
+vmulhu.vx v1, v3, a0
+// CHECK-INST: vmulhu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 92 <unknown>
+
+vmulhsu.vv v1, v3, v2, v0.t
+// CHECK-INST: vmulhsu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x98]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 98 <unknown>
+
+vmulhsu.vv v1, v3, v2
+// CHECK-INST: vmulhsu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x9a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 9a <unknown>
+
+vmulhsu.vx v1, v3, a0, v0.t
+// CHECK-INST: vmulhsu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x98]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 98 <unknown>
+
+vmulhsu.vx v1, v3, a0
+// CHECK-INST: vmulhsu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x9a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 9a <unknown>
+
+vwmul.vv v1, v3, v2, v0.t
+// CHECK-INST: vwmul.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xec]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ec <unknown>
+
+vwmul.vv v1, v3, v2
+// CHECK-INST: vwmul.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xee]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ee <unknown>
+
+vwmul.vx v1, v3, a0, v0.t
+// CHECK-INST: vwmul.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xec]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ec <unknown>
+
+vwmul.vx v1, v3, a0
+// CHECK-INST: vwmul.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xee]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ee <unknown>
+
+vwmulu.vv v1, v3, v2, v0.t
+// CHECK-INST: vwmulu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xe0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 e0 <unknown>
+
+vwmulu.vv v1, v3, v2
+// CHECK-INST: vwmulu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xe2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 e2 <unknown>
+
+vwmulu.vx v1, v3, a0, v0.t
+// CHECK-INST: vwmulu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xe0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 e0 <unknown>
+
+vwmulu.vx v1, v3, a0
+// CHECK-INST: vwmulu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xe2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 e2 <unknown>
+
+vwmulsu.vv v1, v3, v2, v0.t
+// CHECK-INST: vwmulsu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xe8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 e8 <unknown>
+
+vwmulsu.vv v1, v3, v2
+// CHECK-INST: vwmulsu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xea]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ea <unknown>
+
+vwmulsu.vx v1, v3, a0, v0.t
+// CHECK-INST: vwmulsu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xe8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 e8 <unknown>
+
+vwmulsu.vx v1, v3, a0
+// CHECK-INST: vwmulsu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xea]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ea <unknown>
+
+vsmul.vv v1, v3, v2, v0.t
+// CHECK-INST: vsmul.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x9c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 9c <unknown>
+
+vsmul.vv v1, v3, v2
+// CHECK-INST: vsmul.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x9e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 9e <unknown>
+
+vsmul.vx v1, v3, a0, v0.t
+// CHECK-INST: vsmul.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x9c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 9c <unknown>
+
+vsmul.vx v1, v3, a0
+// CHECK-INST: vsmul.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x9e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 9e <unknown>
+
+vfmul.vv v1, v3, v2, v0.t
+// CHECK-INST: vfmul.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 90 <unknown>
+
+vfmul.vv v1, v3, v2
+// CHECK-INST: vfmul.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 92 <unknown>
+
+vfmul.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfmul.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x90]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 90 <unknown>
+
+vfmul.vf v1, v3, fa0
+// CHECK-INST: vfmul.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x92]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 92 <unknown>
+
+vfwmul.vv v1, v3, v2, v0.t
+// CHECK-INST: vfwmul.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xe0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 e0 <unknown>
+
+vfwmul.vv v1, v3, v2
+// CHECK-INST: vfwmul.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xe2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 e2 <unknown>
+
+vfwmul.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfwmul.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xe0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 e0 <unknown>
+
+vfwmul.vf v1, v3, fa0
+// CHECK-INST: vfwmul.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xe2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 e2 <unknown>
Index: llvm/test/MC/RISCV/rvv/mv.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/mv.s
@@ -0,0 +1,55 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmv.v.v v1, v2
+// CHECK-INST: vmv.v.v v1, v2
+// CHECK-ENCODING: [0xd7,0x00,0x01,0x5e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 01 5e <unknown>
+
+vmv.v.x v1, a0
+// CHECK-INST: vmv.v.x v1, a0
+// CHECK-ENCODING: [0xd7,0x40,0x05,0x5e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 05 5e <unknown>
+
+vmv.v.i v1, 15
+// CHECK-INST: vmv.v.i v1, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x07,0x5e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 07 5e <unknown>
+
+vmv.x.s a2, v3
+// CHECK-INST: vmv.x.s a2, v3
+// CHECK-ENCODING: [0x57,0x26,0x30,0x42]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 26 30 42 <unknown>
+
+vmv.s.x v1, a0
+// CHECK-INST: vmv.s.x v1, a0
+// CHECK-ENCODING: [0xd7,0x60,0x05,0x42]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 05 42 <unknown>
+
+vfmv.v.f v1, fa0
+// CHECK-INST: vfmv.v.f v1, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x05,0x5e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 05 5e <unknown>
+
+vfmv.f.s fa0, v3
+// CHECK-INST: vfmv.f.s fa0, v3
+// CHECK-ENCODING: [0x57,0x15,0x30,0x42]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 15 30 42 <unknown>
+
+vfmv.s.f v1, fa0
+// CHECK-INST: vfmv.s.f v1, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x05,0x42]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 05 42 <unknown>
Index: llvm/test/MC/RISCV/rvv/or.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/or.s
@@ -0,0 +1,43 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vor.vv v1, v3, v2, v0.t
+// CHECK-INST: vor.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x28]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 28 <unknown>
+
+vor.vv v1, v3, v2
+// CHECK-INST: vor.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x2a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 2a <unknown>
+
+vor.vx v1, v3, a0, v0.t
+// CHECK-INST: vor.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x28]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 28 <unknown>
+
+vor.vx v1, v3, a0
+// CHECK-INST: vor.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x2a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 2a <unknown>
+
+vor.vi v1, v3, 15, v0.t
+// CHECK-INST: vor.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x28]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 28 <unknown>
+
+vor.vi v1, v3, 15
+// CHECK-INST: vor.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x2a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 2a <unknown>
Index: llvm/test/MC/RISCV/rvv/others.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/others.s
@@ -0,0 +1,169 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmerge.vvm v1, v3, v2, v0
+// CHECK-INST: vmerge.vvm v1, v3, v2, v0
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x5c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 5c <unknown>
+
+vmerge.vxm v1, v3, a0, v0
+// CHECK-INST: vmerge.vxm v1, v3, a0, v0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x5c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 5c <unknown>
+
+vmerge.vim v1, v3, 15, v0
+// CHECK-INST: vmerge.vim v1, v3, 15, v0
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x5c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 5c <unknown>
+
+vslideup.vx v1, v3, a0, v0.t
+// CHECK-INST: vslideup.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x38]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 38 <unknown>
+
+vslideup.vx v1, v3, a0
+// CHECK-INST: vslideup.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x3a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 3a <unknown>
+
+vslideup.vi v1, v3, 31, v0.t
+// CHECK-INST: vslideup.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x38]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 38 <unknown>
+
+vslideup.vi v1, v3, 31
+// CHECK-INST: vslideup.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x3a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 3a <unknown>
+
+vslidedown.vx v1, v3, a0, v0.t
+// CHECK-INST: vslidedown.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x3c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 3c <unknown>
+
+vslidedown.vx v1, v3, a0
+// CHECK-INST: vslidedown.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x3e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 3e <unknown>
+
+vslidedown.vi v1, v3, 31, v0.t
+// CHECK-INST: vslidedown.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x3c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 3c <unknown>
+
+vslidedown.vi v1, v3, 31
+// CHECK-INST: vslidedown.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x3e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 3e <unknown>
+
+vslide1up.vx v1, v3, a0, v0.t
+// CHECK-INST: vslide1up.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x38]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 38 <unknown>
+
+vslide1up.vx v1, v3, a0
+// CHECK-INST: vslide1up.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x3a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 3a <unknown>
+
+vslide1down.vx v1, v3, a0, v0.t
+// CHECK-INST: vslide1down.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x3c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 3c <unknown>
+
+vslide1down.vx v1, v3, a0
+// CHECK-INST: vslide1down.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0x3e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 3e <unknown>
+
+vrgather.vv v1, v3, v2, v0.t
+// CHECK-INST: vrgather.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x30]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 30 <unknown>
+
+vrgather.vv v1, v3, v2
+// CHECK-INST: vrgather.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x32]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 32 <unknown>
+
+vrgather.vx v1, v3, a0, v0.t
+// CHECK-INST: vrgather.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x30]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 30 <unknown>
+
+vrgather.vx v1, v3, a0
+// CHECK-INST: vrgather.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x32]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 32 <unknown>
+
+vrgather.vi v1, v3, 31, v0.t
+// CHECK-INST: vrgather.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x30]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 30 <unknown>
+
+vrgather.vi v1, v3, 31
+// CHECK-INST: vrgather.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x32]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 32 <unknown>
+
+vcompress.vm v1, v3, v2
+// CHECK-INST: vcompress.vm v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x5e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 5e <unknown>
+
+vfsqrt.v v1, v3, v0.t
+// CHECK-INST: vfsqrt.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x30,0x8c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 30 8c <unknown>
+
+vfsqrt.v v1, v3
+// CHECK-INST: vfsqrt.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x30,0x8e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 30 8e <unknown>
+
+vfclass.v v1, v3, v0.t
+// CHECK-INST: vfclass.v v1, v3, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x38,0x8c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 38 8c <unknown>
+
+vfclass.v v1, v3
+// CHECK-INST: vfclass.v v1, v3
+// CHECK-ENCODING: [0xd7,0x10,0x38,0x8e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 38 8e <unknown>
+
+vfmerge.vfm v1, v3, fa0, v0
+// CHECK-INST: vfmerge.vfm v1, v3, fa0, v0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x5c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 5c <unknown>
Index: llvm/test/MC/RISCV/rvv/reduction.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/reduction.s
@@ -0,0 +1,199 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vredsum.vs v1, v3, v2, v0.t
+// CHECK-INST: vredsum.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 00 <unknown>
+
+vredsum.vs v1, v3, v2
+// CHECK-INST: vredsum.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 02 <unknown>
+
+vredmaxu.vs v1, v3, v2, v0.t
+// CHECK-INST: vredmaxu.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x18]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 18 <unknown>
+
+vredmaxu.vs v1, v3, v2
+// CHECK-INST: vredmaxu.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x1a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 1a <unknown>
+
+vredmax.vs v1, v3, v2, v0.t
+// CHECK-INST: vredmax.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 1c <unknown>
+
+vredmax.vs v1, v3, v2
+// CHECK-INST: vredmax.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 1e <unknown>
+
+vredminu.vs v1, v3, v2, v0.t
+// CHECK-INST: vredminu.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x10]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 10 <unknown>
+
+vredminu.vs v1, v3, v2
+// CHECK-INST: vredminu.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x12]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 12 <unknown>
+
+vredmin.vs v1, v3, v2, v0.t
+// CHECK-INST: vredmin.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x14]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 14 <unknown>
+
+vredmin.vs v1, v3, v2
+// CHECK-INST: vredmin.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x16]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 16 <unknown>
+
+vredand.vs v1, v3, v2, v0.t
+// CHECK-INST: vredand.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x04]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 04 <unknown>
+
+vredand.vs v1, v3, v2
+// CHECK-INST: vredand.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x06]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 06 <unknown>
+
+vredor.vs v1, v3, v2, v0.t
+// CHECK-INST: vredor.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 08 <unknown>
+
+vredor.vs v1, v3, v2
+// CHECK-INST: vredor.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 0a <unknown>
+
+vredxor.vs v1, v3, v2, v0.t
+// CHECK-INST: vredxor.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 0c <unknown>
+
+vredxor.vs v1, v3, v2
+// CHECK-INST: vredxor.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 0e <unknown>
+
+vwredsumu.vs v1, v3, v2, v0.t
+// CHECK-INST: vwredsumu.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xc0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 c0 <unknown>
+
+vwredsumu.vs v1, v3, v2
+// CHECK-INST: vwredsumu.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xc2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 c2 <unknown>
+
+vwredsum.vs v1, v3, v2, v0.t
+// CHECK-INST: vwredsum.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xc4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 c4 <unknown>
+
+vwredsum.vs v1, v3, v2
+// CHECK-INST: vwredsum.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xc6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 c6 <unknown>
+
+vfredosum.vs v1, v3, v2, v0.t
+// CHECK-INST: vfredosum.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 0c <unknown>
+
+vfredosum.vs v1, v3, v2
+// CHECK-INST: vfredosum.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 0e <unknown>
+
+vfredsum.vs v1, v3, v2, v0.t
+// CHECK-INST: vfredsum.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x04]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 04 <unknown>
+
+vfredsum.vs v1, v3, v2
+// CHECK-INST: vfredsum.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x06]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 06 <unknown>
+
+vfredmax.vs v1, v3, v2, v0.t
+// CHECK-INST: vfredmax.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 1c <unknown>
+
+vfredmax.vs v1, v3, v2
+// CHECK-INST: vfredmax.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 1e <unknown>
+
+vfredmin.vs v1, v3, v2, v0.t
+// CHECK-INST: vfredmin.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x14]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 14 <unknown>
+
+vfredmin.vs v1, v3, v2
+// CHECK-INST: vfredmin.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x16]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 16 <unknown>
+
+vfwredosum.vs v1, v3, v2, v0.t
+// CHECK-INST: vfwredosum.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xcc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 cc <unknown>
+
+vfwredosum.vs v1, v3, v2
+// CHECK-INST: vfwredosum.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xce]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 ce <unknown>
+
+vfwredsum.vs v1, v3, v2, v0.t
+// CHECK-INST: vfwredsum.vs v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xc4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 c4 <unknown>
+
+vfwredsum.vs v1, v3, v2
+// CHECK-INST: vfwredsum.vs v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xc6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 c6 <unknown>
Index: llvm/test/MC/RISCV/rvv/shift.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/shift.s
@@ -0,0 +1,259 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vsll.vv v1, v3, v2, v0.t
+// CHECK-INST: vsll.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x94]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 94 <unknown>
+
+vsll.vv v1, v3, v2
+// CHECK-INST: vsll.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x96]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 96 <unknown>
+
+vsll.vx v1, v3, a0, v0.t
+// CHECK-INST: vsll.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x94]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 94 <unknown>
+
+vsll.vx v1, v3, a0
+// CHECK-INST: vsll.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x96]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 96 <unknown>
+
+vsll.vi v1, v3, 31, v0.t
+// CHECK-INST: vsll.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x94]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 94 <unknown>
+
+vsll.vi v1, v3, 31
+// CHECK-INST: vsll.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x96]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f 96 <unknown>
+
+vsrl.vv v1, v3, v2, v0.t
+// CHECK-INST: vsrl.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xa0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 a0 <unknown>
+
+vsrl.vv v1, v3, v2
+// CHECK-INST: vsrl.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xa2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 a2 <unknown>
+
+vsrl.vx v1, v3, a0, v0.t
+// CHECK-INST: vsrl.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xa0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 a0 <unknown>
+
+vsrl.vx v1, v3, a0
+// CHECK-INST: vsrl.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xa2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 a2 <unknown>
+
+vsrl.vi v1, v3, 31, v0.t
+// CHECK-INST: vsrl.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f a0 <unknown>
+
+vsrl.vi v1, v3, 31
+// CHECK-INST: vsrl.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f a2 <unknown>
+
+vsra.vv v1, v3, v2, v0.t
+// CHECK-INST: vsra.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 a4 <unknown>
+
+vsra.vv v1, v3, v2
+// CHECK-INST: vsra.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 a6 <unknown>
+
+vsra.vx v1, v3, a0, v0.t
+// CHECK-INST: vsra.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 a4 <unknown>
+
+vsra.vx v1, v3, a0
+// CHECK-INST: vsra.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 a6 <unknown>
+
+vsra.vi v1, v3, 31, v0.t
+// CHECK-INST: vsra.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f a4 <unknown>
+
+vsra.vi v1, v3, 31
+// CHECK-INST: vsra.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f a6 <unknown>
+
+vnsrl.wv v1, v3, v2, v0.t
+// CHECK-INST: vnsrl.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xb0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 b0 <unknown>
+
+vnsrl.wv v1, v3, v2
+// CHECK-INST: vnsrl.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xb2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 b2 <unknown>
+
+vnsrl.wx v1, v3, a0, v0.t
+// CHECK-INST: vnsrl.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xb0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 b0 <unknown>
+
+vnsrl.wx v1, v3, a0
+// CHECK-INST: vnsrl.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xb2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 b2 <unknown>
+
+vnsrl.wi v1, v3, 31, v0.t
+// CHECK-INST: vnsrl.wi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb0]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f b0 <unknown>
+
+vnsrl.wi v1, v3, 31
+// CHECK-INST: vnsrl.wi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb2]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f b2 <unknown>
+
+vnsra.wv v1, v3, v2, v0.t
+// CHECK-INST: vnsra.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 b4 <unknown>
+
+vnsra.wv v1, v3, v2
+// CHECK-INST: vnsra.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 b6 <unknown>
+
+vnsra.wx v1, v3, a0, v0.t
+// CHECK-INST: vnsra.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 b4 <unknown>
+
+vnsra.wx v1, v3, a0
+// CHECK-INST: vnsra.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 b6 <unknown>
+
+vnsra.wi v1, v3, 31, v0.t
+// CHECK-INST: vnsra.wi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb4]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f b4 <unknown>
+
+vnsra.wi v1, v3, 31
+// CHECK-INST: vnsra.wi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb6]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f b6 <unknown>
+
+vssrl.vv v1, v3, v2, v0.t
+// CHECK-INST: vssrl.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xa8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 a8 <unknown>
+
+vssrl.vv v1, v3, v2
+// CHECK-INST: vssrl.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xaa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 aa <unknown>
+
+vssrl.vx v1, v3, a0, v0.t
+// CHECK-INST: vssrl.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xa8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 a8 <unknown>
+
+vssrl.vx v1, v3, a0
+// CHECK-INST: vssrl.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xaa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 aa <unknown>
+
+vssrl.vi v1, v3, 31, v0.t
+// CHECK-INST: vssrl.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f a8 <unknown>
+
+vssrl.vi v1, v3, 31
+// CHECK-INST: vssrl.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xaa]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f aa <unknown>
+
+vssra.vv v1, v3, v2, v0.t
+// CHECK-INST: vssra.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 ac <unknown>
+
+vssra.vv v1, v3, v2
+// CHECK-INST: vssra.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 ae <unknown>
+
+vssra.vx v1, v3, a0, v0.t
+// CHECK-INST: vssra.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 ac <unknown>
+
+vssra.vx v1, v3, a0
+// CHECK-INST: vssra.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 ae <unknown>
+
+vssra.vi v1, v3, 31, v0.t
+// CHECK-INST: vssra.vi v1, v3, 31, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xac]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f ac <unknown>
+
+vssra.vi v1, v3, 31
+// CHECK-INST: vssra.vi v1, v3, 31
+// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xae]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 3f ae <unknown>
Index: llvm/test/MC/RISCV/rvv/sign-injection.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/sign-injection.s
@@ -0,0 +1,79 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vfsgnj.vv v1, v3, v2, v0.t
+// CHECK-INST: vfsgnj.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x20]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 20 <unknown>
+
+vfsgnj.vv v1, v3, v2
+// CHECK-INST: vfsgnj.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x22]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 22 <unknown>
+
+vfsgnj.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfsgnj.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x20]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 20 <unknown>
+
+vfsgnj.vf v1, v3, fa0
+// CHECK-INST: vfsgnj.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x22]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 22 <unknown>
+
+vfsgnjn.vv v1, v3, v2, v0.t
+// CHECK-INST: vfsgnjn.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x24]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 24 <unknown>
+
+vfsgnjn.vv v1, v3, v2
+// CHECK-INST: vfsgnjn.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x26]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 26 <unknown>
+
+vfsgnjn.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfsgnjn.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x24]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 24 <unknown>
+
+vfsgnjn.vf v1, v3, fa0
+// CHECK-INST: vfsgnjn.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x26]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 26 <unknown>
+
+vfsgnjx.vv v1, v3, v2, v0.t
+// CHECK-INST: vfsgnjx.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x28]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 28 <unknown>
+
+vfsgnjx.vv v1, v3, v2
+// CHECK-INST: vfsgnjx.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x2a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 2a <unknown>
+
+vfsgnjx.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfsgnjx.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x28]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 28 <unknown>
+
+vfsgnjx.vf v1, v3, fa0
+// CHECK-INST: vfsgnjx.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x2a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 2a <unknown>
Index: llvm/test/MC/RISCV/rvv/snippet.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/snippet.s
@@ -0,0 +1,31 @@
+// A snippet from https://github.com/riscv/riscv-v-spec.
+//
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+
+loop:
+    vsetvli a3, a0, e16,m4  # vtype = 16-bit integer vectors
+// CHECK-INST: d7 76 65 00    vsetvli a3, a0, e16,m4
+    vlh.v v4, (a1)          # Get 16b vector
+// CHECK-INST: 07 d2 05 12    vlh.v   v4, (a1)
+    slli t1, a3, 1          # Multiply length by two bytes/element
+// CHECK-INST: 13 93 16 00    slli    t1, a3, 1
+    add a1, a1, t1          # Bump pointer
+// CHECK-INST: b3 85 65 00    add     a1, a1, t1
+    vwmul.vx v8, v4, x10    # 32b in <v8--v15>
+// CHECK-INST: 57 64 45 ee    vwmul.vx        v8, v4, a0
+
+    vsetvli x0, a0, e32,m8  # Operate on 32b values
+// CHECK-INST: 57 70 b5 00    vsetvli zero, a0, e32,m8
+    vsrl.vi v8, v8, 3
+// CHECK-INST: 57 b4 81 a2    vsrl.vi v8, v8, 3
+    vsw.v v8, (a2)          # Store vector of 32b
+// CHECK-INST: 27 64 06 02    vsw.v   v8, (a2)
+    slli t1, a3, 2          # Multiply length by four bytes/element
+// CHECK-INST: 13 93 26 00    slli    t1, a3, 2
+    add a2, a2, t1          # Bump pointer
+// CHECK-INST: 33 06 66 00    add     a2, a2, t1
+    sub a0, a0, a3          # Decrement count
+// CHECK-INST: 33 05 d5 40    sub     a0, a0, a3
+    bnez a0, loop           # Any more?
+// CHECK-INST: e3 1a 05 fc    bnez    a0, -44
Index: llvm/test/MC/RISCV/rvv/store.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -0,0 +1,199 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vsb.v v4, (a0), v0.t
+// CHECK-INST: vsb.v v4, (a0), v0.t
+// CHECK-ENCODING: [0x27,0x02,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 05 00 <unknown>
+
+vsb.v v4, (a0)
+// CHECK-INST: vsb.v v4, (a0)
+// CHECK-ENCODING: [0x27,0x02,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 05 02 <unknown>
+
+vsh.v v4, (a0), v0.t
+// CHECK-INST: vsh.v v4, (a0), v0.t
+// CHECK-ENCODING: [0x27,0x52,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 05 00 <unknown>
+
+vsh.v v4, (a0)
+// CHECK-INST: vsh.v v4, (a0)
+// CHECK-ENCODING: [0x27,0x52,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 05 02 <unknown>
+
+vsw.v v4, (a0), v0.t
+// CHECK-INST: vsw.v v4, (a0), v0.t
+// CHECK-ENCODING: [0x27,0x62,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 05 00 <unknown>
+
+vsw.v v4, (a0)
+// CHECK-INST: vsw.v v4, (a0)
+// CHECK-ENCODING: [0x27,0x62,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 05 02 <unknown>
+
+vse.v v4, (a0), v0.t
+// CHECK-INST: vse.v v4, (a0), v0.t
+// CHECK-ENCODING: [0x27,0x72,0x05,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 05 00 <unknown>
+
+vse.v v4, (a0)
+// CHECK-INST: vse.v v4, (a0)
+// CHECK-ENCODING: [0x27,0x72,0x05,0x02]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 05 02 <unknown>
+
+vssb.v v4, (a0), a1, v0.t
+// CHECK-INST: vssb.v v4, (a0), a1, v0.t
+// CHECK-ENCODING: [0x27,0x02,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 b5 08 <unknown>
+
+vssb.v v4, (a0), a1
+// CHECK-INST: vssb.v v4, (a0), a1
+// CHECK-ENCODING: [0x27,0x02,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 b5 0a <unknown>
+
+vssh.v v4, (a0), a1, v0.t
+// CHECK-INST: vssh.v v4, (a0), a1, v0.t
+// CHECK-ENCODING: [0x27,0x52,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 b5 08 <unknown>
+
+vssh.v v4, (a0), a1
+// CHECK-INST: vssh.v v4, (a0), a1
+// CHECK-ENCODING: [0x27,0x52,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 b5 0a <unknown>
+
+vssw.v v4, (a0), a1, v0.t
+// CHECK-INST: vssw.v v4, (a0), a1, v0.t
+// CHECK-ENCODING: [0x27,0x62,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 b5 08 <unknown>
+
+vssw.v v4, (a0), a1
+// CHECK-INST: vssw.v v4, (a0), a1
+// CHECK-ENCODING: [0x27,0x62,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 b5 0a <unknown>
+
+vsse.v v4, (a0), a1, v0.t
+// CHECK-INST: vsse.v v4, (a0), a1, v0.t
+// CHECK-ENCODING: [0x27,0x72,0xb5,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 b5 08 <unknown>
+
+vsse.v v4, (a0), a1
+// CHECK-INST: vsse.v v4, (a0), a1
+// CHECK-ENCODING: [0x27,0x72,0xb5,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 b5 0a <unknown>
+
+vsxb.v v4, (a0), v3, v0.t
+// CHECK-INST: vsxb.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x02,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 35 0c <unknown>
+
+vsxb.v v4, (a0), v3
+// CHECK-INST: vsxb.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x02,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 35 0e <unknown>
+
+vsxh.v v4, (a0), v3, v0.t
+// CHECK-INST: vsxh.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x52,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 35 0c <unknown>
+
+vsxh.v v4, (a0), v3
+// CHECK-INST: vsxh.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x52,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 35 0e <unknown>
+
+vsxw.v v4, (a0), v3, v0.t
+// CHECK-INST: vsxw.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x62,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 35 0c <unknown>
+
+vsxw.v v4, (a0), v3
+// CHECK-INST: vsxw.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x62,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 35 0e <unknown>
+
+vsxe.v v4, (a0), v3, v0.t
+// CHECK-INST: vsxe.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x72,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 35 0c <unknown>
+
+vsxe.v v4, (a0), v3
+// CHECK-INST: vsxe.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x72,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 35 0e <unknown>
+
+vsuxb.v v4, (a0), v3, v0.t
+// CHECK-INST: vsuxb.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x02,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 35 1c <unknown>
+
+vsuxb.v v4, (a0), v3
+// CHECK-INST: vsuxb.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x02,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 02 35 1e <unknown>
+
+vsuxh.v v4, (a0), v3, v0.t
+// CHECK-INST: vsuxh.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x52,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 35 1c <unknown>
+
+vsuxh.v v4, (a0), v3
+// CHECK-INST: vsuxh.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x52,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 52 35 1e <unknown>
+
+vsuxw.v v4, (a0), v3, v0.t
+// CHECK-INST: vsuxw.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x62,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 35 1c <unknown>
+
+vsuxw.v v4, (a0), v3
+// CHECK-INST: vsuxw.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x62,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 62 35 1e <unknown>
+
+vsuxe.v v4, (a0), v3, v0.t
+// CHECK-INST: vsuxe.v v4, (a0), v3, v0.t
+// CHECK-ENCODING: [0x27,0x72,0x35,0x1c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 35 1c <unknown>
+
+vsuxe.v v4, (a0), v3
+// CHECK-INST: vsuxe.v v4, (a0), v3
+// CHECK-ENCODING: [0x27,0x72,0x35,0x1e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 27 72 35 1e <unknown>
Index: llvm/test/MC/RISCV/rvv/sub.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/sub.s
@@ -0,0 +1,307 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vsub.vv v1, v3, v2, v0.t
+// CHECK-INST: vsub.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 08 <unknown>
+
+vsub.vv v1, v3, v2
+// CHECK-INST: vsub.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 0a <unknown>
+
+vsub.vx v1, v3, a0, v0.t
+// CHECK-INST: vsub.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 08 <unknown>
+
+vsub.vx v1, v3, a0
+// CHECK-INST: vsub.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 0a <unknown>
+
+vrsub.vx v1, v3, a0, v0.t
+// CHECK-INST: vrsub.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 0c <unknown>
+
+vrsub.vx v1, v3, a0
+// CHECK-INST: vrsub.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 0e <unknown>
+
+vrsub.vi v1, v3, 15, v0.t
+// CHECK-INST: vrsub.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x0c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 0c <unknown>
+
+vrsub.vi v1, v3, 15
+// CHECK-INST: vrsub.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x0e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 0e <unknown>
+
+vwsubu.vv v1, v3, v2, v0.t
+// CHECK-INST: vwsubu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xc8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 c8 <unknown>
+
+vwsubu.vv v1, v3, v2
+// CHECK-INST: vwsubu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xca]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ca <unknown>
+
+vwsubu.vx v1, v3, a0, v0.t
+// CHECK-INST: vwsubu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xc8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 c8 <unknown>
+
+vwsubu.vx v1, v3, a0
+// CHECK-INST: vwsubu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xca]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ca <unknown>
+
+vwsub.vv v1, v3, v2, v0.t
+// CHECK-INST: vwsub.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xcc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 cc <unknown>
+
+vwsub.vv v1, v3, v2
+// CHECK-INST: vwsub.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xce]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 ce <unknown>
+
+vwsub.vx v1, v3, a0, v0.t
+// CHECK-INST: vwsub.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xcc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 cc <unknown>
+
+vwsub.vx v1, v3, a0
+// CHECK-INST: vwsub.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xce]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 ce <unknown>
+
+vwsubu.wv v1, v3, v2, v0.t
+// CHECK-INST: vwsubu.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xd8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 d8 <unknown>
+
+vwsubu.wv v1, v3, v2
+// CHECK-INST: vwsubu.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xda]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 da <unknown>
+
+vwsubu.wx v1, v3, a0, v0.t
+// CHECK-INST: vwsubu.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xd8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 d8 <unknown>
+
+vwsubu.wx v1, v3, a0
+// CHECK-INST: vwsubu.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xda]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 da <unknown>
+
+vwsub.wv v1, v3, v2, v0.t
+// CHECK-INST: vwsub.wv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xdc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 dc <unknown>
+
+vwsub.wv v1, v3, v2
+// CHECK-INST: vwsub.wv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x20,0x31,0xde]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 20 31 de <unknown>
+
+vwsub.wx v1, v3, a0, v0.t
+// CHECK-INST: vwsub.wx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xdc]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 dc <unknown>
+
+vwsub.wx v1, v3, a0
+// CHECK-INST: vwsub.wx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x60,0x35,0xde]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 60 35 de <unknown>
+
+vsbc.vvm v1, v3, v2, v0
+// CHECK-INST: vsbc.vvm v1, v3, v2, v0
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x48]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 48 <unknown>
+
+vsbc.vxm v1, v3, a0, v0
+// CHECK-INST: vsbc.vxm v1, v3, a0, v0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x48]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 48 <unknown>
+
+vmsbc.vvm v1, v3, v2, v0
+// CHECK-INST: vmsbc.vvm v1, v3, v2, v0
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x4c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 4c <unknown>
+
+vmsbc.vxm v1, v3, a0, v0
+// CHECK-INST: vmsbc.vxm v1, v3, a0, v0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x4c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 4c <unknown>
+
+vssubu.vv v1, v3, v2, v0.t
+// CHECK-INST: vssubu.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 88 <unknown>
+
+vssubu.vv v1, v3, v2
+// CHECK-INST: vssubu.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 8a <unknown>
+
+vssubu.vx v1, v3, a0, v0.t
+// CHECK-INST: vssubu.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x88]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 88 <unknown>
+
+vssubu.vx v1, v3, a0
+// CHECK-INST: vssubu.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x8a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 8a <unknown>
+
+vssub.vv v1, v3, v2, v0.t
+// CHECK-INST: vssub.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x8c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 8c <unknown>
+
+vssub.vv v1, v3, v2
+// CHECK-INST: vssub.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x8e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 8e <unknown>
+
+vssub.vx v1, v3, a0, v0.t
+// CHECK-INST: vssub.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x8c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 8c <unknown>
+
+vssub.vx v1, v3, a0
+// CHECK-INST: vssub.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x8e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 8e <unknown>
+
+vasub.vv v1, v3, v2, v0.t
+// CHECK-INST: vasub.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x98]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 98 <unknown>
+
+vasub.vv v1, v3, v2
+// CHECK-INST: vasub.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x9a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 9a <unknown>
+
+vasub.vx v1, v3, a0, v0.t
+// CHECK-INST: vasub.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x98]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 98 <unknown>
+
+vasub.vx v1, v3, a0
+// CHECK-INST: vasub.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x9a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 9a <unknown>
+
+vfsub.vv v1, v3, v2, v0.t
+// CHECK-INST: vfsub.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 08 <unknown>
+
+vfsub.vv v1, v3, v2
+// CHECK-INST: vfsub.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 0a <unknown>
+
+vfsub.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfsub.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x08]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 08 <unknown>
+
+vfsub.vf v1, v3, fa0
+// CHECK-INST: vfsub.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x0a]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 0a <unknown>
+
+vfrsub.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfrsub.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x9c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 9c <unknown>
+
+vfrsub.vf v1, v3, fa0
+// CHECK-INST: vfrsub.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0x9e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 9e <unknown>
+
+vfwsub.vv v1, v3, v2, v0.t
+// CHECK-INST: vfwsub.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xc8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 c8 <unknown>
+
+vfwsub.vv v1, v3, v2
+// CHECK-INST: vfwsub.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x10,0x31,0xca]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 10 31 ca <unknown>
+
+vfwsub.vf v1, v3, fa0, v0.t
+// CHECK-INST: vfwsub.vf v1, v3, fa0, v0.t
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xc8]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 c8 <unknown>
+
+vfwsub.vf v1, v3, fa0
+// CHECK-INST: vfwsub.vf v1, v3, fa0
+// CHECK-ENCODING: [0xd7,0x50,0x35,0xca]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 50 35 ca <unknown>
Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vsetvli a2, a0, e32,m4
+// CHECK-INST: vsetvli a2, a0, e32,m4
+// CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 76 a5 00 <unknown>
+
+vsetvli a2, a0, e32
+// CHECK-INST: vsetvli a2, a0, e32,m1
+// CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 76 85 00 <unknown>
+
+vsetvl a2, a0, a1
+// CHECK-INST: vsetvl a2, a0, a1
+// CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: 57 76 b5 80 <unknown>
Index: llvm/test/MC/RISCV/rvv/xor.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/xor.s
@@ -0,0 +1,43 @@
+// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vxor.vv v1, v3, v2, v0.t
+// CHECK-INST: vxor.vv v1, v3, v2, v0.t
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x2c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 2c <unknown>
+
+vxor.vv v1, v3, v2
+// CHECK-INST: vxor.vv v1, v3, v2
+// CHECK-ENCODING: [0xd7,0x00,0x31,0x2e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 00 31 2e <unknown>
+
+vxor.vx v1, v3, a0, v0.t
+// CHECK-INST: vxor.vx v1, v3, a0, v0.t
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x2c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 2c <unknown>
+
+vxor.vx v1, v3, a0
+// CHECK-INST: vxor.vx v1, v3, a0
+// CHECK-ENCODING: [0xd7,0x40,0x35,0x2e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 40 35 2e <unknown>
+
+vxor.vi v1, v3, 15, v0.t
+// CHECK-INST: vxor.vi v1, v3, 15, v0.t
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x2c]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 2c <unknown>
+
+vxor.vi v1, v3, 15
+// CHECK-INST: vxor.vi v1, v3, 15
+// CHECK-ENCODING: [0xd7,0xb0,0x37,0x2e]
+// CHECK-ERROR: instruction use requires an option to be enabled
+// CHECK-UNKNOWN: d7 b0 37 2e <unknown>