Index: llvm/lib/Target/MSP430/MSP430ISelLowering.h
===================================================================
--- llvm/lib/Target/MSP430/MSP430ISelLowering.h
+++ llvm/lib/Target/MSP430/MSP430ISelLowering.h
@@ -124,6 +124,7 @@
     bool isZExtFree(EVT VT1, EVT VT2) const override;
     bool isZExtFree(SDValue Val, EVT VT2) const override;
 
+    bool isLegalICmpImmediate(int64_t) const override;
     unsigned getShiftAmountThreshold(EVT VT) const override;
 
     MachineBasicBlock *
Index: llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
===================================================================
--- llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -37,6 +37,11 @@
 
 #define DEBUG_TYPE "msp430-lower"
 
+static cl::opt<bool>MSP430NoLegalImmediate(
+  "msp430-no-legal-immediate", cl::Hidden,
+  cl::desc("Enable non legal immediates (for testing purposes only)"),
+  cl::init(false));
+
 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
                                            const MSP430Subtarget &STI)
     : TargetLowering(TM) {
@@ -357,6 +362,15 @@
 unsigned MSP430TargetLowering::getShiftAmountThreshold(EVT VT) const {
   return 2;
 }
+
+// Implemented to verify test case assertions in
+// tests/codegen/msp430/shift-amount-threshold-b.ll
+bool MSP430TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
+  if (MSP430NoLegalImmediate)
+    return Immed >= -32 && Immed < 32;
+  return TargetLowering::isLegalICmpImmediate(Immed);
+}
+
 //===----------------------------------------------------------------------===//
 //                       MSP430 Inline Assembly Support
 //===----------------------------------------------------------------------===//
Index: llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=msp430-- -msp430-no-legal-immediate=true < %s | FileCheck %s
+
+; Test case for the following transformation in TargetLowering::SimplifySetCC
+; (X & -256) == 256 -> (X >> 8) == 1
+define i16 @testSimplifySetCC_2(i16 %x) {
+; CHECK-LABEL: testSimplifySetCC_2:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    clrc
+; CHECK-NEXT:    rrc r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    cmp #1, r12
+; CHECK-NEXT:    mov r2, r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    and #1, r12
+; CHECK-NEXT:    ret
+entry:
+  %and = and i16 %x, -64
+  %cmp = icmp eq i16 %and, 64
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}
+
+; Test case for the following transformation in TargetLowering::SimplifySetCC
+; X >  0x0ffffffff -> (X >> 32) >= 1
+define i16 @testSimplifySetCC_3(i16 %x) {
+; CHECK-LABEL: testSimplifySetCC_3:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    clrc
+; CHECK-NEXT:    rrc r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    tst r12
+; CHECK-NEXT:    mov r2, r13
+; CHECK-NEXT:    rra r13
+; CHECK-NEXT:    mov #1, r12
+; CHECK-NEXT:    bic r13, r12
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp ugt i16 %x, 63
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}
+
+; Test case for the following transformation in TargetLowering::SimplifySetCC
+; X <  0x100000000 -> (X >> 32) <  1
+define i16 @testSimplifySetCC_4(i16 %x) {
+; CHECK-LABEL: testSimplifySetCC_4:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    clrc
+; CHECK-NEXT:    rrc r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    tst r12
+; CHECK-NEXT:    mov r2, r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    and #1, r12
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp ult i16 %x, 64
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}