Index: llvm/lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -274,13 +274,13 @@ // to be a src operand. The custom inserter must add a tied implicit // def and use of the super register since there seems to be no way to // add an implicit def of a virtual register in tablegen. -def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> { +class VOP_MOVREL : VOPProfile<[untyped, i32, untyped, untyped]> { let Src0RC32 = VOPDstOperand; let Src0RC64 = VOPDstOperand; let Outs = (outs); - let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0); - let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0); + let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0); + let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0); let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); @@ -306,6 +306,9 @@ let EmitDst = 1; // force vdst emission } +def VOP_MOVRELD : VOP_MOVREL; +def VOP_MOVRELSD : VOP_MOVREL; + let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in { // v_movreld_b32 is a special case because the destination output // register is really a source. It isn't actually read (but may be @@ -315,7 +318,7 @@ // so this must have an implicit def of the register added to it. defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>; defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>; -defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_NO_EXT>; +defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>; } // End Uses = [M0, EXEC] defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>; @@ -430,9 +433,8 @@ defm V_PIPEFLUSH : VOP1Inst<"v_pipeflush", VOP_NONE>; let Uses = [M0] in { - // FIXME-GFX10: Should V_MOVRELSD_2_B32 be VOP_NO_EXT? defm V_MOVRELSD_2_B32 : - VOP1Inst<"v_movrelsd_2_b32", VOP_NO_EXT>; + VOP1Inst<"v_movrelsd_2_b32", VOP_MOVRELSD>; def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> { let Constraints = "$vdst = $src1, $vdst1 = $src0"; Index: llvm/test/MC/AMDGPU/gfx10_asm_all.s =================================================================== --- llvm/test/MC/AMDGPU/gfx10_asm_all.s +++ llvm/test/MC/AMDGPU/gfx10_asm_all.s @@ -32199,6 +32199,9 @@ v_movrelsd_b32_e64 v5, v255 // GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00] +v_movrelsd_b32 v5, s1 +// GFX10-ERR: error: invalid operand for instruction + v_movrelsd_2_b32 v5, v1 // GFX10: encoding: [0x01,0x91,0x0a,0x7e] @@ -32217,6 +32220,9 @@ v_movrelsd_2_b32_e64 v5, v255 // GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00] +v_movrelsd_2_b32 v5, s1 +// GFX10-ERR: error: invalid operand for instruction + v_cvt_f16_u16_e32 v5, v1 // GFX10: encoding: [0x01,0xa1,0x0a,0x7e] Index: llvm/test/MC/AMDGPU/vop1.s =================================================================== --- llvm/test/MC/AMDGPU/vop1.s +++ llvm/test/MC/AMDGPU/vop1.s @@ -273,6 +273,10 @@ // VI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] v_movrelsd_b32_e32 v1, v2 +// NOSICI: error: invalid operand for instruction +// NOVI: error: invalid operand for instruction +v_movrelsd_b32_e32 v1, s2 + // NOSI: error: instruction not supported on this GPU // NOSI: v_log_legacy_f32 v1, v2 // CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]