diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -126,7 +126,8 @@ Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6, Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3, Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips, - Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008 + Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, + Mips::FeatureNaN2008 }; namespace { @@ -330,6 +331,9 @@ bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool reportParseError(Twine ErrorMsg); bool reportParseError(SMLoc Loc, Twine ErrorMsg); @@ -654,6 +658,10 @@ return (getSTI().getFeatureBits()[Mips::FeatureCnMips]); } + bool hasCnMipsP() const { + return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]); + } + bool inPicMode() { return IsPicEnabled; } @@ -2545,6 +2553,9 @@ case Mips::MFTHC1: case Mips::MTTHC1: case Mips::CFTC1: case Mips::CTTC1: return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SaaAddr: + case Mips::SaadAddr: + return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; } } @@ -3041,7 +3052,7 @@ TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); return false; - } else if (canUseATReg() && !RdRegIsRsReg) { + } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { unsigned ATReg = getATReg(IDLoc); // If the $rs is different from $rd or if $rs isn't specified and we @@ -3068,7 +3079,8 @@ TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); return false; - } else if (!canUseATReg() && !RdRegIsRsReg) { + } else if ((!canUseATReg() && !RdRegIsRsReg) || + (canUseATReg() && DstReg == getATReg(IDLoc))) { // Otherwise, synthesize the address in the destination register // serially: // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym) @@ -5412,6 +5424,39 @@ return false; } +bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + assert(Inst.getNumOperands() == 3 && "expected three operands"); + assert(Inst.getOperand(0).isReg() && "expected register operand kind"); + assert(Inst.getOperand(1).isReg() && "expected register operand kind"); + + warnIfNoMacro(IDLoc); + + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD; + unsigned RtReg = Inst.getOperand(0).getReg(); + unsigned BaseReg = Inst.getOperand(1).getReg(); + const MCOperand &BaseOp = Inst.getOperand(2); + + if (BaseOp.isImm()) { + int64_t ImmValue = BaseOp.getImm(); + if (ImmValue == 0) { + TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI); + return false; + } + } + + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI)) + return true; + + TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI); + return false; +} + unsigned MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) { diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -63,6 +63,8 @@ bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } + bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } + bool hasCOP3() const { // Only present in MIPS-I and MIPS-II return !hasMips32() && !hasMips3(); @@ -1357,6 +1359,14 @@ return Result; } + if (hasCnMipsP()) { + LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (isGP64()) { LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -196,6 +196,10 @@ "true", "Octeon cnMIPS Support", [FeatureMips64r2]>; +def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP", + "true", "Octeon+ cnMIPS Support", + [FeatureCnMips]>; + def FeatureUseTCCInDIV : SubtargetFeature< "use-tcc-in-div", "UseTCCInDIV", "false", @@ -245,6 +249,7 @@ def : Proc<"mips64r5", [FeatureMips64r5]>; def : Proc<"mips64r6", [FeatureMips64r6]>; def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>; +def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>; def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>; def MipsAsmParser : AsmParser { diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -586,6 +586,24 @@ ASE_CNMIPS; } +// Cavium Octeon+ cnMIPS instructions +let DecoderNamespace = "CnMipsP", + // FIXME: The lack of HasStdEnc is probably a bug + EncodingPredicates = [] in { + +class Saa: + InstSE<(outs), (ins GPR64Opnd:$rt, GPR64Opnd:$rs), + !strconcat(opstr, "\t$rt, (${rs})"), [], NoItinerary, FrmR, opstr>; + +def SAA : Saa<"saa">, SAA_FM<0x18>, ASE_CNMIPSP; +def SAAD : Saa<"saad">, SAA_FM<0x19>, ASE_CNMIPSP; + +def SaaAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), + "saa\t$rt, $addr">, ASE_CNMIPSP; +def SaadAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr), + "saad\t$rt, $addr">, ASE_CNMIPSP; +} + } /// Move between CPU and coprocessor registers diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -626,6 +626,19 @@ let Inst{5-0} = funct; } +class SAA_FM funct> : StdArch { + bits<5> rt; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0x1c; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-6} = 0; + let Inst{5-0} = funct; +} + //===----------------------------------------------------------------------===// // System calls format //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -211,6 +211,10 @@ AssemblerPredicate<"FeatureCnMips">; def NotCnMips : Predicate<"!Subtarget->hasCnMips()">, AssemblerPredicate<"!FeatureCnMips">; +def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">, + AssemblerPredicate<"FeatureCnMipsP">; +def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">, + AssemblerPredicate<"!FeatureCnMipsP">; def IsSym32 : Predicate<"Subtarget->hasSym32()">, AssemblerPredicate<"FeatureSym32">; def IsSym64 : Predicate<"!Subtarget->hasSym32()">, @@ -439,6 +443,14 @@ list ASEPredicate = [NotCnMips]; } +class ASE_CNMIPSP { + list ASEPredicate = [HasCnMipsP]; +} + +class NOT_ASE_CNMIPSP { + list ASEPredicate = [NotCnMipsP]; +} + class ASE_MIPS64_CNMIPS { list ASEPredicate = [HasMips64, HasCnMips]; } diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -720,11 +720,16 @@ CINS, CINS32, CINS64_32, CINS_i32, DMFC2_OCTEON, DMTC2_OCTEON, DPOP, EXTS, EXTS32, MTM0, MTM1, MTM2, MTP0, MTP1, MTP2, - POP, SEQ, SEQi, SNE, SNEi, V3MULU, VMM0, - VMULU)>; + POP, SEQ, SEQi, SNE, SNEi, + V3MULU, VMM0, VMULU)>; def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUL)>; +// Cavium Networks MIPS (cnMIPSP) - Octeon+, HasCnMipsP +// ================================================= + +def : InstRW<[GenericWriteALU], (instrs SAA, SAAD)>; + // FPU Pipelines // ============= diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -18,7 +18,8 @@ list UnsupportedFeatures = [HasMips3, HasMips32r6, HasMips64, HasMips64r2, HasMips64r5, HasMips64r6, IsGP64bit, IsPTR64bit, - InMicroMips, InMips16Mode, HasCnMips, + InMicroMips, InMips16Mode, + HasCnMips, HasCnMipsP, HasDSP, HasDSPR2, HasMT, HasCRC]; } diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h --- a/llvm/lib/Target/Mips/MipsSubtarget.h +++ b/llvm/lib/Target/Mips/MipsSubtarget.h @@ -111,6 +111,9 @@ // CPU supports cnMIPS (Cavium Networks Octeon CPU). bool HasCnMips; + // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU). + bool HasCnMipsP; + // isLinux - Target system is Linux. Is false we consider ELFOS for now. bool IsLinux; @@ -270,6 +273,7 @@ bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } bool hasCnMips() const { return HasCnMips; } + bool hasCnMipsP() const { return HasCnMipsP; } bool isLittle() const { return IsLittle; } bool isABICalls() const { return !NoABICalls; } diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -73,7 +73,8 @@ : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true), - IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), + IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), + HasCnMips(false), HasCnMipsP(false), HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), diff --git a/llvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt b/llvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc %s -disassemble -triple=mips64el-unknown-linux -mcpu=octeon+ \ +# RUN: | FileCheck %s + +0x00 0x00 0x76 0xca # CHECK: bbit0 $19, 22, 4 +0x28 0x48 0xc7 0x70 # CHECK: baddu $9, $6, $7 +0x00 0x00 0x0a 0xd9 # CHECK: bbit032 $8, 10, 4 +0x00 0x00 0x7f 0xe8 # CHECK: bbit1 $3, 31, 4 +0x00 0x00 0x0a 0xfb # CHECK: bbit132 $24, 10, 4 +0x72 0xec 0x29 0x71 # CHECK: cins $9, $9, 17, 29 +0xb3 0x44 0x4f 0x70 # CHECK: cins32 $15, $2, 18, 8 +0x03 0x48 0xc7 0x70 # CHECK: dmul $9, $6, $7 +0x40 0x00 0x22 0x48 # CHECK: dmfc2 $2, 64 +0x47 0x40 0xa2 0x48 # CHECK: dmtc2 $2, 16455 +0x2d 0x48 0xc0 0x70 # CHECK: dpop $9, $6 +0x7a 0x34 0xef 0x71 # CHECK: exts $15, $15, 17, 6 +0xbb 0x42 0xa4 0x71 # CHECK: exts32 $4, $13, 10, 8 +0x08 0x00 0xe0 0x71 # CHECK: mtm0 $15 +0x0c 0x00 0x00 0x72 # CHECK: mtm1 $16 +0x0d 0x00 0x20 0x72 # CHECK: mtm2 $17 +0x09 0x00 0x40 0x72 # CHECK: mtp0 $18 +0x0a 0x00 0x60 0x72 # CHECK: mtp1 $19 +0x0b 0x00 0x80 0x72 # CHECK: mtp2 $20 +0x2c 0x48 0xc0 0x70 # CHECK: pop $9, $6 +0x18 0x00 0xa2 0x70 # CHECK: saa $2, ($5) +0x19 0x00 0xa2 0x70 # CHECK: saad $2, ($5) +0x2a 0xc8 0xf8 0x72 # CHECK: seq $25, $23, $24 +0xae 0x09 0x10 0x72 # CHECK: seqi $16, $16, 38 +0x2b 0xb8 0xf4 0x72 # CHECK: sne $23, $23, $20 +0xef 0xb1 0x04 0x72 # CHECK: snei $4, $16, -313 +0x8f 0x01 0x00 0x00 # CHECK: sync 6 +0x11 0xa8 0x55 0x71 # CHECK: v3mulu $21, $10, $21 +0x10 0x18 0x70 0x72 # CHECK: vmm0 $3, $19, $16 +0x0f 0xd8 0x66 0x73 # CHECK: vmulu $27, $27, $6 diff --git a/llvm/test/MC/Disassembler/Mips/octeonp/valid.txt b/llvm/test/MC/Disassembler/Mips/octeonp/valid.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/octeonp/valid.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc %s -disassemble -triple=mips64-unknown-linux -mcpu=octeon+ \ +# RUN: | FileCheck %s + +0xca 0x76 0x00 0x00 # CHECK: bbit0 $19, 22, 4 +0x70 0xc7 0x48 0x28 # CHECK: baddu $9, $6, $7 +0xd9 0x0a 0x00 0x00 # CHECK: bbit032 $8, 10, 4 +0xe8 0x7f 0x00 0x00 # CHECK: bbit1 $3, 31, 4 +0xfb 0x0a 0x00 0x00 # CHECK: bbit132 $24, 10, 4 +0x71 0x29 0xec 0x72 # CHECK: cins $9, $9, 17, 29 +0x70 0x4f 0x44 0xb3 # CHECK: cins32 $15, $2, 18, 8 +0x70 0xc7 0x48 0x03 # CHECK: dmul $9, $6, $7 +0x48 0x22 0x00 0x40 # CHECK: dmfc2 $2, 64 +0x48 0xa2 0x40 0x47 # CHECK: dmtc2 $2, 16455 +0x70 0xc0 0x48 0x2d # CHECK: dpop $9, $6 +0x71 0xef 0x34 0x7a # CHECK: exts $15, $15, 17, 6 +0x71 0xa4 0x42 0xbb # CHECK: exts32 $4, $13, 10, 8 +0x71 0xe0 0x00 0x08 # CHECK: mtm0 $15 +0x72 0x00 0x00 0x0c # CHECK: mtm1 $16 +0x72 0x20 0x00 0x0d # CHECK: mtm2 $17 +0x72 0x40 0x00 0x09 # CHECK: mtp0 $18 +0x72 0x60 0x00 0x0a # CHECK: mtp1 $19 +0x72 0x80 0x00 0x0b # CHECK: mtp2 $20 +0x70 0xc0 0x48 0x2c # CHECK: pop $9, $6 +0x70 0xa2 0x00 0x18 # CHECK: saa $2, ($5) +0x70 0xa2 0x00 0x19 # CHECK: saad $2, ($5) +0x72 0xf8 0xc8 0x2a # CHECK: seq $25, $23, $24 +0x72 0x10 0x09 0xae # CHECK: seqi $16, $16, 38 +0x72 0xf4 0xb8 0x2b # CHECK: sne $23, $23, $20 +0x72 0x04 0xb1 0xef # CHECK: snei $4, $16, -313 +0x00 0x00 0x01 0x8f # CHECK: sync 6 +0x71 0x55 0xa8 0x11 # CHECK: v3mulu $21, $10, $21 +0x72 0x70 0x18 0x10 # CHECK: vmm0 $3, $19, $16 +0x73 0x66 0xd8 0x0f # CHECK: vmulu $27, $27, $6 diff --git a/llvm/test/MC/Mips/cnmipsp/invalid.s b/llvm/test/MC/Mips/cnmipsp/invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Mips/cnmipsp/invalid.s @@ -0,0 +1,7 @@ +# Instructions that are invalid. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=octeon+ 2>%t1 +# RUN: FileCheck %s < %t1 + +saa $2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +saa $2, $5, $6 # CHECK: :[[@LINE]]:11: error: unexpected token in argument list diff --git a/llvm/test/MC/Mips/cnmipsp/valid.s b/llvm/test/MC/Mips/cnmipsp/valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Mips/cnmipsp/valid.s @@ -0,0 +1,123 @@ +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon+ \ +# RUN: | FileCheck %s + +# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28] +# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28] +# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28] +# CHECK: bbit0 $19, 22, foo # encoding: [0xca,0x76,A,A] +# CHECK: bbit032 $fp, 11, foo # encoding: [0xdb,0xcb,A,A] +# CHECK: bbit032 $8, 10, foo # encoding: [0xd9,0x0a,A,A] +# CHECK: bbit1 $3, 31, foo # encoding: [0xe8,0x7f,A,A] +# CHECK: bbit132 $24, 10, foo # encoding: [0xfb,0x0a,A,A] +# CHECK: bbit132 $14, 14, foo # encoding: [0xf9,0xce,A,A] +# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2] +# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72] +# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3] +# CHECK: cins32 $22, $22, 9, 22 # encoding: [0x72,0xd6,0xb2,0x73] +# CHECK: cins32 $24, $ra, 0, 31 # encoding: [0x73,0xf8,0xf8,0x33] +# CHECK: cins32 $15, $15, 5, 5 # encoding: [0x71,0xef,0x29,0x73] +# CHECK: dmtc2 $2, 16455 # encoding: [0x48,0xa2,0x40,0x47] +# CHECK: dmfc2 $2, 64 # encoding: [0x48,0x22,0x00,0x40] +# CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03] +# CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03] +# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03] +# CHECK: dmul $21, $21, $25 # encoding: [0x72,0xb9,0xa8,0x03] +# CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d] +# CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d] +# CHECK: dpop $12, $12 # encoding: [0x71,0x80,0x60,0x2d] +# CHECK: exts $4, $25, 27, 15 # encoding: [0x73,0x24,0x7e,0xfa] +# CHECK: exts $15, $15, 17, 6 # encoding: [0x71,0xef,0x34,0x7a] +# CHECK: exts32 $4, $13, 10, 8 # encoding: [0x71,0xa4,0x42,0xbb] +# CHECK: exts32 $15, $15, 11, 20 # encoding: [0x71,0xef,0xa2,0xfb] +# CHECK: exts32 $7, $4, 22, 9 # encoding: [0x70,0x87,0x4d,0xbb] +# CHECK: exts32 $25, $25, 5, 25 # encoding: [0x73,0x39,0xc9,0x7b] +# CHECK: mtm0 $15 # encoding: [0x71,0xe0,0x00,0x08] +# CHECK: mtm1 $16 # encoding: [0x72,0x00,0x00,0x0c] +# CHECK: mtm2 $17 # encoding: [0x72,0x20,0x00,0x0d] +# CHECK: mtp0 $18 # encoding: [0x72,0x40,0x00,0x09] +# CHECK: mtp1 $19 # encoding: [0x72,0x60,0x00,0x0a] +# CHECK: mtp2 $20 # encoding: [0x72,0x80,0x00,0x0b] +# CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c] +# CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c] +# CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c] +# CHECK: saa $2, ($5) # encoding: [0x70,0xa2,0x00,0x18] +# CHECK: saad $2, ($5) # encoding: [0x70,0xa2,0x00,0x19] +# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a] +# CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a] +# CHECK: seqi $17, $15, -512 # encoding: [0x71,0xf1,0x80,0x2e] +# CHECK: seqi $16, $16, 38 # encoding: [0x72,0x10,0x09,0xae] +# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b] +# CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b] +# CHECK: snei $4, $16, -313 # encoding: [0x72,0x04,0xb1,0xef] +# CHECK: snei $26, $26, 511 # encoding: [0x73,0x5a,0x7f,0xef] +# CHECK: sync 2 # encoding: [0x00,0x00,0x00,0x8f] +# CHECK: sync 6 # encoding: [0x00,0x00,0x01,0x8f] +# CHECK: sync 4 # encoding: [0x00,0x00,0x01,0x0f] +# CHECK: sync 5 # encoding: [0x00,0x00,0x01,0x4f] +# CHECK: v3mulu $21, $10, $21 # encoding: [0x71,0x55,0xa8,0x11] +# CHECK: v3mulu $20, $20, $10 # encoding: [0x72,0x8a,0xa0,0x11] +# CHECK: vmm0 $3, $19, $16 # encoding: [0x72,0x70,0x18,0x10] +# CHECK: vmm0 $ra, $ra, $9 # encoding: [0x73,0xe9,0xf8,0x10] +# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f] +# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f] + +foo: + baddu $9, $6, $7 + baddu $17, $18, $19 + baddu $2, $3 + bbit0 $19, 22, foo + bbit032 $30, 11, foo + bbit0 $8, 42, foo + bbit1 $3, 31, foo + bbit132 $24, 10, foo + bbit1 $14, 46, foo + cins $25, $10, 22, 2 + cins $9, 17, 29 + cins32 $15, $2, 18, 8 + cins32 $22, 9, 22 + cins $24, $31, 32, 31 + cins $15, 37, 5 + dmtc2 $2, 0x4047 + dmfc2 $2, 0x0040 + dmul $9, $6, $7 + dmul $19, $24, $25 + dmul $9, $6 + dmul $21, $25 + dpop $9, $6 + dpop $15, $22 + dpop $12 + exts $4, $25, 27, 15 + exts $15, 17, 6 + exts32 $4, $13, 10, 8 + exts32 $15, 11, 20 + exts $7, $4, 54, 9 + exts $25, 37, 25 + mtm0 $15 + mtm1 $16 + mtm2 $17 + mtp0 $18 + mtp1 $19 + mtp2 $20 + pop $9, $6 + pop $8, $19 + pop $2 + saa $2, ($5) + saad $2, ($5) + seq $25, $23, $24 + seq $6, $24 + seqi $17, $15, -512 + seqi $16, 38 + sne $25, $23, $24 + sne $23, $20 + snei $4, $16, -313 + snei $26, 511 + synciobdma + syncs + syncw + syncws + v3mulu $21, $10, $21 + v3mulu $20, $10 + vmm0 $3, $19, $16 + vmm0 $31, $9 + vmulu $29, $10, $17 + vmulu $27, $6 diff --git a/llvm/test/MC/Mips/elf_eflags.s b/llvm/test/MC/Mips/elf_eflags.s --- a/llvm/test/MC/Mips/elf_eflags.s +++ b/llvm/test/MC/Mips/elf_eflags.s @@ -193,7 +193,13 @@ # MIPS64EL-MIPS64-NAN2008-PIC: Flags [ (0x60000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=octeon -target-abi n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-OCTEON %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux \ +# RUN: -mcpu=octeon+ -target-abi n64 %s -o - \ +# RUN: | llvm-readobj -h | FileCheck --check-prefix=MIPSEL-OCTEON %s # MIPSEL-OCTEON: Flags [ (0x808B0004) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -position-independent -mcpu=octeon -target-abi n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-OCTEON-PIC %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux \ +# RUN: -position-independent -mcpu=octeon+ -target-abi n64 %s -o - \ +# RUN: | llvm-readobj -h | FileCheck --check-prefix=MIPSEL-OCTEON-PIC %s # MIPSEL-OCTEON-PIC: Flags [ (0x808B0006) diff --git a/llvm/test/MC/Mips/elf_header.s b/llvm/test/MC/Mips/elf_header.s --- a/llvm/test/MC/Mips/elf_header.s +++ b/llvm/test/MC/Mips/elf_header.s @@ -86,6 +86,10 @@ # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r6 %s -o - | llvm-readobj -h | FileCheck --check-prefixes=ALL,ELF64,LE,N64,NAN2008,MIPS64R6 %s # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=octeon -target-abi=n64 %s -o - | llvm-readobj -h | FileCheck --check-prefixes=ALL,ELF64,LE,N64,NAN1985,OCTEON %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux \ +# RUN: -mcpu=octeon+ -target-abi=n64 %s -o - \ +# RUN: | llvm-readobj -h \ +# RUN: | FileCheck --check-prefixes=ALL,ELF64,LE,N64,NAN1985,OCTEON %s # ALL: ElfHeader { # ALL-NEXT: Ident { diff --git a/llvm/test/MC/Mips/macro-saa.s b/llvm/test/MC/Mips/macro-saa.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Mips/macro-saa.s @@ -0,0 +1,32 @@ +# RUN: llvm-mc -triple=mips -show-encoding -mcpu=octeon+ %s \ +# RUN: | FileCheck -check-prefix=MIPS32 %s +# RUN: llvm-mc -triple=mips64 -show-encoding -mcpu=octeon+ %s \ +# RUN: | FileCheck -check-prefix=MIPS64 %s + +saa $2, 8($5) + +# MIPS32: addiu $1, $5, 8 # encoding: [0x24,0xa1,0x00,0x08] +# MIPS32-NEXT: saa $2, ($1) # encoding: [0x70,0x22,0x00,0x18] + +# MIPS64: daddiu $1, $5, 8 # encoding: [0x64,0xa1,0x00,0x08] +# MIPS64-NEXT: saa $2, ($1) # encoding: [0x70,0x22,0x00,0x18] + +saa $2, foo + +# MIPS32: lui $1, %hi(foo) # encoding: [0x3c,0x01,A,A] +# MIPS32-NEXT: # fixup A - offset: 0, value: %hi(foo), kind: fixup_Mips_HI16 +# MIPS32-NEXT: addiu $1, $1, %lo(foo) # encoding: [0x24,0x21,A,A] +# MIPS32-NEXT: # fixup A - offset: 0, value: %lo(foo), kind: fixup_Mips_LO16 +# MIPS32-NEXT: saa $2, ($1) # encoding: [0x70,0x22,0x00,0x18] + +# MIPS64: lui $1, %highest(foo) # encoding: [0x3c,0x01,A,A] +# MIPS64-NEXT: # fixup A - offset: 0, value: %highest(foo), kind: fixup_Mips_HIGHEST +# MIPS64-NEXT: daddiu $1, $1, %higher(foo) # encoding: [0x64,0x21,A,A] +# MIPS64-NEXT: # fixup A - offset: 0, value: %higher(foo), kind: fixup_Mips_HIGHER +# MIPS64-NEXT: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38] +# MIPS64-NEXT: daddiu $1, $1, %hi(foo) # encoding: [0x64,0x21,A,A] +# MIPS64-NEXT: # fixup A - offset: 0, value: %hi(foo), kind: fixup_Mips_HI16 +# MIPS64-NEXT: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38] +# MIPS64-NEXT: daddiu $1, $1, %lo(foo) # encoding: [0x64,0x21,A,A] +# MIPS64-NEXT: # fixup A - offset: 0, value: %lo(foo), kind: fixup_Mips_LO16 +# MIPS64-NEXT: saa $2, ($1) # encoding: [0x70,0x22,0x00,0x18]