Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -22,6 +22,7 @@
 
 namespace llvm {
 class PPCTargetMachine;
+extern cl::opt<bool> DisableNonVolatileCR;
 
 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
   unsigned Reg = 0;
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -75,6 +75,11 @@
                            "spill on ppc"),
                   cl::Hidden, cl::init(100));
 
+cl::opt<bool>
+llvm::DisableNonVolatileCR("ppc-disable-non-volatile-cr",
+                           cl::desc("Disable non-volatile CR/CR bit"),
+                           cl::init(false), cl::Hidden);
+
 static unsigned offsetMinAlignForOpcode(unsigned OpC);
 
 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -363,11 +363,20 @@
        CR1LT, CR1GT, CR1EQ, CR1UN,
        CR0LT, CR0GT, CR0EQ, CR0UN)> {
   let Size = 32;
+  let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT, CR3EQ, CR3UN, CR4LT, CR4GT, CR4EQ, CR4UN)];
+  let AltOrderSelect = [{
+    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() && DisableNonVolatileCR;
+  }];
 }
 
-def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
-                                                CR7, CR2, CR3, CR4)>;
-
+def CRRC : RegisterClass<"PPC", [i32], 32,
+  (add CR0, CR1, CR5, CR6,
+       CR7, CR2, CR3, CR4)> {
+  let AltOrders = [(sub CRRC, CR2, CR3, CR4)];
+  let AltOrderSelect = [{
+    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() && DisableNonVolatileCR;
+  }];
+}
 // The CTR registers are not allocatable because they're used by the
 // decrement-and-branch instructions, and thus need to stay live across
 // multiple basic blocks.
Index: llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll
@@ -0,0 +1,47 @@
+; Note: Test option to disable use of non-volatile CR to avoid CR spilling in prologue.
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-disable-non-volatile-cr\
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck --check-prefix=CHECK-DISABLE %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu\
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck --check-prefix=CHECK-ENABLE %s
+
+; Function Attrs: nounwind
+define dso_local signext i32 @DisableNonVolatileCR(i32 signext %a, i32 signext %b) {
+; CHECK-DISABLE-LABEL: DisableNonVolatileCR:
+; CHECK-DISABLE:       # %bb.0: # %entry
+; CHECK-DISABLE-NOT:    mfocrf [[REG1:r[0-9]+]]
+; CHECK-DISABLE-NOT:    stw [[REG1]]
+; CHECK-DISABLE:        stdu r1
+; CHECK-DISABLE-DAG:    mfocrf [[REG2:r[0-9]+]]
+; CHECK-DISABLE-DAG:    stw [[REG2]]
+; CHECK-DISABLE:        # %bb.1: # %if.then
+;
+; CHECK-ENABLE-LABEL: DisableNonVolatileCR:
+; CHECK-ENABLE:       # %bb.0: # %entry
+; CHECK-ENABLE-DAG:    mfocrf [[REG1:r[0-9]+]]
+; CHECK-ENABLE-DAG:    stw [[REG1]]
+; CHECK-ENABLE:        stdu r1
+; CHECK-ENABLE-NOT:    mfocrf [[REG2:r[0-9]+]]
+; CHECK-ENABLE-NOT:    stw [[REG2]]
+; CHECK-ENABLE:        # %bb.1: # %if.then
+
+entry:
+  %cmp = icmp slt i32 %a, %b
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @fa to void ()*)() #2
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @fb to void ()*)() #2
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %conv = zext i1 %cmp to i32
+  %call = tail call signext i32 @callee(i32 signext %conv) #2
+  ret i32 %call
+}
+
+declare void @fa(...)
+declare void @fb(...)
+declare signext i32 @callee(i32 signext)