Index: llvm/lib/Target/AMDGPU/AMDGPUInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -77,18 +77,25 @@ def TruePredicate : Predicate<"">; +class PredConcat lst, Predicate pred> { + list ret = + !foldl([pred], lst, acc, cur, + !listconcat(acc, !if(!eq(!cast(cur),!cast(pred)), + [], [cur]))); +} + class PredicateControl { Predicate SubtargetPredicate = TruePredicate; - list AssemblerPredicates = []; Predicate AssemblerPredicate = TruePredicate; Predicate WaveSizePredicate = TruePredicate; list OtherPredicates = []; - list Predicates = !listconcat([SubtargetPredicate, - AssemblerPredicate, - WaveSizePredicate], - AssemblerPredicates, - OtherPredicates); + list Predicates = PredConcat< + PredConcat.ret, + AssemblerPredicate>.ret, + WaveSizePredicate>.ret; } + class AMDGPUPat : Pat, PredicateControl; Index: llvm/lib/Target/AMDGPU/DSInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/DSInstructions.td +++ llvm/lib/Target/AMDGPU/DSInstructions.td @@ -1075,7 +1075,7 @@ class DS_Real_vi op, DS_Pseudo ds> : DS_Real , SIMCInstr { - let AssemblerPredicates = [isGFX8GFX9]; + let AssemblerPredicate = isGFX8GFX9; let DecoderNamespace = "GFX8"; // encoding Index: llvm/lib/Target/AMDGPU/MIMGInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -183,7 +183,7 @@ class MIMG_gfx6789 op, dag outs, string dns = ""> : MIMG, MIMGe_gfx6789 { let SubtargetPredicate = isGFX6GFX7GFX8GFX9; - let AssemblerPredicates = [isGFX6GFX7GFX8GFX9]; + let AssemblerPredicate = isGFX6GFX7GFX8GFX9; let MIMGEncoding = MIMGEncGfx6; @@ -194,7 +194,7 @@ class MIMG_gfx10 : MIMG, MIMGe_gfx10 { let SubtargetPredicate = isGFX10Plus; - let AssemblerPredicates = [isGFX10Plus]; + let AssemblerPredicate = isGFX10Plus; let MIMGEncoding = MIMGEncGfx10Default; @@ -207,7 +207,7 @@ class MIMG_nsa_gfx10 : MIMG, MIMGe_gfx10 { let SubtargetPredicate = isGFX10Plus; - let AssemblerPredicates = [isGFX10Plus]; + let AssemblerPredicate = isGFX10Plus; let MIMGEncoding = MIMGEncGfx10NSA; @@ -416,13 +416,13 @@ RegisterClass addr_rc, bit enableDasm = 0> : MIMG_Atomic_gfx6789_base { - let AssemblerPredicates = [isGFX6GFX7]; + let AssemblerPredicate = isGFX6GFX7; } class MIMG_Atomic_vi : MIMG_Atomic_gfx6789_base { - let AssemblerPredicates = [isGFX8GFX9]; + let AssemblerPredicate = isGFX8GFX9; let MIMGEncoding = MIMGEncGfx8; } Index: llvm/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1381,7 +1381,7 @@ def _si : EXP_Helper, SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>, EXPe { - let AssemblerPredicates = [isGFX6GFX7]; + let AssemblerPredicate = isGFX6GFX7; let DecoderNamespace = "GFX6GFX7"; let DisableDecoder = DisableSIDecoder; } @@ -1389,7 +1389,7 @@ def _vi : EXP_Helper, SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>, EXPe_vi { - let AssemblerPredicates = [isGFX8GFX9]; + let AssemblerPredicate = isGFX8GFX9; let DecoderNamespace = "GFX8"; let DisableDecoder = DisableVIDecoder; } @@ -1397,7 +1397,7 @@ def _gfx10 : EXP_Helper, SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.GFX10>, EXPe { - let AssemblerPredicates = [isGFX10Plus]; + let AssemblerPredicate = isGFX10Plus; let DecoderNamespace = "GFX10"; let DisableDecoder = DisableSIDecoder; } Index: llvm/lib/Target/AMDGPU/SMInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/SMInstructions.td +++ llvm/lib/Target/AMDGPU/SMInstructions.td @@ -417,7 +417,7 @@ , SIMCInstr , Enc32 { - let AssemblerPredicates = [isGFX6GFX7]; + let AssemblerPredicate = isGFX6GFX7; let DecoderNamespace = "GFX6GFX7"; let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?); @@ -471,7 +471,7 @@ , Enc64 { bit glc; - let AssemblerPredicates = [isGFX8GFX9]; + let AssemblerPredicate = isGFX8GFX9; let DecoderNamespace = "GFX8"; let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?); @@ -660,7 +660,7 @@ SM_Real, Enc64 { - let AssemblerPredicates = [isGFX7Only]; + let AssemblerPredicate = isGFX7Only; let DecoderNamespace = "GFX7"; let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc, DLC:$dlc); @@ -697,7 +697,7 @@ , SIMCInstr , Enc32 { - let AssemblerPredicates = [isGFX7Only]; + let AssemblerPredicate = isGFX7Only; let DecoderNamespace = "GFX7"; let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?); @@ -835,7 +835,7 @@ bit glc; bit dlc; - let AssemblerPredicates = [isGFX10Plus]; + let AssemblerPredicate = isGFX10Plus; let DecoderNamespace = "GFX10"; let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?); Index: llvm/lib/Target/AMDGPU/SOPInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/SOPInstructions.td +++ llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1503,7 +1503,7 @@ class Select_vi : SIMCInstr { - list AssemblerPredicates = [isGFX8GFX9]; + Predicate AssemblerPredicate = isGFX8GFX9; string DecoderNamespace = "GFX8"; } Index: llvm/lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -699,7 +699,7 @@ } multiclass VOP1Only_Real_vi op> { - let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { + let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { def _vi : VOP1_Real(NAME), SIEncodingFamily.VI>, VOP1e(NAME).Pfl>; @@ -707,7 +707,7 @@ } multiclass VOP1_Real_e32e64_vi op> { - let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { + let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { def _e32_vi : VOP1_Real(NAME#"_e32"), SIEncodingFamily.VI>, VOP1e(NAME#"_e32").Pfl>; @@ -899,7 +899,7 @@ //===----------------------------------------------------------------------===// multiclass VOP1_Real_gfx9 op> { - let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in { + let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { defm NAME : VOP1_Real_e32e64_vi ; } Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -1282,7 +1282,7 @@ // GFX8, GFX9 (VI). //===----------------------------------------------------------------------===// -let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { +let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { multiclass VOP2_Real_MADK_vi op> { def _vi : VOP2_Real(NAME), SIEncodingFamily.VI>, @@ -1316,7 +1316,7 @@ VOP2_Real_e32_vi, VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>; -} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" +} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" multiclass VOP2_SDWA_Real op> { foreach _ = BoolToList(NAME#"_e32").Pfl.HasExtSDWA>.ret in @@ -1332,7 +1332,7 @@ VOP2_SDWA9Ae (NAME#"_sdwa").Pfl>; } -let AssemblerPredicates = [isGFX8Only] in { +let AssemblerPredicate = isGFX8Only in { multiclass VOP2be_Real_e32e64_vi_only op, string OpName, string AsmName> { def _e32_vi : @@ -1366,7 +1366,7 @@ } } -let AssemblerPredicates = [isGFX9Only] in { +let AssemblerPredicate = isGFX9Only in { multiclass VOP2be_Real_e32e64_gfx9 op, string OpName, string AsmName> { def _e32_gfx9 : @@ -1424,7 +1424,7 @@ } } -} // AssemblerPredicates = [isGFX9Only] +} // AssemblerPredicate = isGFX9Only multiclass VOP2_Real_e32e64_vi op> : Base_VOP2_Real_e32e64_vi, VOP2_SDWA_Real, VOP2_SDWA9_Real { Index: llvm/lib/Target/AMDGPU/VOP3Instructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -927,7 +927,7 @@ // GFX8, GFX9 (VI). //===----------------------------------------------------------------------===// -let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { +let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { multiclass VOP3_Real_vi op> { def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>, @@ -949,9 +949,9 @@ VOP3Interp_vi (NAME).Pfl>; } -} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" +} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" -let AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" in { +let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { multiclass VOP3_F16_Real_vi op> { def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>, @@ -963,9 +963,9 @@ VOP3Interp_vi (NAME).Pfl>; } -} // End AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" +} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" -let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in { +let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { multiclass VOP3_F16_Real_gfx9 op, string OpName, string AsmName> { def _gfx9 : VOP3_Real(OpName), SIEncodingFamily.GFX9>, @@ -999,7 +999,7 @@ } } -} // End AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" +} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; Index: llvm/lib/Target/AMDGPU/VOP3PInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -404,7 +404,7 @@ multiclass VOP3P_Real_vi op> { def _vi : VOP3P_Real(NAME), SIEncodingFamily.VI>, VOP3Pe (NAME).Pfl> { - let AssemblerPredicates = [HasVOP3PInsts]; + let AssemblerPredicate = HasVOP3PInsts; let DecoderNamespace = "GFX8"; } } @@ -412,7 +412,7 @@ multiclass VOP3P_Real_MAI op> { def _vi : VOP3P_Real(NAME), SIEncodingFamily.VI>, VOP3Pe_MAI (NAME).Pfl> { - let AssemblerPredicates = [HasMAIInsts]; + let AssemblerPredicate = HasMAIInsts; let DecoderNamespace = "GFX8"; } } Index: llvm/lib/Target/AMDGPU/VOPCInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -1218,7 +1218,7 @@ //===----------------------------------------------------------------------===// multiclass VOPC_Real_vi op> { - let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { + let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { def _e32_vi : VOPC_Real(NAME#"_e32"), SIEncodingFamily.VI>, VOPCe;