diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4435,6 +4435,9 @@
     unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
                       RHSKnown.countMinTrailingZeros();
     Known.Zero.setLowBits(std::min(TrailZ, 32u));
+    // Skip extra check if all bits are known zeros.
+    if (TrailZ >= 32)
+      break;
 
     // Truncate to 24 bits.
     LHSKnown = LHSKnown.trunc(24);
diff --git a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
--- a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
@@ -157,3 +157,14 @@
   %mul2 = mul i32 %mul0, %mul1
   ret i32 %mul2
 }
+
+; GFX9-LABEL: known_bits_mul24:
+; GFX9: v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    s_setpc_b64
+define i32 @known_bits_mul24() {
+  %r0 = call i32 @llvm.amdgcn.mul.i24(i32 0, i32 -7)
+  %r1 = shl i32 %r0, 2
+  ret i32 %r1
+}
+
+declare i32 @llvm.amdgcn.mul.i24(i32, i32)