diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -280,54 +280,11 @@
     }
   }
 
-  if (hasFP(MF)) {
-    // To find the instruction restoring FP from stack.
-    for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
-      if (I->mayLoad() && I->getOperand(0).isReg()) {
-        Register DestReg = I->getOperand(0).getReg();
-        if (DestReg == FPReg) {
-          // If there is frame pointer, after restoring $fp registers, we
-          // need adjust CFA back to the correct sp-based offset.
-          // Emit ".cfi_def_cfa $sp, CFAOffset"
-          uint64_t CFAOffset =
-              FirstSPAdjustAmount
-                  ? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
-                  : -FPOffset;
-          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
-              nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
-          BuildMI(MBB, std::next(I), DL,
-                  TII->get(TargetOpcode::CFI_INSTRUCTION))
-              .addCFIIndex(CFIIndex);
-          break;
-        }
-      }
-    }
-  }
-
-  // Add CFI directives for callee-saved registers.
-  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto &Entry : CSI) {
-    Register Reg = Entry.getReg();
-    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-        nullptr, RI->getDwarfRegNum(Reg, true)));
-    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-        .addCFIIndex(CFIIndex);
-  }
-
   if (FirstSPAdjustAmount)
     StackSize = FirstSPAdjustAmount;
 
   // Deallocate stack
   adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
-
-  // After restoring $sp, we need to adjust CFA to $(sp + 0)
-  // Emit ".cfi_def_cfa_offset 0"
-  unsigned CFIIndex =
-      MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
-  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-      .addCFIIndex(CFIIndex);
 }
 
 int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
diff --git a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll
--- a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll
+++ b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll
@@ -40,11 +40,7 @@
 ; RV32I-NEXT:    lw s1, 4(sp)
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB0_4: # %lpad
 ; RV32I-NEXT:  .Ltmp4:
@@ -81,11 +77,7 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    ld s0, 16(sp)
 ; RV64I-NEXT:    ld ra, 24(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
 ; RV64I-NEXT:    addi sp, sp, 32
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB0_4: # %lpad
 ; RV64I-NEXT:  .Ltmp4:
@@ -119,12 +111,10 @@
 define internal void @callee(i1* %p) {
 ; RV32I-LABEL: callee:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: callee:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   ret void
 }
diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll
--- a/llvm/test/CodeGen/RISCV/frame-info.ll
+++ b/llvm/test/CodeGen/RISCV/frame-info.ll
@@ -7,12 +7,10 @@
 define void @trivial() {
 ; RV32-LABEL: trivial:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: trivial:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV32-WITHFP-LABEL: trivial:
@@ -26,12 +24,8 @@
 ; RV32-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp)
-; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp)
-; RV32-WITHFP-NEXT:    .cfi_restore ra
-; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
-; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    ret
   ret void
 }
@@ -54,12 +48,8 @@
 ; RV32-NEXT:    call baz
 ; RV32-NEXT:    addi sp, s0, -16
 ; RV32-NEXT:    lw s0, 8(sp)
-; RV32-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-NEXT:    lw ra, 12(sp)
-; RV32-NEXT:    .cfi_restore ra
-; RV32-NEXT:    .cfi_restore s0
 ; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stack_alloc:
@@ -84,12 +74,8 @@
 ; RV64-NEXT:    call baz
 ; RV64-NEXT:    addi sp, s0, -16
 ; RV64-NEXT:    ld s0, 0(sp)
-; RV64-NEXT:    .cfi_def_cfa sp, 16
 ; RV64-NEXT:    ld ra, 8(sp)
-; RV64-NEXT:    .cfi_restore ra
-; RV64-NEXT:    .cfi_restore s0
 ; RV64-NEXT:    addi sp, sp, 16
-; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV32-WITHFP-LABEL: stack_alloc:
@@ -109,12 +95,8 @@
 ; RV32-WITHFP-NEXT:    call baz
 ; RV32-WITHFP-NEXT:    addi sp, s0, -16
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp)
-; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp)
-; RV32-WITHFP-NEXT:    .cfi_restore ra
-; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
-; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    ret
 entry:
   %0 = alloca i8, i32 %size, align 16
@@ -122,8 +104,6 @@
   ret void
 }
 
-; TODO: fix use of .cfi_restore with wrong CFAs
-
 define void @branch_and_tail_call(i1 %a) {
 ; RV32-LABEL: branch_and_tail_call:
 ; RV32:       # %bb.0:
@@ -135,16 +115,12 @@
 ; RV32-NEXT:    beqz a0, .LBB2_2
 ; RV32-NEXT:  # %bb.1: # %blue_pill
 ; RV32-NEXT:    lw ra, 12(sp)
-; RV32-NEXT:    .cfi_restore ra
 ; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    tail foo
 ; RV32-NEXT:  .LBB2_2: # %red_pill
 ; RV32-NEXT:    call bar
 ; RV32-NEXT:    lw ra, 12(sp)
-; RV32-NEXT:    .cfi_restore ra
 ; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: branch_and_tail_call:
@@ -157,16 +133,12 @@
 ; RV64-NEXT:    beqz a0, .LBB2_2
 ; RV64-NEXT:  # %bb.1: # %blue_pill
 ; RV64-NEXT:    ld ra, 8(sp)
-; RV64-NEXT:    .cfi_restore ra
 ; RV64-NEXT:    addi sp, sp, 16
-; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    tail foo
 ; RV64-NEXT:  .LBB2_2: # %red_pill
 ; RV64-NEXT:    call bar
 ; RV64-NEXT:    ld ra, 8(sp)
-; RV64-NEXT:    .cfi_restore ra
 ; RV64-NEXT:    addi sp, sp, 16
-; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV32-WITHFP-LABEL: branch_and_tail_call:
@@ -183,22 +155,14 @@
 ; RV32-WITHFP-NEXT:    beqz a0, .LBB2_2
 ; RV32-WITHFP-NEXT:  # %bb.1: # %blue_pill
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp)
-; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp)
-; RV32-WITHFP-NEXT:    .cfi_restore ra
-; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
-; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    tail foo
 ; RV32-WITHFP-NEXT:  .LBB2_2: # %red_pill
 ; RV32-WITHFP-NEXT:    call bar
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp)
-; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp)
-; RV32-WITHFP-NEXT:    .cfi_restore ra
-; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
-; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    ret
   br i1 %a, label %blue_pill, label %red_pill
 blue_pill:
diff --git a/llvm/test/CodeGen/RISCV/large-stack.ll b/llvm/test/CodeGen/RISCV/large-stack.ll
--- a/llvm/test/CodeGen/RISCV/large-stack.ll
+++ b/llvm/test/CodeGen/RISCV/large-stack.ll
@@ -16,7 +16,6 @@
 ; RV32I-FPELIM-NEXT:    lui a0, 74565
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
 ; RV32I-FPELIM-NEXT:    add sp, sp, a0
-; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: test:
@@ -36,12 +35,8 @@
 ; RV32I-WITHFP-NEXT:    addi a0, a0, -352
 ; RV32I-WITHFP-NEXT:    add sp, sp, a0
 ; RV32I-WITHFP-NEXT:    lw s0, 2024(sp)
-; RV32I-WITHFP-NEXT:    .cfi_def_cfa sp, 2032
 ; RV32I-WITHFP-NEXT:    lw ra, 2028(sp)
-; RV32I-WITHFP-NEXT:    .cfi_restore ra
-; RV32I-WITHFP-NEXT:    .cfi_restore s0
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
-; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-WITHFP-NEXT:    ret
   %tmp = alloca [ 305419896 x i8 ] , align 4
   ret void
@@ -80,10 +75,7 @@
 ; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 2032
 ; RV32I-FPELIM-NEXT:    lw s1, 2024(sp)
 ; RV32I-FPELIM-NEXT:    lw s0, 2028(sp)
-; RV32I-FPELIM-NEXT:    .cfi_restore s0
-; RV32I-FPELIM-NEXT:    .cfi_restore s1
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 2032
-; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
@@ -123,14 +115,8 @@
 ; RV32I-WITHFP-NEXT:    lw s2, 2016(sp)
 ; RV32I-WITHFP-NEXT:    lw s1, 2020(sp)
 ; RV32I-WITHFP-NEXT:    lw s0, 2024(sp)
-; RV32I-WITHFP-NEXT:    .cfi_def_cfa sp, 2032
 ; RV32I-WITHFP-NEXT:    lw ra, 2028(sp)
-; RV32I-WITHFP-NEXT:    .cfi_restore ra
-; RV32I-WITHFP-NEXT:    .cfi_restore s0
-; RV32I-WITHFP-NEXT:    .cfi_restore s1
-; RV32I-WITHFP-NEXT:    .cfi_restore s2
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
-; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-WITHFP-NEXT:    ret
   %data = alloca [ 100000 x i32 ] , align 4
   %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
diff --git a/llvm/test/CodeGen/RISCV/split-offsets.ll b/llvm/test/CodeGen/RISCV/split-offsets.ll
--- a/llvm/test/CodeGen/RISCV/split-offsets.ll
+++ b/llvm/test/CodeGen/RISCV/split-offsets.ll
@@ -22,7 +22,6 @@
 ; RV32I-NEXT:    sw a3, 4(a0)
 ; RV32I-NEXT:    sw a3, 0(a1)
 ; RV32I-NEXT:    sw a2, 4(a1)
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test1:
@@ -38,7 +37,6 @@
 ; RV64I-NEXT:    sw a3, 4(a0)
 ; RV64I-NEXT:    sw a3, 0(a1)
 ; RV64I-NEXT:    sw a2, 4(a1)
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 entry:
   %s = load [65536 x i32]*, [65536 x i32]** %sp
@@ -74,7 +72,6 @@
 ; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    blt a3, a2, .LBB1_1
 ; RV32I-NEXT:  .LBB1_2: # %while_end
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test2:
@@ -99,7 +96,6 @@
 ; RV64I-NEXT:    sext.w a4, a3
 ; RV64I-NEXT:    blt a4, a2, .LBB1_1
 ; RV64I-NEXT:  .LBB1_2: # %while_end
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 entry:
   %s = load [65536 x i32]*, [65536 x i32]** %sp
diff --git a/llvm/test/CodeGen/RISCV/srem-lkk.ll b/llvm/test/CodeGen/RISCV/srem-lkk.ll
--- a/llvm/test/CodeGen/RISCV/srem-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-lkk.ll
@@ -18,9 +18,7 @@
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_positive_odd:
@@ -35,7 +33,6 @@
 ; RV32IM-NEXT:    addi a2, zero, 95
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_positive_odd:
@@ -48,9 +45,7 @@
 ; RV64I-NEXT:    addi a1, zero, 95
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_positive_odd:
@@ -72,7 +67,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 95
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 95
   ret i32 %1
@@ -89,9 +83,7 @@
 ; RV32I-NEXT:    addi a1, zero, 1060
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_positive_even:
@@ -105,7 +97,6 @@
 ; RV32IM-NEXT:    addi a2, zero, 1060
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_positive_even:
@@ -118,9 +109,7 @@
 ; RV64I-NEXT:    addi a1, zero, 1060
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_positive_even:
@@ -139,7 +128,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 1060
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 1060
   ret i32 %1
@@ -156,9 +144,7 @@
 ; RV32I-NEXT:    addi a1, zero, -723
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_negative_odd:
@@ -172,7 +158,6 @@
 ; RV32IM-NEXT:    addi a2, zero, -723
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_negative_odd:
@@ -185,9 +170,7 @@
 ; RV64I-NEXT:    addi a1, zero, -723
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_negative_odd:
@@ -209,7 +192,6 @@
 ; RV64IM-NEXT:    addi a2, zero, -723
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, -723
   ret i32 %1
@@ -227,9 +209,7 @@
 ; RV32I-NEXT:    addi a1, a1, 1595
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_negative_even:
@@ -244,7 +224,6 @@
 ; RV32IM-NEXT:    addi a2, a2, 1595
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_negative_even:
@@ -258,9 +237,7 @@
 ; RV64I-NEXT:    addiw a1, a1, 1595
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_negative_even:
@@ -282,7 +259,6 @@
 ; RV64IM-NEXT:    addiw a2, a2, 1595
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, -22981
   ret i32 %1
@@ -312,11 +288,7 @@
 ; RV32I-NEXT:    lw s1, 4(sp)
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_srem_sdiv:
@@ -332,7 +304,6 @@
 ; RV32IM-NEXT:    mul a2, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a2
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_srem_sdiv:
@@ -357,11 +328,7 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    ld s0, 16(sp)
 ; RV64I-NEXT:    ld ra, 24(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
 ; RV64I-NEXT:    addi sp, sp, 32
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_srem_sdiv:
@@ -384,7 +351,6 @@
 ; RV64IM-NEXT:    mul a2, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a2
 ; RV64IM-NEXT:    addw a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 95
   %2 = sdiv i32 %x, 95
@@ -401,7 +367,6 @@
 ; RV32I-NEXT:    add a1, a0, a1
 ; RV32I-NEXT:    andi a1, a1, -64
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_power_of_two:
@@ -411,7 +376,6 @@
 ; RV32IM-NEXT:    add a1, a0, a1
 ; RV32IM-NEXT:    andi a1, a1, -64
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_power_of_two:
@@ -425,7 +389,6 @@
 ; RV64I-NEXT:    addi a2, a2, -64
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_power_of_two:
@@ -439,7 +402,6 @@
 ; RV64IM-NEXT:    addi a2, a2, -64
 ; RV64IM-NEXT:    and a1, a1, a2
 ; RV64IM-NEXT:    subw a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 64
   ret i32 %1
@@ -450,7 +412,6 @@
 ; CHECK-LABEL: dont_fold_srem_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mv a0, zero
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = srem i32 %x, 1
   ret i32 %1
@@ -466,7 +427,6 @@
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i32_smax:
@@ -477,7 +437,6 @@
 ; RV32IM-NEXT:    lui a2, 524288
 ; RV32IM-NEXT:    and a1, a1, a2
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i32_smax:
@@ -492,7 +451,6 @@
 ; RV64I-NEXT:    slli a2, a2, 31
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i32_smax:
@@ -507,7 +465,6 @@
 ; RV64IM-NEXT:    slli a2, a2, 31
 ; RV64IM-NEXT:    and a1, a1, a2
 ; RV64IM-NEXT:    addw a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 2147483648
   ret i32 %1
@@ -525,9 +482,7 @@
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __moddi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i64:
@@ -540,9 +495,7 @@
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __moddi3
 ; RV32IM-NEXT:    lw ra, 12(sp)
-; RV32IM-NEXT:    .cfi_restore ra
 ; RV32IM-NEXT:    addi sp, sp, 16
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i64:
@@ -554,9 +507,7 @@
 ; RV64I-NEXT:    addi a1, zero, 98
 ; RV64I-NEXT:    call __moddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i64:
@@ -576,7 +527,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 98
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem i64 %x, 98
   ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
--- a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
@@ -58,15 +58,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_vec_1:
@@ -117,7 +109,6 @@
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_vec_1:
@@ -169,15 +160,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_vec_1:
@@ -252,7 +235,6 @@
 ; RV64IM-NEXT:    sh a3, 4(a0)
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a1, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
   ret <4 x i16> %1
@@ -308,15 +290,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_srem_vec_2:
@@ -360,7 +334,6 @@
 ; RV32IM-NEXT:    sh a2, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh t0, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_srem_vec_2:
@@ -412,15 +385,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_srem_vec_2:
@@ -470,7 +435,6 @@
 ; RV64IM-NEXT:    sh a2, 4(a0)
 ; RV64IM-NEXT:    sh a1, 2(a0)
 ; RV64IM-NEXT:    sh t0, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   ret <4 x i16> %1
@@ -560,19 +524,7 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_srem_sdiv:
@@ -620,7 +572,6 @@
 ; RV32IM-NEXT:    sh a2, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a4, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_srem_sdiv:
@@ -704,19 +655,7 @@
 ; RV64I-NEXT:    ld s1, 72(sp)
 ; RV64I-NEXT:    ld s0, 80(sp)
 ; RV64I-NEXT:    ld ra, 88(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
-; RV64I-NEXT:    .cfi_restore s6
-; RV64I-NEXT:    .cfi_restore s7
-; RV64I-NEXT:    .cfi_restore s8
-; RV64I-NEXT:    .cfi_restore s9
 ; RV64I-NEXT:    addi sp, sp, 96
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_srem_sdiv:
@@ -770,7 +709,6 @@
 ; RV64IM-NEXT:    sh a1, 4(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a2, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -829,13 +767,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_power_of_two:
@@ -877,7 +809,6 @@
 ; RV32IM-NEXT:    sh a2, 2(a0)
 ; RV32IM-NEXT:    sh a1, 0(a0)
 ; RV32IM-NEXT:    sh a7, 6(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_power_of_two:
@@ -929,13 +860,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_power_of_two:
@@ -983,7 +908,6 @@
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a1, 0(a0)
 ; RV64IM-NEXT:    sh a7, 6(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
@@ -1030,13 +954,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_one:
@@ -1078,7 +996,6 @@
 ; RV32IM-NEXT:    sh a2, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a3, 2(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_one:
@@ -1120,13 +1037,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_one:
@@ -1185,7 +1096,6 @@
 ; RV64IM-NEXT:    sh a2, 6(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
@@ -1234,13 +1144,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_i16_smax:
@@ -1279,7 +1183,6 @@
 ; RV32IM-NEXT:    sh a1, 6(a0)
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a2, 2(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_i16_smax:
@@ -1323,13 +1226,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_i16_smax:
@@ -1380,7 +1277,6 @@
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a3, 6(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
   ret <4 x i16> %1
@@ -1468,19 +1364,7 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_srem_i64:
@@ -1563,19 +1447,7 @@
 ; RV32IM-NEXT:    lw s1, 36(sp)
 ; RV32IM-NEXT:    lw s0, 40(sp)
 ; RV32IM-NEXT:    lw ra, 44(sp)
-; RV32IM-NEXT:    .cfi_restore ra
-; RV32IM-NEXT:    .cfi_restore s0
-; RV32IM-NEXT:    .cfi_restore s1
-; RV32IM-NEXT:    .cfi_restore s2
-; RV32IM-NEXT:    .cfi_restore s3
-; RV32IM-NEXT:    .cfi_restore s4
-; RV32IM-NEXT:    .cfi_restore s5
-; RV32IM-NEXT:    .cfi_restore s6
-; RV32IM-NEXT:    .cfi_restore s7
-; RV32IM-NEXT:    .cfi_restore s8
-; RV32IM-NEXT:    .cfi_restore s9
 ; RV32IM-NEXT:    addi sp, sp, 48
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_srem_i64:
@@ -1617,13 +1489,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_srem_i64:
@@ -1682,7 +1548,6 @@
 ; RV64IM-NEXT:    sd a2, 24(a0)
 ; RV64IM-NEXT:    sd a3, 8(a0)
 ; RV64IM-NEXT:    sd a1, 16(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
   ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/RISCV/urem-lkk.ll b/llvm/test/CodeGen/RISCV/urem-lkk.ll
--- a/llvm/test/CodeGen/RISCV/urem-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/urem-lkk.ll
@@ -18,9 +18,7 @@
 ; RV32I-NEXT:    addi a1, zero, 95
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_positive_odd:
@@ -35,7 +33,6 @@
 ; RV32IM-NEXT:    addi a2, zero, 95
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_positive_odd:
@@ -49,9 +46,7 @@
 ; RV64I-NEXT:    addi a1, zero, 95
 ; RV64I-NEXT:    call __umoddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_positive_odd:
@@ -74,7 +69,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 95
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 95
   ret i32 %1
@@ -91,9 +85,7 @@
 ; RV32I-NEXT:    addi a1, zero, 1060
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_positive_even:
@@ -105,7 +97,6 @@
 ; RV32IM-NEXT:    addi a2, zero, 1060
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_positive_even:
@@ -119,9 +110,7 @@
 ; RV64I-NEXT:    addi a1, zero, 1060
 ; RV64I-NEXT:    call __umoddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_positive_even:
@@ -141,7 +130,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 1060
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 1060
   ret i32 %1
@@ -171,11 +159,7 @@
 ; RV32I-NEXT:    lw s1, 4(sp)
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_urem_udiv:
@@ -191,7 +175,6 @@
 ; RV32IM-NEXT:    mul a2, a1, a2
 ; RV32IM-NEXT:    sub a0, a0, a2
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_urem_udiv:
@@ -217,11 +200,7 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    ld s0, 16(sp)
 ; RV64I-NEXT:    ld ra, 24(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
 ; RV64I-NEXT:    addi sp, sp, 32
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_urem_udiv:
@@ -245,7 +224,6 @@
 ; RV64IM-NEXT:    mul a2, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a2
 ; RV64IM-NEXT:    add a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 95
   %2 = udiv i32 %x, 95
@@ -258,7 +236,6 @@
 ; CHECK-LABEL: dont_fold_urem_power_of_two:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a0, a0, 63
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem i32 %x, 64
   ret i32 %1
@@ -269,7 +246,6 @@
 ; CHECK-LABEL: dont_fold_urem_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mv a0, zero
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem i32 %x, 1
   ret i32 %1
@@ -279,7 +255,6 @@
 define i32 @dont_fold_urem_i32_umax(i32 %x) {
 ; CHECK-LABEL: dont_fold_urem_i32_umax:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem i32 %x, 4294967296
   ret i32 %1
@@ -297,9 +272,7 @@
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    call __umoddi3
 ; RV32I-NEXT:    lw ra, 12(sp)
-; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_i64:
@@ -312,9 +285,7 @@
 ; RV32IM-NEXT:    mv a3, zero
 ; RV32IM-NEXT:    call __umoddi3
 ; RV32IM-NEXT:    lw ra, 12(sp)
-; RV32IM-NEXT:    .cfi_restore ra
 ; RV32IM-NEXT:    addi sp, sp, 16
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_i64:
@@ -326,9 +297,7 @@
 ; RV64I-NEXT:    addi a1, zero, 98
 ; RV64I-NEXT:    call __umoddi3
 ; RV64I-NEXT:    ld ra, 8(sp)
-; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_i64:
@@ -347,7 +316,6 @@
 ; RV64IM-NEXT:    addi a2, zero, 98
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    sub a0, a0, a1
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem i64 %x, 98
   ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
@@ -59,15 +59,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_vec_1:
@@ -112,7 +104,6 @@
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_vec_1:
@@ -164,15 +155,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_vec_1:
@@ -242,7 +225,6 @@
 ; RV64IM-NEXT:    sh a3, 4(a0)
 ; RV64IM-NEXT:    sh a2, 2(a0)
 ; RV64IM-NEXT:    sh a1, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
   ret <4 x i16> %1
@@ -298,15 +280,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: fold_urem_vec_2:
@@ -350,7 +324,6 @@
 ; RV32IM-NEXT:    sh a2, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh t0, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_urem_vec_2:
@@ -402,15 +375,7 @@
 ; RV64I-NEXT:    ld s1, 40(sp)
 ; RV64I-NEXT:    ld s0, 48(sp)
 ; RV64I-NEXT:    ld ra, 56(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
 ; RV64I-NEXT:    addi sp, sp, 64
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_vec_2:
@@ -460,7 +425,6 @@
 ; RV64IM-NEXT:    sh a2, 4(a0)
 ; RV64IM-NEXT:    sh a1, 2(a0)
 ; RV64IM-NEXT:    sh t0, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   ret <4 x i16> %1
@@ -550,19 +514,7 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: combine_urem_udiv:
@@ -610,7 +562,6 @@
 ; RV32IM-NEXT:    sh a3, 4(a0)
 ; RV32IM-NEXT:    sh a1, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_urem_udiv:
@@ -694,19 +645,7 @@
 ; RV64I-NEXT:    ld s1, 72(sp)
 ; RV64I-NEXT:    ld s0, 80(sp)
 ; RV64I-NEXT:    ld ra, 88(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
-; RV64I-NEXT:    .cfi_restore s4
-; RV64I-NEXT:    .cfi_restore s5
-; RV64I-NEXT:    .cfi_restore s6
-; RV64I-NEXT:    .cfi_restore s7
-; RV64I-NEXT:    .cfi_restore s8
-; RV64I-NEXT:    .cfi_restore s9
 ; RV64I-NEXT:    addi sp, sp, 96
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: combine_urem_udiv:
@@ -760,7 +699,6 @@
 ; RV64IM-NEXT:    sh a1, 4(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a2, 0(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
@@ -804,13 +742,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_power_of_two:
@@ -836,7 +768,6 @@
 ; RV32IM-NEXT:    sh a3, 2(a0)
 ; RV32IM-NEXT:    sh a1, 0(a0)
 ; RV32IM-NEXT:    sh a2, 6(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_power_of_two:
@@ -873,13 +804,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_power_of_two:
@@ -911,7 +836,6 @@
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a2, 0(a0)
 ; RV64IM-NEXT:    sh a1, 6(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
@@ -958,13 +882,7 @@
 ; RV32I-NEXT:    lw s1, 20(sp)
 ; RV32I-NEXT:    lw s0, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
 ; RV32I-NEXT:    addi sp, sp, 32
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_one:
@@ -999,7 +917,6 @@
 ; RV32IM-NEXT:    sh a3, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a2, 2(a0)
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_one:
@@ -1041,13 +958,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_one:
@@ -1103,7 +1014,6 @@
 ; RV64IM-NEXT:    sh a2, 6(a0)
 ; RV64IM-NEXT:    sh a3, 2(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
@@ -1113,7 +1023,6 @@
 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; CHECK-LABEL: dont_fold_urem_i16_smax:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
   ret <4 x i16> %1
@@ -1201,19 +1110,7 @@
 ; RV32I-NEXT:    lw s1, 36(sp)
 ; RV32I-NEXT:    lw s0, 40(sp)
 ; RV32I-NEXT:    lw ra, 44(sp)
-; RV32I-NEXT:    .cfi_restore ra
-; RV32I-NEXT:    .cfi_restore s0
-; RV32I-NEXT:    .cfi_restore s1
-; RV32I-NEXT:    .cfi_restore s2
-; RV32I-NEXT:    .cfi_restore s3
-; RV32I-NEXT:    .cfi_restore s4
-; RV32I-NEXT:    .cfi_restore s5
-; RV32I-NEXT:    .cfi_restore s6
-; RV32I-NEXT:    .cfi_restore s7
-; RV32I-NEXT:    .cfi_restore s8
-; RV32I-NEXT:    .cfi_restore s9
 ; RV32I-NEXT:    addi sp, sp, 48
-; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: dont_fold_urem_i64:
@@ -1296,19 +1193,7 @@
 ; RV32IM-NEXT:    lw s1, 36(sp)
 ; RV32IM-NEXT:    lw s0, 40(sp)
 ; RV32IM-NEXT:    lw ra, 44(sp)
-; RV32IM-NEXT:    .cfi_restore ra
-; RV32IM-NEXT:    .cfi_restore s0
-; RV32IM-NEXT:    .cfi_restore s1
-; RV32IM-NEXT:    .cfi_restore s2
-; RV32IM-NEXT:    .cfi_restore s3
-; RV32IM-NEXT:    .cfi_restore s4
-; RV32IM-NEXT:    .cfi_restore s5
-; RV32IM-NEXT:    .cfi_restore s6
-; RV32IM-NEXT:    .cfi_restore s7
-; RV32IM-NEXT:    .cfi_restore s8
-; RV32IM-NEXT:    .cfi_restore s9
 ; RV32IM-NEXT:    addi sp, sp, 48
-; RV32IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: dont_fold_urem_i64:
@@ -1350,13 +1235,7 @@
 ; RV64I-NEXT:    ld s1, 24(sp)
 ; RV64I-NEXT:    ld s0, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
-; RV64I-NEXT:    .cfi_restore ra
-; RV64I-NEXT:    .cfi_restore s0
-; RV64I-NEXT:    .cfi_restore s1
-; RV64I-NEXT:    .cfi_restore s2
-; RV64I-NEXT:    .cfi_restore s3
 ; RV64I-NEXT:    addi sp, sp, 48
-; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: dont_fold_urem_i64:
@@ -1412,7 +1291,6 @@
 ; RV64IM-NEXT:    sd a2, 24(a0)
 ; RV64IM-NEXT:    sd a3, 8(a0)
 ; RV64IM-NEXT:    sd a1, 16(a0)
-; RV64IM-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
   ret <4 x i64> %1
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -53,7 +53,6 @@
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a1, sp, 24
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a1, 12(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, 48
-; ILP32-ILP32F-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; ILP32-ILP32F-FPELIM-NEXT:    ret
 ;
 ; ILP32-ILP32F-WITHFP-LABEL: va1:
@@ -77,12 +76,8 @@
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a1, s0, 8
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a1, -12(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 8(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 12(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_restore ra
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_restore s0
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 48
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; ILP32-ILP32F-WITHFP-NEXT:    ret
 ;
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1:
@@ -100,7 +95,6 @@
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, sp, 24
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a1, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va1:
@@ -119,7 +113,6 @@
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lw a0, 24(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, 80
-; LP64-LP64F-LP64D-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-WITHFP-LABEL: va1:
@@ -144,12 +137,8 @@
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lw a0, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_def_cfa sp, 32
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_restore ra
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_restore s0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
   %va = alloca i8*, align 4
   %1 = bitcast i8** %va to i8*
@@ -1809,7 +1798,6 @@
 ; ILP32-ILP32F-FPELIM-NEXT:    lui a1, 24414
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a1, a1, 304
 ; ILP32-ILP32F-FPELIM-NEXT:    add sp, sp, a1
-; ILP32-ILP32F-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; ILP32-ILP32F-FPELIM-NEXT:    ret
 ;
 ; ILP32-ILP32F-WITHFP-LABEL: va_large_stack:
@@ -1842,12 +1830,8 @@
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a1, a1, -1728
 ; ILP32-ILP32F-WITHFP-NEXT:    add sp, sp, a1
 ; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 1992(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_def_cfa sp, 2000
 ; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 1996(sp)
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_restore ra
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_restore s0
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 2032
-; ILP32-ILP32F-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; ILP32-ILP32F-WITHFP-NEXT:    ret
 ;
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack:
@@ -1893,7 +1877,6 @@
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lui a1, 24414
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a1, a1, 304
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add sp, sp, a1
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va_large_stack:
@@ -1943,7 +1926,6 @@
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a1, 24414
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a1, a1, 336
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    add sp, sp, a1
-; LP64-LP64F-LP64D-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack:
@@ -1977,12 +1959,8 @@
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a1, a1, -1680
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add sp, sp, a1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 1952(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_def_cfa sp, 1968
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 1960(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_restore ra
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_restore s0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 2032
-; LP64-LP64F-LP64D-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
   %large = alloca [ 100000000 x i8 ]
   %va = alloca i8*, align 4