diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h
--- a/llvm/lib/Target/X86/X86RegisterInfo.h
+++ b/llvm/lib/Target/X86/X86RegisterInfo.h
@@ -91,6 +91,9 @@
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
+  /// Return whether this function requires register scavenging.
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
+
   /// getGPRsForTailCall - Returns a register class with registers that can be
   /// used in forming tail calls.
   const TargetRegisterClass *
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -22,6 +22,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/Constants.h"
@@ -256,6 +257,11 @@
   return RC;
 }
 
+bool X86RegisterInfo::requiresRegisterScavenging(
+    const MachineFunction &MF) const {
+  return true;
+}
+
 unsigned
 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
                                      MachineFunction &MF) const {
@@ -775,11 +781,35 @@
   }
 
   if (MI.getOperand(FIOperandNum+3).isImm()) {
-    // Offset is a 32-bit integer.
     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
     int Offset = FIOffset + Imm;
-    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
-           "Requesting 64-bit offset in 32-bit immediate!");
+    if (!isInt<32>((long long)FIOffset + Imm)) {
+      // Load the immediate into a register and use SIB addressing.
+      assert(Is64Bit && "Need 64-bit frame offset in 32-bit mode!");
+
+      assert(MI.getOperand(FIOperandNum + X86::AddrIndexReg).getReg() == 0 &&
+             "Index register already in use with large frame offset!");
+
+      assert(RS && "Register scavenger not available for large frame offset!");
+
+      assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
+             "No emergency spill slot for large frame offset!");
+
+      // WARNING: This API is deprecated but PrologEpilogInserter uses forward()
+      // so we have to use this here.
+      Register OffsetReg = RS->scavengeRegister(getRegClass(BasePtr), II,
+                                                SPAdj);
+
+      const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
+
+      BuildMI(MBB, II, MI.getDebugLoc(), TII->get(X86::MOV64ri), OffsetReg).
+          addImm((long long)FIOffset + Imm);
+      MI.getOperand(FIOperandNum + X86::AddrIndexReg).setReg(OffsetReg);
+      MI.getOperand(FIOperandNum + X86::AddrIndexReg).setIsKill();
+      MI.getOperand(FIOperandNum + X86::AddrDisp).setImm(0);
+      return;
+    }
+
     if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
   } else {
diff --git a/llvm/test/CodeGen/X86/large-stack-offset.ll b/llvm/test/CodeGen/X86/large-stack-offset.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/large-stack-offset.ll
@@ -0,0 +1,34 @@
+; Test that we can support a large immediate offset on the stack.
+;
+; RUN: llc %s -o - | FileCheck %s
+;
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+source_filename = "test.c"
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@.str.7 = external dso_local unnamed_addr constant [73 x i8], align 1
+
+; Function Attrs: noinline optnone
+define dso_local void @main() local_unnamed_addr #0 {
+entry:
+  %result = alloca [1048576000 x double], align 16
+  br i1 undef, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  unreachable
+
+if.end:                                           ; preds = %entry
+  %arrayidx34 = getelementptr inbounds [1048576000 x double], [1048576000 x double]* %result, i64 0, i64 262143999
+; CHECK: movabsq $2298478584, [[INDEX:%[a-z]+]]       # imm = 0x88FFFFF8
+; CHECK-NEXT:	movsd	(%rbp,[[INDEX]]), {{[a-z0-9]+}}
+
+  %0 = load double, double* %arrayidx34, align 8
+  call void (i8*, ...) @printf(i8* getelementptr inbounds ([73 x i8], [73 x i8]* @.str.7, i64 0, i64 0), i32 undef, i32 262143999, double %0, i32 524287999, double undef, i32 786431999, double undef, i32 1048575999, double undef)
+  ret void
+}
+
+declare dso_local void @printf(i8*, ...) local_unnamed_addr #1
+
+attributes #0 = { noinline optnone "frame-pointer"="all" "no-infs-fp-math"="false" }
+attributes #1 = { "use-soft-float"="false" }