diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -4161,6 +4161,8 @@ case ISD::FP_EXTEND: case ISD::STRICT_FP_EXTEND: + case ISD::FP_ROUND: + case ISD::STRICT_FP_ROUND: case ISD::FP_TO_SINT: case ISD::STRICT_FP_TO_SINT: case ISD::FP_TO_UINT: @@ -4297,13 +4299,21 @@ if (TLI.isTypeLegal(WideVT) && !N->isStrictFPOpcode()) { SDValue Res; if (N->isStrictFPOpcode()) { - Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other }, - { N->getOperand(0), InOp }); + if (Opcode == ISD::STRICT_FP_ROUND) + Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other }, + { N->getOperand(0), InOp, N->getOperand(2) }); + else + Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other }, + { N->getOperand(0), InOp }); // Legalize the chain result - switch anything that used the old chain to // use the new one. ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); - } else - Res = DAG.getNode(Opcode, dl, WideVT, InOp); + } else { + if (Opcode == ISD::FP_ROUND) + Res = DAG.getNode(Opcode, dl, WideVT, InOp, N->getOperand(1)); + else + Res = DAG.getNode(Opcode, dl, WideVT, InOp); + } return DAG.getNode( ISD::EXTRACT_SUBVECTOR, dl, VT, Res, DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))); diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll --- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll +++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll @@ -30,6 +30,16 @@ ret void } +; FUNC-LABEL: {{^}}fptrunc_v3f64_to_v3f32: +; GCN: v_cvt_f32_f64_e32 +; GCN: v_cvt_f32_f64_e32 +; GCN: v_cvt_f32_f64_e32 +define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(<3 x float> addrspace(1)* %out, <3 x double> %in) { + %result = fptrunc <3 x double> %in to <3 x float> + store <3 x float> %result, <3 x float> addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}fptrunc_v4f64_to_v4f32: ; GCN: v_cvt_f32_f64_e32 ; GCN: v_cvt_f32_f64_e32