diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -146,7 +146,8 @@
       ISD::SETGE,  ISD::SETNE};
 
   ISD::NodeType FPOpToExtend[] = {
-      ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM};
+      ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
+      ISD::FP_TO_FP16};
 
   if (Subtarget.hasStdExtF()) {
     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
@@ -158,6 +159,8 @@
     setOperationAction(ISD::BR_CC, MVT::f32, Expand);
     for (auto Op : FPOpToExtend)
       setOperationAction(Op, MVT::f32, Expand);
+    setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
+    setTruncStoreAction(MVT::f32, MVT::f16, Expand);
   }
 
   if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
@@ -175,6 +178,8 @@
     setTruncStoreAction(MVT::f64, MVT::f32, Expand);
     for (auto Op : FPOpToExtend)
       setOperationAction(Op, MVT::f64, Expand);
+    setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
+    setTruncStoreAction(MVT::f64, MVT::f16, Expand);
   }
 
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
diff --git a/llvm/test/CodeGen/RISCV/fp16-promote.ll b/llvm/test/CodeGen/RISCV/fp16-promote.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fp16-promote.ll
@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr +d -target-abi ilp32d < %s | FileCheck %s
+
+define void @test_load_store(half* %p, half* %q) nounwind {
+; CHECK-LABEL: test_load_store:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lh a0, 0(a0)
+; CHECK-NEXT:    sh a0, 0(a1)
+; CHECK-NEXT:    ret
+  %a = load half, half* %p, align 2
+  store half %a, half* %q
+  ret void
+}
+
+define float @test_fpextend_float(half* %p) nounwind {
+; CHECK-LABEL: test_fpextend_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp)
+; CHECK-NEXT:    lhu a0, 0(a0)
+; CHECK-NEXT:    call __gnu_h2f_ieee
+; CHECK-NEXT:    lw ra, 12(sp)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %a = load half, half* %p
+  %r = fpext half %a to float
+  ret float %r
+}
+
+define double @test_fpextend_double(half* %p) nounwind {
+; CHECK-LABEL: test_fpextend_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp)
+; CHECK-NEXT:    lhu a0, 0(a0)
+; CHECK-NEXT:    call __gnu_h2f_ieee
+; CHECK-NEXT:    fcvt.d.s fa0, fa0
+; CHECK-NEXT:    lw ra, 12(sp)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %a = load half, half* %p
+  %r = fpext half %a to double
+  ret double %r
+}
+
+define void @test_fptrunc_float(float %f, half* %p) nounwind {
+; CHECK-LABEL: test_fptrunc_float:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp)
+; CHECK-NEXT:    sw s0, 8(sp)
+; CHECK-NEXT:    mv s0, a0
+; CHECK-NEXT:    call __gnu_f2h_ieee
+; CHECK-NEXT:    sh a0, 0(s0)
+; CHECK-NEXT:    lw s0, 8(sp)
+; CHECK-NEXT:    lw ra, 12(sp)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %a = fptrunc float %f to half
+  store half %a, half* %p
+  ret void
+}
+
+define void @test_fptrunc_double(double %d, half* %p) nounwind {
+; CHECK-LABEL: test_fptrunc_double:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw ra, 12(sp)
+; CHECK-NEXT:    sw s0, 8(sp)
+; CHECK-NEXT:    mv s0, a0
+; CHECK-NEXT:    call __truncdfhf2
+; CHECK-NEXT:    sh a0, 0(s0)
+; CHECK-NEXT:    lw s0, 8(sp)
+; CHECK-NEXT:    lw ra, 12(sp)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %a = fptrunc double %d to half
+  store half %a, half* %p
+  ret void
+}
+
+define void @test_fadd(half* %p, half* %q) nounwind {
+; CHECK-LABEL: test_fadd:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    sw ra, 28(sp)
+; CHECK-NEXT:    sw s0, 24(sp)
+; CHECK-NEXT:    sw s1, 20(sp)
+; CHECK-NEXT:    fsd fs0, 8(sp)
+; CHECK-NEXT:    mv s0, a1
+; CHECK-NEXT:    mv s1, a0
+; CHECK-NEXT:    lhu a0, 0(a0)
+; CHECK-NEXT:    call __gnu_h2f_ieee
+; CHECK-NEXT:    fmv.s fs0, fa0
+; CHECK-NEXT:    lhu a0, 0(s0)
+; CHECK-NEXT:    call __gnu_h2f_ieee
+; CHECK-NEXT:    fadd.s fa0, fs0, fa0
+; CHECK-NEXT:    call __gnu_f2h_ieee
+; CHECK-NEXT:    sh a0, 0(s1)
+; CHECK-NEXT:    fld fs0, 8(sp)
+; CHECK-NEXT:    lw s1, 20(sp)
+; CHECK-NEXT:    lw s0, 24(sp)
+; CHECK-NEXT:    lw ra, 28(sp)
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fadd half %a, %b
+  store half %r, half* %p
+  ret void
+}
+
+define void @test_fmul(half* %p, half* %q) nounwind {
+; CHECK-LABEL: test_fmul:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    sw ra, 28(sp)
+; CHECK-NEXT:    sw s0, 24(sp)
+; CHECK-NEXT:    sw s1, 20(sp)
+; CHECK-NEXT:    fsd fs0, 8(sp)
+; CHECK-NEXT:    mv s0, a1
+; CHECK-NEXT:    mv s1, a0
+; CHECK-NEXT:    lhu a0, 0(a0)
+; CHECK-NEXT:    call __gnu_h2f_ieee
+; CHECK-NEXT:    fmv.s fs0, fa0
+; CHECK-NEXT:    lhu a0, 0(s0)
+; CHECK-NEXT:    call __gnu_h2f_ieee
+; CHECK-NEXT:    fmul.s fa0, fs0, fa0
+; CHECK-NEXT:    call __gnu_f2h_ieee
+; CHECK-NEXT:    sh a0, 0(s1)
+; CHECK-NEXT:    fld fs0, 8(sp)
+; CHECK-NEXT:    lw s1, 20(sp)
+; CHECK-NEXT:    lw s0, 24(sp)
+; CHECK-NEXT:    lw ra, 28(sp)
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %a = load half, half* %p, align 2
+  %b = load half, half* %q, align 2
+  %r = fmul half %a, %b
+  store half %r, half* %p
+  ret void
+}