diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3958,6 +3958,13 @@
                                               const AsmOperandInfo &OpInfo,
                                               SelectionDAG &DAG) const;
 
+  /// Returns how the platform's inline assembly operands of the given type
+  /// should be extended for the given register type (ZERO_EXTEND, SIGN_EXTEND
+  /// or ANY_EXTEND).
+  virtual ISD::NodeType getExtendForInlineAsmOperand(EVT VT) const {
+    return ISD::ANY_EXTEND;
+  }
+
   //===--------------------------------------------------------------------===//
   // Div utility functions
   //
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8258,12 +8258,14 @@
             return;
           }
 
-          RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType());
+          EVT ValVT = InOperandVal.getValueType();
+          RegsForValue MatchedRegs(Regs, RegVT, ValVT);
 
           SDLoc dl = getCurSDLoc();
           // Use the produced MatchedRegs object to
           MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl, Chain, &Flag,
-                                    CS.getInstruction());
+                                    CS.getInstruction(),
+                                    TLI.getExtendForInlineAsmOperand(ValVT));
           MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
                                            true, OpInfo.getMatchedOperand(), dl,
                                            DAG, AsmNodeOperands);
@@ -8361,8 +8363,11 @@
 
       SDLoc dl = getCurSDLoc();
 
+      EVT ValVT = InOperandVal.getValueType();
+      ISD::NodeType ExtendType = TLI.getExtendForInlineAsmOperand(ValVT);
       OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
-                                        Chain, &Flag, CS.getInstruction());
+                                        Chain, &Flag, CS.getInstruction(),
+                                        ExtendType);
 
       OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
                                                dl, DAG, AsmNodeOperands);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -104,6 +104,8 @@
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
+  ISD::NodeType getExtendForInlineAsmOperand(EVT VT) const override;
+
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2672,6 +2672,16 @@
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
+ISD::NodeType
+RISCVTargetLowering::getExtendForInlineAsmOperand(EVT VT) const {
+  // GCC forces 32-bit integers on RV64I to be sign-extended in registers,
+  // whether unsigned or signed, and this is visible to inline assembly, so we
+  // make it look like we do the same.
+  if (Subtarget.is64Bit() && VT == MVT::i32)
+    return ISD::SIGN_EXTEND;
+  return TargetLowering::getExtendForInlineAsmOperand(VT);
+}
+
 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
                                                    Instruction *Inst,
                                                    AtomicOrdering Ord) const {
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll b/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
@@ -55,7 +55,7 @@
 }
 
 ; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved.
-define i32 @explicit_register_x1(i32 %a) nounwind {
+define i32 @explicit_register_x1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -84,7 +84,7 @@
 }
 
 ; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved.
-define i32 @explicit_register_ra(i32 %a) nounwind {
+define i32 @explicit_register_ra(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_ra:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -112,7 +112,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x2(i32 %a) nounwind {
+define i32 @explicit_register_x2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv sp, a0
@@ -132,7 +132,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_sp(i32 %a) nounwind {
+define i32 @explicit_register_sp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_sp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv sp, a0
@@ -153,7 +153,7 @@
 }
 
 ; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved.
-define i32 @explicit_register_x3(i32 %a) nounwind {
+define i32 @explicit_register_x3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -182,7 +182,7 @@
 }
 
 ; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved.
-define i32 @explicit_register_gp(i32 %a) nounwind {
+define i32 @explicit_register_gp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_gp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -211,7 +211,7 @@
 }
 
 ; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved.
-define i32 @explicit_register_x4(i32 %a) nounwind {
+define i32 @explicit_register_x4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -240,7 +240,7 @@
 }
 
 ; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved.
-define i32 @explicit_register_tp(i32 %a) nounwind {
+define i32 @explicit_register_tp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_tp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -268,7 +268,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x5(i32 %a) nounwind {
+define i32 @explicit_register_x5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t0, a0
@@ -288,7 +288,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t0(i32 %a) nounwind {
+define i32 @explicit_register_t0(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t0, a0
@@ -308,7 +308,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x6(i32 %a) nounwind {
+define i32 @explicit_register_x6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t1, a0
@@ -328,7 +328,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t1(i32 %a) nounwind {
+define i32 @explicit_register_t1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t1, a0
@@ -348,7 +348,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x7(i32 %a) nounwind {
+define i32 @explicit_register_x7(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t2, a0
@@ -368,7 +368,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t2(i32 %a) nounwind {
+define i32 @explicit_register_t2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t2, a0
@@ -389,7 +389,7 @@
 }
 
 ; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved.
-define i32 @explicit_register_x8(i32 %a) nounwind {
+define i32 @explicit_register_x8(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -418,7 +418,7 @@
 }
 
 ; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved.
-define i32 @explicit_register_s0(i32 %a) nounwind {
+define i32 @explicit_register_s0(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -447,7 +447,7 @@
 }
 
 ; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved.
-define i32 @explicit_register_fp(i32 %a) nounwind {
+define i32 @explicit_register_fp(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_fp:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -476,7 +476,7 @@
 }
 
 ; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved.
-define i32 @explicit_register_x9(i32 %a) nounwind {
+define i32 @explicit_register_x9(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x9:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -505,7 +505,7 @@
 }
 
 ; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved.
-define i32 @explicit_register_s1(i32 %a) nounwind {
+define i32 @explicit_register_s1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -533,7 +533,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x10(i32 %a) nounwind {
+define i32 @explicit_register_x10(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -551,7 +551,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a0(i32 %a) nounwind {
+define i32 @explicit_register_a0(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -569,7 +569,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x11(i32 %a) nounwind {
+define i32 @explicit_register_x11(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a1, a0
@@ -589,7 +589,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a1(i32 %a) nounwind {
+define i32 @explicit_register_a1(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a1, a0
@@ -609,7 +609,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x12(i32 %a) nounwind {
+define i32 @explicit_register_x12(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x12:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a0
@@ -629,7 +629,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a2(i32 %a) nounwind {
+define i32 @explicit_register_a2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a0
@@ -649,7 +649,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x13(i32 %a) nounwind {
+define i32 @explicit_register_x13(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x13:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a3, a0
@@ -669,7 +669,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a3(i32 %a) nounwind {
+define i32 @explicit_register_a3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a3, a0
@@ -689,7 +689,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x14(i32 %a) nounwind {
+define i32 @explicit_register_x14(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x14:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a4, a0
@@ -709,7 +709,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a4(i32 %a) nounwind {
+define i32 @explicit_register_a4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a4, a0
@@ -729,7 +729,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x15(i32 %a) nounwind {
+define i32 @explicit_register_x15(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x15:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a5, a0
@@ -749,7 +749,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a5(i32 %a) nounwind {
+define i32 @explicit_register_a5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a5, a0
@@ -769,7 +769,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x16(i32 %a) nounwind {
+define i32 @explicit_register_x16(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a6, a0
@@ -789,7 +789,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a6(i32 %a) nounwind {
+define i32 @explicit_register_a6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a6, a0
@@ -809,7 +809,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x17(i32 %a) nounwind {
+define i32 @explicit_register_x17(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x17:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a7, a0
@@ -829,7 +829,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_a7(i32 %a) nounwind {
+define i32 @explicit_register_a7(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_a7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a7, a0
@@ -850,7 +850,7 @@
 }
 
 ; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved.
-define i32 @explicit_register_x18(i32 %a) nounwind {
+define i32 @explicit_register_x18(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x18:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -879,7 +879,7 @@
 }
 
 ; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved.
-define i32 @explicit_register_s2(i32 %a) nounwind {
+define i32 @explicit_register_s2(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -908,7 +908,7 @@
 }
 
 ; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved.
-define i32 @explicit_register_x19(i32 %a) nounwind {
+define i32 @explicit_register_x19(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x19:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -937,7 +937,7 @@
 }
 
 ; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved.
-define i32 @explicit_register_s3(i32 %a) nounwind {
+define i32 @explicit_register_s3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -966,7 +966,7 @@
 }
 
 ; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved.
-define i32 @explicit_register_x20(i32 %a) nounwind {
+define i32 @explicit_register_x20(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x20:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -995,7 +995,7 @@
 }
 
 ; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved.
-define i32 @explicit_register_s4(i32 %a) nounwind {
+define i32 @explicit_register_s4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1024,7 +1024,7 @@
 }
 
 ; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved.
-define i32 @explicit_register_x21(i32 %a) nounwind {
+define i32 @explicit_register_x21(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x21:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1053,7 +1053,7 @@
 }
 
 ; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved.
-define i32 @explicit_register_s5(i32 %a) nounwind {
+define i32 @explicit_register_s5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1082,7 +1082,7 @@
 }
 
 ; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved.
-define i32 @explicit_register_x22(i32 %a) nounwind {
+define i32 @explicit_register_x22(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x22:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1111,7 +1111,7 @@
 }
 
 ; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved.
-define i32 @explicit_register_s6(i32 %a) nounwind {
+define i32 @explicit_register_s6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1140,7 +1140,7 @@
 }
 
 ; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved.
-define i32 @explicit_register_x23(i32 %a) nounwind {
+define i32 @explicit_register_x23(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x23:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1169,7 +1169,7 @@
 }
 
 ; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved.
-define i32 @explicit_register_s7(i32 %a) nounwind {
+define i32 @explicit_register_s7(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1198,7 +1198,7 @@
 }
 
 ; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved.
-define i32 @explicit_register_x24(i32 %a) nounwind {
+define i32 @explicit_register_x24(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x24:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1227,7 +1227,7 @@
 }
 
 ; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved.
-define i32 @explicit_register_s8(i32 %a) nounwind {
+define i32 @explicit_register_s8(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1256,7 +1256,7 @@
 }
 
 ; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved.
-define i32 @explicit_register_x25(i32 %a) nounwind {
+define i32 @explicit_register_x25(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x25:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1285,7 +1285,7 @@
 }
 
 ; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved.
-define i32 @explicit_register_s9(i32 %a) nounwind {
+define i32 @explicit_register_s9(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s9:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1314,7 +1314,7 @@
 }
 
 ; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved.
-define i32 @explicit_register_x26(i32 %a) nounwind {
+define i32 @explicit_register_x26(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x26:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1343,7 +1343,7 @@
 }
 
 ; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved.
-define i32 @explicit_register_s10(i32 %a) nounwind {
+define i32 @explicit_register_s10(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1372,7 +1372,7 @@
 }
 
 ; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved.
-define i32 @explicit_register_x27(i32 %a) nounwind {
+define i32 @explicit_register_x27(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x27:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1401,7 +1401,7 @@
 }
 
 ; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved.
-define i32 @explicit_register_s11(i32 %a) nounwind {
+define i32 @explicit_register_s11(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_s11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1429,7 +1429,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x28(i32 %a) nounwind {
+define i32 @explicit_register_x28(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x28:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t3, a0
@@ -1449,7 +1449,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t3(i32 %a) nounwind {
+define i32 @explicit_register_t3(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t3, a0
@@ -1469,7 +1469,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x29(i32 %a) nounwind {
+define i32 @explicit_register_x29(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x29:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t4, a0
@@ -1489,7 +1489,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t4(i32 %a) nounwind {
+define i32 @explicit_register_t4(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t4:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t4, a0
@@ -1509,7 +1509,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x30(i32 %a) nounwind {
+define i32 @explicit_register_x30(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t5, a0
@@ -1529,7 +1529,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t5(i32 %a) nounwind {
+define i32 @explicit_register_t5(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t5:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t5, a0
@@ -1549,7 +1549,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_x31(i32 %a) nounwind {
+define i32 @explicit_register_x31(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_x31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t6, a0
@@ -1569,7 +1569,7 @@
   ret i32 %1
 }
 
-define i32 @explicit_register_t6(i32 %a) nounwind {
+define i32 @explicit_register_t6(i32 signext %a) nounwind {
 ; RV32I-LABEL: explicit_register_t6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv t6, a0
diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -6,7 +6,7 @@
 
 @gi = external global i32
 
-define i32 @constraint_r(i32 %a) nounwind {
+define i32 @constraint_r(i32 signext %a) nounwind {
 ; RV32I-LABEL: constraint_r:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, %hi(gi)
@@ -19,7 +19,7 @@
 ; RV64I-LABEL: constraint_r:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, %hi(gi)
-; RV64I-NEXT:    lwu a1, %lo(gi)(a1)
+; RV64I-NEXT:    lw a1, %lo(gi)(a1)
 ; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    #NO_APP
@@ -29,7 +29,7 @@
   ret i32 %2
 }
 
-define i32 @constraint_i(i32 %a) nounwind {
+define i32 @constraint_i(i32 signext %a) nounwind {
 ; RV32I-LABEL: constraint_i:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -175,7 +175,7 @@
   ret void
 }
 
-define i32 @modifier_z_zero(i32 %a) nounwind {
+define i32 @modifier_z_zero(i32 signext %a) nounwind {
 ; RV32I-LABEL: modifier_z_zero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -193,7 +193,7 @@
   ret i32 %1
 }
 
-define i32 @modifier_z_nonzero(i32 %a) nounwind {
+define i32 @modifier_z_nonzero(i32 signext %a) nounwind {
 ; RV32I-LABEL: modifier_z_nonzero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 1
@@ -213,7 +213,7 @@
   ret i32 %1
 }
 
-define i32 @modifier_i_imm(i32 %a) nounwind {
+define i32 @modifier_i_imm(i32 signext %a) nounwind {
 ; RV32I-LABEL: modifier_i_imm:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -231,7 +231,7 @@
   ret i32 %1
 }
 
-define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
+define i32 @modifier_i_reg(i32 signext %a, i32 signext %b) nounwind {
 ; RV32I-LABEL: modifier_i_reg:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP