Index: llvm/include/llvm/IR/IntrinsicsAArch64.td =================================================================== --- llvm/include/llvm/IR/IntrinsicsAArch64.td +++ llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -815,10 +815,23 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". + +class AdvSIMD_Pred2VectorArg_Intrinsic + : Intrinsic<[llvm_anyvector_ty], + [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem]>; + + // // Integer arithmetic // +def int_aarch64_sve_add : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_sub : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_subr : AdvSIMD_Pred2VectorArg_Intrinsic; + +def int_aarch64_sve_bic : AdvSIMD_2VectorArg_Intrinsic; + def int_aarch64_sve_abs : AdvSIMD_Merged1VectorArg_Intrinsic; def int_aarch64_sve_neg : AdvSIMD_Merged1VectorArg_Intrinsic; Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -183,6 +183,13 @@ addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass); addRegisterClass(MVT::nxv1f64, &AArch64::ZPRRegClass); addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass); + + for (auto VT : { MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT:: nxv2i64 }) { + setOperationAction(ISD::SADDSAT, VT, Legal); + setOperationAction(ISD::UADDSAT, VT, Legal); + setOperationAction(ISD::SSUBSAT, VT, Legal); + setOperationAction(ISD::USUBSAT, VT, Legal); + } } // Compute derived properties from the register classes Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -18,26 +18,26 @@ def SETFFR : sve_int_setffr<"setffr">; def WRFFR : sve_int_wrffr<"wrffr">; - defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; - defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; - defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">; - defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">; - defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">; - defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">; - - defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">; - defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">; - defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">; - defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">; - - defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; - defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; - defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">; - - defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">; - defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">; - defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">; - defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">; + defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add", add>; + defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub", sub>; + defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd", saddsat>; + defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd", uaddsat>; + defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub", ssubsat>; + defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub", usubsat>; + + defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and", and>; + defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr", or>; + defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor", xor>; + defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", int_aarch64_sve_bic>; + + defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", int_aarch64_sve_add>; + defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", int_aarch64_sve_sub>; + defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", int_aarch64_sve_subr>; + + defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", null_frag>; + defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor", null_frag>; + defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and", null_frag>; + defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic", null_frag>; defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; @@ -73,14 +73,14 @@ defm UMIN_ZI : sve_int_arith_imm1<0b11, "umin", imm0_255>; defm MUL_ZI : sve_int_arith_imm2<"mul">; - defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul">; - defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">; - defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh">; + defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul", null_frag>; + defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", null_frag>; + defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh", null_frag>; - defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">; - defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv">; - defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">; - defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">; + defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv", null_frag>; + defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv", null_frag>; + defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", null_frag>; + defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", null_frag>; defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot", int_aarch64_sve_sdot>; defm UDOT_ZZZ : sve_intx_dot<0b1, "udot", int_aarch64_sve_udot>; @@ -105,12 +105,12 @@ defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">; defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">; - defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">; - defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">; - defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">; - defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin">; - defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">; - defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">; + defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax", null_frag>; + defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax", null_frag>; + defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", null_frag>; + defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin", null_frag>; + defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd", null_frag>; + defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd", null_frag>; defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe">; defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">; Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -288,6 +288,11 @@ : Pat<(vtd (op vt1:$Op1)), (inst $Op1)>; +class SVE_2_Op_Pat +: Pat<(vtd (op vt1:$Op1, vt2:$Op2)), + (inst $Op1, $Op2)>; + class SVE_3_Op_Pat : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), @@ -1105,10 +1110,10 @@ //===----------------------------------------------------------------------===// class sve_int_bin_cons_arit_0 sz8_64, bits<3> opc, string asm, - ZPRRegOp zprty> + ZPRRegOp zprty, ValueType vt, SDPatternOperator op> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", - "", []>, Sched<[]> { + "", [(set (vt zprty:$Zd), (op (vt zprty:$Zn), (vt zprty:$Zm)))]>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; @@ -1122,11 +1127,11 @@ let Inst{4-0} = Zd; } -multiclass sve_int_bin_cons_arit_0 opc, string asm> { - def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>; - def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>; - def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; - def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; +multiclass sve_int_bin_cons_arit_0 opc, string asm, SDPatternOperator op> { + def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8, nxv16i8, op>; + def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16, nxv8i16, op>; + def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32, nxv4i32, op>; + def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64, nxv2i64, op>; } //===----------------------------------------------------------------------===// @@ -1780,9 +1785,9 @@ //===----------------------------------------------------------------------===// class sve_int_bin_pred_arit_log sz8_64, bits<2> fmt, bits<3> opc, - string asm, ZPRRegOp zprty> + string asm, ValueType vt, ValueType pt, ZPRRegOp zprty, SDPatternOperator op> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), - asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", [(set (vt zprty:$Zdn), (op (pt PPR3bAny:$Pg), (vt zprty:$_Zdn), (vt zprty:$Zm)))]>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Zm; @@ -1801,38 +1806,38 @@ let ElementSize = zprty.ElementSize; } -multiclass sve_int_bin_pred_log opc, string asm> { - def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; - def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; - def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_log opc, string asm, SDPatternOperator op> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, nxv16i8, nxv16i1, ZPR8, op>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, nxv8i16, nxv8i1, ZPR16, op>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, nxv4i32, nxv4i1, ZPR32, op>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, nxv2i64, nxv2i1, ZPR64, op>; } -multiclass sve_int_bin_pred_arit_0 opc, string asm> { - def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; - def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; - def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_arit_0 opc, string asm, SDPatternOperator op> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, nxv16i8, nxv16i1, ZPR8, op>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, nxv8i16, nxv8i1, ZPR16, op>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, nxv4i32, nxv4i1, ZPR32, op>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, nxv2i64, nxv2i1, ZPR64, op>; } -multiclass sve_int_bin_pred_arit_1 opc, string asm> { - def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>; - def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>; - def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_arit_1 opc, string asm, SDPatternOperator op> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, nxv16i8, nxv16i1, ZPR8, op>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, nxv8i16, nxv8i1, ZPR16, op>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, nxv4i32, nxv4i1, ZPR32, op>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, nxv2i64, nxv2i1, ZPR64, op>; } -multiclass sve_int_bin_pred_arit_2 opc, string asm> { - def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>; - def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>; - def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_arit_2 opc, string asm, SDPatternOperator op> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, nxv16i8, nxv16i1, ZPR8, op>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, nxv8i16, nxv8i1, ZPR16, op>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, nxv4i32, nxv4i1, ZPR32, op>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, nxv2i64, nxv2i1, ZPR64, op>; } // Special case for divides which are not defined for 8b/16b elements. -multiclass sve_int_bin_pred_arit_2_div opc, string asm> { - def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_arit_2_div opc, string asm, SDPatternOperator op> { + def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, nxv4i32, nxv4i1, ZPR32, op>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, nxv2i64, nxv2i1, ZPR64, op>; } //===----------------------------------------------------------------------===// @@ -3057,11 +3062,11 @@ // SVE Bitwise Logical - Unpredicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_cons_log opc, string asm> +class sve_int_bin_cons_log opc, string asm, SDPatternOperator op> : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm), asm, "\t$Zd, $Zn, $Zm", "", - []>, Sched<[]> { + [(set (nxv2i64 ZPR64:$Zd), (op (nxv2i64 ZPR64:$Zn), (nxv2i64 ZPR64:$Zm)))]>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; @@ -3074,15 +3079,20 @@ let Inst{4-0} = Zd; } -multiclass sve_int_bin_cons_log opc, string asm> { - def NAME : sve_int_bin_cons_log; +multiclass sve_int_bin_cons_log opc, string asm, SDPatternOperator op> { + // The NAME is required because it is used for other optimization patterns in the SVEInstrInfo file. + def NAME : sve_int_bin_cons_log; + + def : SVE_2_Op_Pat(NAME)>; + def : SVE_2_Op_Pat(NAME)>; + def : SVE_2_Op_Pat(NAME)>; def : InstAlias(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>; + (!cast(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>; def : InstAlias(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>; + (!cast(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>; def : InstAlias(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>; + (!cast(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>; } class sve2_int_bitwise_ternary_op_d opc, string asm> Index: llvm/test/CodeGen/AArch64/sve-int-arith-pred.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AArch64/sve-int-arith-pred.ll @@ -0,0 +1,143 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +define @add_i8( %pg, %a, %b) { +; CHECK-LABEL: add_i8: +; CHECK: add z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.add.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @add_i16( %pg, %a, %b) { +; CHECK-LABEL: add_i16: +; CHECK: add z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.add.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @add_i32( %pg, %a, %b) { +; CHECK-LABEL: add_i32: +; CHECK: add z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.add.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @add_i64( %pg, %a, %b) { +; CHECK-LABEL: add_i64: +; CHECK: add z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.add.nxv2i64( %pg, + %a, + %b) + ret %out +} + + + + +define @sub_i8( %pg, %a, %b) { +; CHECK-LABEL: sub_i8: +; CHECK: sub z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sub.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @sub_i16( %pg, %a, %b) { +; CHECK-LABEL: sub_i16: +; CHECK: sub z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sub.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @sub_i32( %pg, %a, %b) { +; CHECK-LABEL: sub_i32: +; CHECK: sub z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sub.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @sub_i64( %pg, %a, %b) { +; CHECK-LABEL: sub_i64: +; CHECK: sub z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sub.nxv2i64( %pg, + %a, + %b) + ret %out +} + + + +define @subr_i8( %pg, %a, %b) { +; CHECK-LABEL: subr_i8: +; CHECK: subr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.subr.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @subr_i16( %pg, %a, %b) { +; CHECK-LABEL: subr_i16: +; CHECK: subr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.subr.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @subr_i32( %pg, %a, %b) { +; CHECK-LABEL: subr_i32: +; CHECK: subr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.subr.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @subr_i64( %pg, %a, %b) { +; CHECK-LABEL: subr_i64: +; CHECK: subr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.subr.nxv2i64( %pg, + %a, + %b) + ret %out +} + + + +declare @llvm.aarch64.sve.add.nxv16i8(, , ) +declare @llvm.aarch64.sve.add.nxv8i16(, , ) +declare @llvm.aarch64.sve.add.nxv4i32(, , ) +declare @llvm.aarch64.sve.add.nxv2i64(, , ) + +declare @llvm.aarch64.sve.sub.nxv16i8(, , ) +declare @llvm.aarch64.sve.sub.nxv8i16(, , ) +declare @llvm.aarch64.sve.sub.nxv4i32(, , ) +declare @llvm.aarch64.sve.sub.nxv2i64(, , ) + +declare @llvm.aarch64.sve.subr.nxv16i8(, , ) +declare @llvm.aarch64.sve.subr.nxv8i16(, , ) +declare @llvm.aarch64.sve.subr.nxv4i32(, , ) +declare @llvm.aarch64.sve.subr.nxv2i64(, , ) Index: llvm/test/CodeGen/AArch64/sve-int-arith.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AArch64/sve-int-arith.ll @@ -0,0 +1,216 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +define @add_i64( %a, %b) { +; CHECK-LABEL: add_i64 +; CHECK: add z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = add %a, %b + ret %res +} + +define @add_i32( %a, %b) { +; CHECK-LABEL: add_i32 +; CHECK: add z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %res = add %a, %b + ret %res +} + +define @add_i16( %a, %b) { +; CHECK-LABEL: add_i16 +; CHECK: add z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %res = add %a, %b + ret %res +} + +define @add_i8( %a, %b) { +; CHECK-LABEL: add_i8 +; CHECK: add z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %res = add %a, %b + ret %res +} + +define @sub_i64( %a, %b) { +; CHECK-LABEL: sub_i64 +; CHECK: sub z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = sub %a, %b + ret %res +} + +define @sub_i32( %a, %b) { +; CHECK-LABEL: sub_i32 +; CHECK: sub z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %res = sub %a, %b + ret %res +} + +define @sub_i16( %a, %b) { +; CHECK-LABEL: sub_i16 +; CHECK: sub z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %res = sub %a, %b + ret %res +} + +define @sub_i8( %a, %b) { +; CHECK-LABEL: sub_i8 +; CHECK: sub z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %res = sub %a, %b + ret %res +} + +define @sqadd_i64( %a, %b) { +; CHECK-LABEL: sqadd_i64 +; CHECK: sqadd z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.sadd.sat.nxv2i64( %a, %b) + ret %res +} + +define @sqadd_i32( %a, %b) { +; CHECK-LABEL: sqadd_i32 +; CHECK: sqadd z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.sadd.sat.nxv4i32( %a, %b) + ret %res +} + +define @sqadd_i16( %a, %b) { +; CHECK-LABEL: sqadd_i16 +; CHECK: sqadd z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.sadd.sat.nxv8i16( %a, %b) + ret %res +} + +define @sqadd_i8( %a, %b) { +; CHECK-LABEL: sqadd_i8 +; CHECK: sqadd z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %res = call @llvm.sadd.sat.nxv16i8( %a, %b) + ret %res +} + + +define @sqsub_i64( %a, %b) { +; CHECK-LABEL: sqsub_i64 +; CHECK: sqsub z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.ssub.sat.nxv2i64( %a, %b) + ret %res +} + +define @sqsub_i32( %a, %b) { +; CHECK-LABEL: sqsub_i32 +; CHECK: sqsub z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.ssub.sat.nxv4i32( %a, %b) + ret %res +} + +define @sqsub_i16( %a, %b) { +; CHECK-LABEL: sqsub_i16 +; CHECK: sqsub z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.ssub.sat.nxv8i16( %a, %b) + ret %res +} + +define @sqsub_i8( %a, %b) { +; CHECK-LABEL: sqsub_i8 +; CHECK: sqsub z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %res = call @llvm.ssub.sat.nxv16i8( %a, %b) + ret %res +} + + +define @uqadd_i64( %a, %b) { +; CHECK-LABEL: uqadd_i64 +; CHECK: uqadd z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.uadd.sat.nxv2i64( %a, %b) + ret %res +} + +define @uqadd_i32( %a, %b) { +; CHECK-LABEL: uqadd_i32 +; CHECK: uqadd z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.uadd.sat.nxv4i32( %a, %b) + ret %res +} + +define @uqadd_i16( %a, %b) { +; CHECK-LABEL: uqadd_i16 +; CHECK: uqadd z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.uadd.sat.nxv8i16( %a, %b) + ret %res +} + +define @uqadd_i8( %a, %b) { +; CHECK-LABEL: uqadd_i8 +; CHECK: uqadd z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %res = call @llvm.uadd.sat.nxv16i8( %a, %b) + ret %res +} + + +define @uqsub_i64( %a, %b) { +; CHECK-LABEL: uqsub_i64 +; CHECK: uqsub z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.usub.sat.nxv2i64( %a, %b) + ret %res +} + +define @uqsub_i32( %a, %b) { +; CHECK-LABEL: uqsub_i32 +; CHECK: uqsub z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.usub.sat.nxv4i32( %a, %b) + ret %res +} + +define @uqsub_i16( %a, %b) { +; CHECK-LABEL: uqsub_i16 +; CHECK: uqsub z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %res = call @llvm.usub.sat.nxv8i16( %a, %b) + ret %res +} + +define @uqsub_i8( %a, %b) { +; CHECK-LABEL: uqsub_i8 +; CHECK: uqsub z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %res = call @llvm.usub.sat.nxv16i8( %a, %b) + ret %res +} + +declare @llvm.sadd.sat.nxv16i8(, ) +declare @llvm.sadd.sat.nxv8i16(, ) +declare @llvm.sadd.sat.nxv4i32(, ) +declare @llvm.sadd.sat.nxv2i64(, ) + +declare @llvm.ssub.sat.nxv16i8(, ) +declare @llvm.ssub.sat.nxv8i16(, ) +declare @llvm.ssub.sat.nxv4i32(, ) +declare @llvm.ssub.sat.nxv2i64(, ) + +declare @llvm.uadd.sat.nxv16i8(, ) +declare @llvm.uadd.sat.nxv8i16(, ) +declare @llvm.uadd.sat.nxv4i32(, ) +declare @llvm.uadd.sat.nxv2i64(, ) + +declare @llvm.usub.sat.nxv16i8(, ) +declare @llvm.usub.sat.nxv8i16(, ) +declare @llvm.usub.sat.nxv4i32(, ) +declare @llvm.usub.sat.nxv2i64(, ) Index: llvm/test/CodeGen/AArch64/sve-int-log.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AArch64/sve-int-log.ll @@ -0,0 +1,138 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +define @and_d( %a, %b) { +; CHECK-LABEL: and_d +; CHECK: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = and %a, %b + ret %res +} + +define @and_s( %a, %b) { +; CHECK-LABEL: and_s +; CHECK: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = and %a, %b + ret %res +} + +define @and_h( %a, %b) { +; CHECK-LABEL: and_h +; CHECK: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = and %a, %b + ret %res +} + +define @and_b( %a, %b) { +; CHECK-LABEL: and_b +; CHECK: and z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = and %a, %b + ret %res +} +define @or_d( %a, %b) { +; CHECK-LABEL: or_d +; CHECK: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = or %a, %b + ret %res +} + +define @or_s( %a, %b) { +; CHECK-LABEL: or_s +; CHECK: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = or %a, %b + ret %res +} + +define @or_h( %a, %b) { +; CHECK-LABEL: or_h +; CHECK: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = or %a, %b + ret %res +} + +define @or_b( %a, %b) { +; CHECK-LABEL: or_b +; CHECK: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = or %a, %b + ret %res +} + +define @xor_d( %a, %b) { +; CHECK-LABEL: xor_d +; CHECK: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = xor %a, %b + ret %res +} + +define @xor_s( %a, %b) { +; CHECK-LABEL: xor_s +; CHECK: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = xor %a, %b + ret %res +} + +define @xor_h( %a, %b) { +; CHECK-LABEL: xor_h +; CHECK: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = xor %a, %b + ret %res +} + +define @xor_b( %a, %b) { +; CHECK-LABEL: xor_b +; CHECK: eor z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = xor %a, %b + ret %res +} + +define @bic_d( %a, %b) { +; CHECK-LABEL: bic_d +; CHECK: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.bic.nxv2i64( %a, + %b) + ret %res +} + +define @bic_s( %a, %b) { +; CHECK-LABEL: bic_s +; CHECK: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.bic.nxv4i32( %a, + %b) + ret %res +} + +define @bic_h( %a, %b) { +; CHECK-LABEL: bic_h +; CHECK: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.bic.nxv8i16( %a, + %b) + + ret %res +} + +define @bic_b( %a, %b) { +; CHECK-LABEL: bic_b +; CHECK: bic z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.bic.nxv16i8( %a, + %b) + ret %res +} + +declare @llvm.aarch64.sve.bic.nxv2i64(, ) +declare @llvm.aarch64.sve.bic.nxv4i32(, ) +declare @llvm.aarch64.sve.bic.nxv8i16(, ) +declare @llvm.aarch64.sve.bic.nxv16i8(, )