Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9397,10 +9397,15 @@ // sext i1 (setgt iN X, -1) --> sra (not X), (N - 1) // zext i1 (setgt iN X, -1) --> srl (not X), (N - 1) SDLoc DL(N); - SDValue NotX = DAG.getNOT(DL, X, VT); - SDValue ShiftAmount = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); - auto ShiftOpcode = N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; - return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount); + unsigned ShCt = VT.getSizeInBits() - 1; + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (ShCt <= TLI.getShiftAmountThreshold(VT)) { + SDValue NotX = DAG.getNOT(DL, X, VT); + SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT); + auto ShiftOpcode = + N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL; + return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount); + } } return SDValue(); } @@ -19910,22 +19915,28 @@ auto *N2C = dyn_cast(N2.getNode()); if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) { unsigned ShCt = XType.getSizeInBits() - N2C->getAPIntValue().logBase2() - 1; - SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); - SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); - AddToWorklist(Shift.getNode()); - - if (XType.bitsGT(AType)) { - Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); + if (ShCt <= TLI.getShiftAmountThreshold(XType)) { + SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); + SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt); AddToWorklist(Shift.getNode()); - } - if (CC == ISD::SETGT) - Shift = DAG.getNOT(DL, Shift, AType); + if (XType.bitsGT(AType)) { + Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); + AddToWorklist(Shift.getNode()); + } + + if (CC == ISD::SETGT) + Shift = DAG.getNOT(DL, Shift, AType); - return DAG.getNode(ISD::AND, DL, AType, Shift, N2); + return DAG.getNode(ISD::AND, DL, AType, Shift, N2); + } } - SDValue ShiftAmt = DAG.getConstant(XType.getSizeInBits() - 1, DL, ShiftAmtTy); + unsigned ShCt = XType.getSizeInBits() - 1; + if (ShCt > TLI.getShiftAmountThreshold(XType)) + return SDValue(); + + SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt); AddToWorklist(Shift.getNode()); @@ -20035,31 +20046,29 @@ // when the condition can be materialized as an all-ones register. Any // single bit-test can be materialized as an all-ones register with // shift-left and shift-right-arith. - // TODO: The operation legality checks could be loosened to include "custom", - // but that may cause regressions for targets that do not have shift - // instructions. if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && - N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2) && - TLI.isOperationLegal(ISD::SHL, VT) && - TLI.isOperationLegal(ISD::SRA, VT)) { + N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) { SDValue AndLHS = N0->getOperand(0); auto *ConstAndRHS = dyn_cast(N0->getOperand(1)); if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { // Shift the tested bit over the sign bit. const APInt &AndMask = ConstAndRHS->getAPIntValue(); - SDValue ShlAmt = - DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS), - getShiftAmountTy(AndLHS.getValueType())); - SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); - - // Now arithmetic right shift it all the way over, so the result is either - // all-ones, or zero. - SDValue ShrAmt = - DAG.getConstant(AndMask.getBitWidth() - 1, SDLoc(Shl), - getShiftAmountTy(Shl.getValueType())); - SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); - - return DAG.getNode(ISD::AND, DL, VT, Shr, N3); + unsigned ShCt = AndMask.getBitWidth() - 1; + if (ShCt <= TLI.getShiftAmountThreshold(VT)) { + SDValue ShlAmt = + DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS), + getShiftAmountTy(AndLHS.getValueType())); + SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); + + // Now arithmetic right shift it all the way over, so the result is + // either all-ones, or zero. + SDValue ShrAmt = + DAG.getConstant(ShCt, SDLoc(Shl), + getShiftAmountTy(Shl.getValueType())); + SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); + + return DAG.getNode(ISD::AND, DL, VT, Shr, N3); + } } } @@ -20101,10 +20110,13 @@ if (N2C->isOne()) return Temp; + unsigned ShCt = N2C->getAPIntValue().logBase2(); + if (ShCt > TLI.getShiftAmountThreshold(VT)) + return SDValue(); + // shl setcc result by log2 n2c return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, - DAG.getConstant(N2C->getAPIntValue().logBase2(), - SDLoc(Temp), + DAG.getConstant(ShCt, SDLoc(Temp), getShiftAmountTy(Temp.getValueType()))); } Index: llvm/test/CodeGen/MSP430/shift-amount-threshold.ll =================================================================== --- llvm/test/CodeGen/MSP430/shift-amount-threshold.ll +++ llvm/test/CodeGen/MSP430/shift-amount-threshold.ll @@ -1,7 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=msp430-- < %s | FileCheck %s -define i16 @testSimplifySetCC_0(i16 %a) { +; Prevent the following conversion in TargetLowering::SimplifySetCC +; (X & 8) != 0 --> (X & 8) >> 3 +define i16 @testSimplifySetCC_0(i16 %x) { ; CHECK-LABEL: testSimplifySetCC_0: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: bit #32, r12 @@ -9,13 +11,15 @@ ; CHECK-NEXT: and #1, r12 ; CHECK-NEXT: ret entry: - %and = and i16 %a, 32 + %and = and i16 %x, 32 %cmp = icmp ne i16 %and, 0 %conv = zext i1 %cmp to i16 ret i16 %conv } -define i16 @testSimplifySetCC_1(i16 %a) { +; Prevent the following conversion in TargetLowering::SimplifySetCC +; (X & 8) == 8 --> (X & 8) >> 3 +define i16 @testSimplifySetCC_1(i16 %x) { ; CHECK-LABEL: testSimplifySetCC_1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: bit #32, r12 @@ -23,145 +27,119 @@ ; CHECK-NEXT: and #1, r12 ; CHECK-NEXT: ret entry: - %and = and i16 %a, 32 + %and = and i16 %x, 32 %cmp = icmp eq i16 %and, 32 %conv = zext i1 %cmp to i16 ret i16 %conv } -define i16 @testSiymplifySelect(i16 %a) { -; CHECK-LABEL: testSiymplifySelect: +; Prevent the following conversion in DAGCombiner::SimplifySelectCC +; (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) +define i16 @testSiymplifySelectCC_0(i16 %x, i16 %a) { +; CHECK-LABEL: testSiymplifySelectCC_0: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: mov r12, r13 +; CHECK-NEXT: mov r12, r14 ; CHECK-NEXT: clr r12 -; CHECK-NEXT: bit #2048, r13 +; CHECK-NEXT: bit #2048, r14 ; CHECK-NEXT: jeq .LBB2_2 ; CHECK-NEXT: ; %bb.1: ; %entry -; CHECK-NEXT: mov #3, r12 +; CHECK-NEXT: mov r13, r12 ; CHECK-NEXT: .LBB2_2: ; %entry ; CHECK-NEXT: ret entry: - %and = and i16 %a, 2048 + %and = and i16 %x, 2048 %cmp = icmp eq i16 %and, 0 - %cond = select i1 %cmp, i16 0, i16 3 + %cond = select i1 %cmp, i16 0, i16 %a ret i16 %cond } -define i16 @testExtendSignBit(i16 %a) { -; CHECK-LABEL: testExtendSignBit: +; Prevent the following conversion in DAGCombiner foldExtendedSignBitTest +; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1) +define i16 @testExtendSignBit_0(i16 %x) { +; CHECK-LABEL: testExtendSignBit_0: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: inv r12 -; CHECK-NEXT: swpb r12 -; CHECK-NEXT: mov.b r12, r12 -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: ret -entry: - %cmp = icmp sgt i16 %a, -1 - %cond = select i1 %cmp, i16 1, i16 0 - ret i16 %cond -} - -define i16 @testShiftAnd_0(i16 %a) { -; CHECK-LABEL: testShiftAnd_0: -; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: swpb r12 -; CHECK-NEXT: sxt r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 +; CHECK-NEXT: mov r12, r13 +; CHECK-NEXT: mov #-1, r12 +; CHECK-NEXT: tst r13 +; CHECK-NEXT: jge .LBB3_2 +; CHECK-NEXT: ; %bb.1: ; %entry +; CHECK-NEXT: clr r12 +; CHECK-NEXT: .LBB3_2: ; %entry ; CHECK-NEXT: ret entry: - %cmp = icmp slt i16 %a, 0 - %cond = select i1 %cmp, i16 -1, i16 0 + %cmp = icmp sgt i16 %x, -1 + %cond = sext i1 %cmp to i16 ret i16 %cond } -define i16 @testShiftAnd_1(i16 %a) { -; CHECK-LABEL: testShiftAnd_1: +; Prevent the following conversion in DAGCombiner foldExtendedSignBitTest +; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1) +define i16 @testExtendSignBit_1(i16 %x) { +; CHECK-LABEL: testExtendSignBit_1: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: swpb r12 -; CHECK-NEXT: mov.b r12, r12 -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 +; CHECK-NEXT: mov r12, r13 +; CHECK-NEXT: mov #1, r12 +; CHECK-NEXT: tst r13 +; CHECK-NEXT: jge .LBB4_2 +; CHECK-NEXT: ; %bb.1: ; %entry +; CHECK-NEXT: clr r12 +; CHECK-NEXT: .LBB4_2: ; %entry ; CHECK-NEXT: ret entry: - %cmp = icmp slt i16 %a, 0 - %cond = select i1 %cmp, i16 1, i16 0 + %cmp = icmp sgt i16 %x, -1 + %cond = zext i1 %cmp to i16 ret i16 %cond } -define i16 @testShiftAnd_2(i16 %a) { -; CHECK-LABEL: testShiftAnd_2: +; Prevent the following conversion in DAGCombiner::foldSelectCCToShiftAnd +; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A +define i16 @testShiftAnd_0(i16 %x, i16 %a) { +; CHECK-LABEL: testShiftAnd_0: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: swpb r12 -; CHECK-NEXT: mov.b r12, r12 -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: and #2, r12 +; CHECK-NEXT: tst r12 +; CHECK-NEXT: jl .LBB5_2 +; CHECK-NEXT: ; %bb.1: ; %entry +; CHECK-NEXT: clr r13 +; CHECK-NEXT: .LBB5_2: ; %entry +; CHECK-NEXT: mov r13, r12 ; CHECK-NEXT: ret entry: - %cmp = icmp slt i16 %a, 0 - %cond = select i1 %cmp, i16 2, i16 0 + %cmp = icmp slt i16 %x, 0 + %cond = select i1 %cmp, i16 %a, i16 0 ret i16 %cond } -define i16 @testShiftAnd_3(i16 %a) { -; CHECK-LABEL: testShiftAnd_3: +; Prevent the following conversion in DAGCombiner::foldSelectCCToShiftAnd +; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit +define i16 @testShiftAnd_1(i16 %x) { +; CHECK-LABEL: testShiftAnd_1: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: swpb r12 -; CHECK-NEXT: sxt r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: and #3, r12 +; CHECK-NEXT: mov r12, r13 +; CHECK-NEXT: mov #32, r12 +; CHECK-NEXT: tst r13 +; CHECK-NEXT: jl .LBB6_2 +; CHECK-NEXT: ; %bb.1: ; %entry +; CHECK-NEXT: clr r12 +; CHECK-NEXT: .LBB6_2: ; %entry ; CHECK-NEXT: ret entry: - %cmp = icmp slt i16 %a, 0 - %cond = select i1 %cmp, i16 3, i16 0 + %cmp = icmp slt i16 %x, 0 + %cond = select i1 %cmp, i16 32, i16 0 ret i16 %cond } -define i16 @testShiftAnd_4(i16 %a, i16 %b) { -; CHECK-LABEL: testShiftAnd_4: +; Prevent the following conversion in DAGCombiner::SimplifySelectCC +; select C, 16, 0 -> shl C, 4 +define i16 @estSiymplifySelectCC_1(i16 %a, i16 %b) { +; CHECK-LABEL: estSiymplifySelectCC_1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: mov r12, r14 -; CHECK-NEXT: mov #1, r12 +; CHECK-NEXT: mov #32, r12 ; CHECK-NEXT: cmp r14, r13 -; CHECK-NEXT: jl .LBB8_2 +; CHECK-NEXT: jl .LBB7_2 ; CHECK-NEXT: ; %bb.1: ; %entry ; CHECK-NEXT: clr r12 -; CHECK-NEXT: .LBB8_2: ; %entry -; CHECK-NEXT: add r12, r12 -; CHECK-NEXT: add r12, r12 -; CHECK-NEXT: add r12, r12 -; CHECK-NEXT: add r12, r12 -; CHECK-NEXT: add r12, r12 +; CHECK-NEXT: .LBB7_2: ; %entry ; CHECK-NEXT: ret entry: %cmp = icmp sgt i16 %a, %b