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Differential D69039

[AArch64,Assembler] Compiler support for ID_MMFR5_EL1
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Authored by MarkMurrayARM on Oct 16 2019, 7:11 AM.

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vhscampos
Commits
rGb6dd12862177: [AArch64,Assembler] Compiler support for ID_MMFR5_EL1
rL375010: [AArch64,Assembler] Compiler support for ID_MMFR5_EL1
Summary

Add read-only system register ID_MMFR5_EL1 and unit tests.

Diff Detail

Event Timeline

MarkMurrayARM created this revision.Oct 16 2019, 7:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 16 2019, 7:11 AM
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B39646: Diff 225217.Oct 16 2019, 7:11 AM
vhscampos accepted this revision.Oct 16 2019, 7:41 AM
This revision is now accepted and ready to land.Oct 16 2019, 7:41 AM
Closed by commit rGb6dd12862177: [AArch64,Assembler] Compiler support for ID_MMFR5_EL1 (authored by MarkMurrayARM). · Explain WhyOct 16 2019, 9:04 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
1 line
test/
MC/
AArch64/
4 lines
2 lines
Disassembler/
AArch64/
2 lines

Diff 225240

llvm/lib/Target/AArch64/AArch64SystemOperands.td

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def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>;
def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>;
def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>;
def : ROSysReg<"ID_MMFR5_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b110>;
// Trace registers // Trace registers
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>;
def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>;
def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>;
def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>;
def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>;
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llvm/test/MC/AArch64/basic-a64-diagnostics.s

Show First 20 Lines • Show All 3,575 Lines • ▼ Show 20 Lines// write-only registers actually are.
msr ID_PFR1_EL1, x12 msr ID_PFR1_EL1, x12
msr ID_DFR0_EL1, x12 msr ID_DFR0_EL1, x12
msr ID_AFR0_EL1, x12 msr ID_AFR0_EL1, x12
msr ID_MMFR0_EL1, x12 msr ID_MMFR0_EL1, x12
msr ID_MMFR1_EL1, x12 msr ID_MMFR1_EL1, x12
msr ID_MMFR2_EL1, x12 msr ID_MMFR2_EL1, x12
msr ID_MMFR3_EL1, x12 msr ID_MMFR3_EL1, x12
msr ID_MMFR4_EL1, x12 msr ID_MMFR4_EL1, x12
msr ID_MMFR5_EL1, x12
msr ID_ISAR0_EL1, x12 msr ID_ISAR0_EL1, x12
msr ID_ISAR1_EL1, x12 msr ID_ISAR1_EL1, x12
msr ID_ISAR2_EL1, x12 msr ID_ISAR2_EL1, x12
msr ID_ISAR3_EL1, x12 msr ID_ISAR3_EL1, x12
msr ID_ISAR4_EL1, x12 msr ID_ISAR4_EL1, x12
msr ID_ISAR5_EL1, x12 msr ID_ISAR5_EL1, x12
msr MVFR0_EL1, x12 msr MVFR0_EL1, x12
msr MVFR1_EL1, x12 msr MVFR1_EL1, x12
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// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR3_EL1, x12 // CHECK-ERROR-NEXT: msr ID_MMFR3_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR4_EL1, x12 // CHECK-ERROR-NEXT: msr ID_MMFR4_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR5_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR0_EL1, x12 // CHECK-ERROR-NEXT: msr ID_ISAR0_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR1_EL1, x12 // CHECK-ERROR-NEXT: msr ID_ISAR1_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR2_EL1, x12 // CHECK-ERROR-NEXT: msr ID_ISAR2_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
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llvm/test/MC/AArch64/basic-a64-instructions.s

Show First 20 Lines • Show All 4,289 Lines • ▼ Show 20 Lines// CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 // encoding: [0xcc,0xef,0x1b,0xd5]
mrs x9, ID_PFR1_EL1 mrs x9, ID_PFR1_EL1
mrs x9, ID_DFR0_EL1 mrs x9, ID_DFR0_EL1
mrs x9, ID_AFR0_EL1 mrs x9, ID_AFR0_EL1
mrs x9, ID_MMFR0_EL1 mrs x9, ID_MMFR0_EL1
mrs x9, ID_MMFR1_EL1 mrs x9, ID_MMFR1_EL1
mrs x9, ID_MMFR2_EL1 mrs x9, ID_MMFR2_EL1
mrs x9, ID_MMFR3_EL1 mrs x9, ID_MMFR3_EL1
mrs x9, ID_MMFR4_EL1 mrs x9, ID_MMFR4_EL1
mrs x9, ID_MMFR5_EL1
mrs x9, ID_ISAR0_EL1 mrs x9, ID_ISAR0_EL1
mrs x9, ID_ISAR1_EL1 mrs x9, ID_ISAR1_EL1
mrs x9, ID_ISAR2_EL1 mrs x9, ID_ISAR2_EL1
mrs x9, ID_ISAR3_EL1 mrs x9, ID_ISAR3_EL1
mrs x9, ID_ISAR4_EL1 mrs x9, ID_ISAR4_EL1
mrs x9, ID_ISAR5_EL1 mrs x9, ID_ISAR5_EL1
mrs x9, MVFR0_EL1 mrs x9, MVFR0_EL1
mrs x9, MVFR1_EL1 mrs x9, MVFR1_EL1
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// CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} // encoding: [0xc9,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} // encoding: [0xc9,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}} // encoding: [0xc9,0x03,0x38,0xd5]
// CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} // encoding: [0x69,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} // encoding: [0x69,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} // encoding: [0x89,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} // encoding: [0x89,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} // encoding: [0xa9,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} // encoding: [0xa9,0x02,0x38,0xd5]
// CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} // encoding: [0x09,0x03,0x38,0xd5] // CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} // encoding: [0x09,0x03,0x38,0xd5]
// CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} // encoding: [0x29,0x03,0x38,0xd5] // CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} // encoding: [0x29,0x03,0x38,0xd5]
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llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

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# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} # CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}}
# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} # CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}}
# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} # CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}}
# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} # CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} # CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} # CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} # CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
# CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} # CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}
# CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}}
# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} # CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} # CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} # CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} # CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}}
# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} # CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}}
# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} # CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}}
# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} # CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}}
# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} # CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}}
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0x29 0x1 0x38 0xd5 0x29 0x1 0x38 0xd5
0x49 0x1 0x38 0xd5 0x49 0x1 0x38 0xd5
0x69 0x1 0x38 0xd5 0x69 0x1 0x38 0xd5
0x89 0x1 0x38 0xd5 0x89 0x1 0x38 0xd5
0xa9 0x1 0x38 0xd5 0xa9 0x1 0x38 0xd5
0xc9 0x1 0x38 0xd5 0xc9 0x1 0x38 0xd5
0xe9 0x1 0x38 0xd5 0xe9 0x1 0x38 0xd5
0xc9 0x2 0x38 0xd5 0xc9 0x2 0x38 0xd5
0xc9 0x3 0x38 0xd5
0x9 0x2 0x38 0xd5 0x9 0x2 0x38 0xd5
0x29 0x2 0x38 0xd5 0x29 0x2 0x38 0xd5
0x49 0x2 0x38 0xd5 0x49 0x2 0x38 0xd5
0x69 0x2 0x38 0xd5 0x69 0x2 0x38 0xd5
0x89 0x2 0x38 0xd5 0x89 0x2 0x38 0xd5
0xa9 0x2 0x38 0xd5 0xa9 0x2 0x38 0xd5
0x9 0x3 0x38 0xd5 0x9 0x3 0x38 0xd5
0x29 0x3 0x38 0xd5 0x29 0x3 0x38 0xd5
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