diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -335,7 +335,7 @@ int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset, bool *OutUseUnscaledOp = nullptr, unsigned *OutUnscaledOp = nullptr, - int *EmittableOffset = nullptr); + int64_t *EmittableOffset = nullptr); static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -3368,7 +3368,7 @@ StackOffset &SOffset, bool *OutUseUnscaledOp, unsigned *OutUnscaledOp, - int *EmittableOffset) { + int64_t *EmittableOffset) { // Set output values in case of early exit. if (EmittableOffset) *EmittableOffset = 0; @@ -3430,7 +3430,7 @@ "Cannot have remainder when using unscaled op"); assert(MinOff < MaxOff && "Unexpected Min/Max offsets"); - int NewOffset = Offset / Scale; + int64_t NewOffset = Offset / Scale; if (MinOff <= NewOffset && NewOffset <= MaxOff) Offset = Remainder; else { @@ -3471,7 +3471,7 @@ return true; } - int NewOffset; + int64_t NewOffset; unsigned UnscaledOp; bool UseUnscaledOp; int Status = isAArch64FrameOffsetLegal(MI, Offset, &UseUnscaledOp, diff --git a/llvm/test/CodeGen/AArch64/framelayout-large-offset.mir b/llvm/test/CodeGen/AArch64/framelayout-large-offset.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/framelayout-large-offset.mir @@ -0,0 +1,144 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - +--- +name: framelayout_large_offset +tracksRegLiveness: true +fixedStack: + - { id: 0, offset: 2147483648, size: 1} +body: | + bb.0: + $x0 = LDRXui %fixed-stack.0, 0 + RET_ReallyLR +... +# CHECK: framelayout_large_offset: +# CHECK: sub x8, sp, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #4095, lsl #12 +# CHECK-NEXT: sub x8, x8, #127, lsl #12 +# CHECK-NEXT: sub x8, x8, #3840 +# CHECK-NEXT: ldur x0, [x8, #-256] +# CHECK-NEXT: ret