Index: lib/CodeGen/MIRParser/MIParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIParser.cpp +++ lib/CodeGen/MIRParser/MIParser.cpp @@ -1437,6 +1437,7 @@ if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty) return error("inconsistent type for generic virtual register"); + MRI.setRegClassOrRegBank(Reg, static_cast(nullptr)); MRI.setType(Reg, Ty); } } @@ -1455,6 +1456,7 @@ if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty) return error("inconsistent type for generic virtual register"); + MRI.setRegClassOrRegBank(Reg, static_cast(nullptr)); MRI.setType(Reg, Ty); } else if (Register::isVirtualRegister(Reg)) { // Generic virtual registers must have a type. Index: test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir =================================================================== --- test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir +++ test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir @@ -1,11 +1,11 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 -# Check there are COPY instructions surrounding ADDVI_W instruction. -# MIParser does not set RegClassOrRegBank for parsed virtual registers. +# Check there are no COPY instructions surrounding ADDVI_W instruction. +# MIParser sets RegClassOrRegBank for parsed virtual registers. # Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w) -# gets selected into ADDVI_W creates additional copies. -# FixMe: Make sure this test has same output as setRegClassOrRegBank.ll. +# gets selected into ADDVI_W works as expected. +# Check that setRegClassOrRegBank.ll has same output. --- | @@ -25,11 +25,9 @@ ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>) - ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25 - ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]] - ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25 + ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 Index: test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir =================================================================== --- test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir +++ test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir @@ -151,11 +151,9 @@ ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>) - ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3 - ; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]] - ; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b(<16 x s8>) = ADDVI_B [[LOAD]](<16 x s8>), 3 + ; P5600: G_STORE [[ADDVI_B]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 @@ -177,11 +175,9 @@ ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>) - ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18 - ; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]] - ; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18 + ; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 @@ -203,11 +199,9 @@ ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>) - ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25 - ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]] - ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25 + ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 @@ -229,11 +223,9 @@ ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>) - ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31 - ; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]] - ; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d(<2 x s64>) = ADDVI_D [[LOAD]](<2 x s64>), 31 + ; P5600: G_STORE [[ADDVI_D]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 Index: test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir =================================================================== --- test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir +++ test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir @@ -343,10 +343,9 @@ ; FP32-LABEL: name: u32tof32 ; FP32: liveins: $a0 - ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP32: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0 ; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200 - ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32) - ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32) + ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY]](s32), [[C]](s32) ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]] ; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64) @@ -354,10 +353,9 @@ ; FP32: RetRA implicit $f0 ; FP64-LABEL: name: u32tof32 ; FP64: liveins: $a0 - ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP64: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0 ; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200 - ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32) - ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32) + ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY]](s32), [[C]](s32) ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]] ; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64) @@ -501,20 +499,18 @@ ; FP32-LABEL: name: u32tof64 ; FP32: liveins: $a0 - ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP32: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0 ; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200 - ; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32) - ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32) + ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY]](s32), [[C]](s32) ; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]] ; FP32: $d0 = COPY [[FSUB]](s64) ; FP32: RetRA implicit $d0 ; FP64-LABEL: name: u32tof64 ; FP64: liveins: $a0 - ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; FP64: [[COPY:%[0-9]+]]:gpr32(s32) = COPY $a0 ; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200 - ; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32) - ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32) + ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY]](s32), [[C]](s32) ; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]] ; FP64: $d0 = COPY [[FSUB]](s64)