Index: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -178,7 +178,9 @@
     if (OldIdx != -1) {
       assert(OldIdx == NumOperands);
       assert(isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI));
-      DPPInst.addReg(CombOldVGPR.Reg, 0, CombOldVGPR.SubReg);
+      auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);
+      DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
+                     CombOldVGPR.SubReg);
       ++NumOperands;
     } else {
       // TODO: this discards MAC/FMA instructions for now, let's add it later
Index: llvm/test/CodeGen/AMDGPU/dpp_combine.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/dpp_combine.mir
+++ llvm/test/CodeGen/AMDGPU/dpp_combine.mir
@@ -512,7 +512,7 @@
 ...
 
 # CHECK-LABEL: name: add_old_subreg_undef
-# CHECK: %5:vgpr_32 = V_ADD_U32_dpp %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
+# CHECK: %5:vgpr_32 = V_ADD_U32_dpp undef %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
 
 name:            add_old_subreg_undef
 tracksRegLiveness: true
@@ -551,3 +551,14 @@
     %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $exec
 ...
+
+# Test an undef old operand
+# CHECK-LABEL: name: dpp_undef_old
+# CHECK: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec
+name: dpp_undef_old
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
+...