Index: include/llvm/CodeGen/LiveIntervals.h
===================================================================
--- include/llvm/CodeGen/LiveIntervals.h
+++ include/llvm/CodeGen/LiveIntervals.h
@@ -469,7 +469,7 @@
 
     void computeLiveInRegUnits();
     void computeRegUnitRange(LiveRange&, unsigned Unit);
-    void computeVirtRegInterval(LiveInterval&);
+    bool computeVirtRegInterval(LiveInterval&);
 
     using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
     void extendSegmentsToUses(LiveRange &Segments,
Index: lib/CodeGen/LiveIntervals.cpp
===================================================================
--- lib/CodeGen/LiveIntervals.cpp
+++ lib/CodeGen/LiveIntervals.cpp
@@ -191,12 +191,12 @@
 }
 
 /// Compute the live interval of a virtual register, based on defs and uses.
-void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
+bool LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
   assert(LRCalc && "LRCalc not initialized.");
   assert(LI.empty() && "Should only compute empty intervals.");
   LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
   LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
-  computeDeadValues(LI, nullptr);
+  return computeDeadValues(LI, nullptr);
 }
 
 void LiveIntervals::computeVirtRegs() {
@@ -204,7 +204,12 @@
     unsigned Reg = Register::index2VirtReg(i);
     if (MRI->reg_nodbg_empty(Reg))
       continue;
-    createAndComputeVirtRegInterval(Reg);
+    LiveInterval &LI = createEmptyInterval(Reg);
+    bool NeedSplit = computeVirtRegInterval(LI);
+    if (NeedSplit) {
+      SmallVector<LiveInterval*, 8> SplitLIs;
+      splitSeparateComponents(LI, SplitLIs);
+    }
   }
 }
 
@@ -500,6 +505,8 @@
 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
                                       SmallVectorImpl<MachineInstr*> *dead) {
   bool MayHaveSplitComponents = false;
+  bool HaveDeadDef = false;
+
   for (VNInfo *VNI : LI.valnos) {
     if (VNI->isUnused())
       continue;
@@ -530,6 +537,10 @@
       MachineInstr *MI = getInstructionFromIndex(Def);
       assert(MI && "No instruction defining live value");
       MI->addRegisterDead(LI.reg, TRI);
+      if (HaveDeadDef)
+        MayHaveSplitComponents = true;
+      HaveDeadDef = true;
+
       if (dead && MI->allDefsAreDead()) {
         LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
         dead->push_back(MI);
Index: test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir
@@ -0,0 +1,19 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+# There are multiple dead defs of the same virtual register. Make sure
+# the intervals are split during the initial live range computation.
+
+---
+name:            multiple_connected_components_dead
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: multiple_connected_components_dead
+    ; CHECK: dead %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK: dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+
+...
+
Index: test/DebugInfo/WebAssembly/dbg-value-move-reg-stackify.mir
===================================================================
--- test/DebugInfo/WebAssembly/dbg-value-move-reg-stackify.mir
+++ test/DebugInfo/WebAssembly/dbg-value-move-reg-stackify.mir
@@ -1,10 +1,10 @@
 # RUN: llc < %s -run-pass=wasm-reg-stackify -x=mir 2>&1 | FileCheck %s
 
 # CHECK: body:
-# CHECK: %1:i32 = I32_WRAP_I64 %0,
-# CHECK-NEXT: DBG_VALUE %1,
-# CHECK-NEXT: %1:i32 = CALL_i32 @bar,
-# CHECK-NEXT: DBG_VALUE %1,
+# CHECK: dead %3:i32 = I32_WRAP_I64 %0,
+# CHECK-NEXT: DBG_VALUE %1:i32
+# CHECK-NEXT: dead %2:i32 = CALL_i32 @bar,
+# CHECK-NEXT: DBG_VALUE %1:i32,
 # CHECK-NEXT: %[[NEWREG:.*]]:i32 = CALL_i32 @bar,
 # CHECK-NEXT: DBG_VALUE %[[NEWREG]],
 # CHECK-NEXT: CALL_VOID @foo, %[[NEWREG]],
Index: test/DebugInfo/X86/live-debug-vars-discard-invalid.mir
===================================================================
--- test/DebugInfo/X86/live-debug-vars-discard-invalid.mir
+++ test/DebugInfo/X86/live-debug-vars-discard-invalid.mir
@@ -1,5 +1,4 @@
-# FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39481.
-# RUN: llc -mtriple=x86_64-linux-gnu -start-before greedy -stop-after virtregrewriter -o - -verify-machineinstrs=0 %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -start-before greedy -stop-after virtregrewriter -o - -verify-machineinstrs %s | FileCheck %s
 
 --- |
   ; ModuleID = '<stdin>'
@@ -115,7 +114,7 @@
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
 # CHECK-NEXT:   dead renamable $rcx = IMPLICIT_DEF
-# CHECK-NEXT:   DBG_VALUE $rcx, $noreg, !18, !DIExpression()
+# CHECK-NEXT:   DBG_VALUE $noreg, $noreg, !18, !DIExpression()
 
 # CHECK-LABEL: bb.3:
 # CHECK:        dead renamable $rcx = IMPLICIT_DEF