diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -787,6 +787,21 @@
     SpillsKnownBit = true;
     break;
   default:
+    // On Power9, we can use SETB to extract the LT bit. This only works for
+    // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
+    // of the bit we care about (32-bit sign bit) will be set to the value of
+    // the LT bit (regardless of the other bits in the CR field).
+    if (Subtarget.isISA3_0()) {
+      if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
+          SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
+          SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
+          SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
+        BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
+          .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
+        break;
+      }
+    }
+
     // We need to move the CR field that contains the CR bit we are spilling.
     // The super register may not be explicitly defined (i.e. it can be defined
     // by a CR-logical that only defines the subreg) so we state that the CR
diff --git a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
@@ -0,0 +1,56 @@
+; NOTE: This test case aims to test the sequence of spilling the CR[0-7]LT bits
+; NOTE: on POWER9 using the setb instruction.
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
+; RUN:     | FileCheck %s --check-prefix=CHECK-P8
+
+define void @p9_setb_spill() {
+; CHECK-P9-LABEL: p9_setb_spill:
+; CHECK-P9:       # %bb.1: # %if.then
+; CHECK-P9-DAG:    crnor 4*cr[[CREG:.*]]+lt, eq, eq
+; CHECK-P9-DAG:    setb [[REG1:.*]], cr[[CREG]]
+; CHECK-P9-DAG:    stw [[REG1]]
+; CHECK-P9:        blr
+; CHECK-P9:        .LBB0_4: # %if.then1
+;
+; CHECK-P8-LABEL: p9_setb_spill:
+; CHECK-P8:       # %bb.1: # %if.then
+; CHECK-P8-DAG:    crnor 4*cr[[CREG2:.*]]+lt, eq, eq
+; CHECK-P8-DAG:    mfocrf [[REG2:.*]],
+; CHECK-P8-DAG:    rlwinm [[REG2]], [[REG2]]
+; CHECK-P8-DAG:    stw [[REG2]]
+; CHECK-P8:        blr
+; CHECK-P8:        .LBB0_4: # %if.then1
+entry:
+  br i1 undef, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call signext i32 bitcast (i32 (...)* @fn_call to i32 ()*)()
+  %cmp1 = icmp ne i32 %call, 0
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %off0 = phi i1 [ %cmp1, %if.then ], [ false, %entry ]
+  tail call void asm sideeffect "#Clobber", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}"()
+  %off0.not = xor i1 %off0, true
+  %or = or i1 false, %off0.not
+  br i1 %or, label %if.end2, label %if.then1
+
+if.then1:                                         ; preds = %if.end
+  unreachable
+
+if.end2:                                         ; preds = %if.end
+  ret void
+}
+
+declare signext i32 @fn_call(...)