Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5665,7 +5665,16 @@
       if (RI.hasAGPRs(NewDstRC))
         return nullptr;
 
-      NewDstRC = RI.getEquivalentAGPRClass(NewDstRC);
+      switch (Inst.getOpcode()) {
+      case AMDGPU::PHI:
+      case AMDGPU::REG_SEQUENCE:
+      case AMDGPU::INSERT_SUBREG:
+        NewDstRC = RI.getEquivalentAGPRClass(NewDstRC);
+        break;
+      default:
+        NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
+      }
+
       if (!NewDstRC)
         return nullptr;
     } else {
Index: llvm/trunk/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/fold_acc_copy_into_valu.mir
@@ -0,0 +1,15 @@
+# RUN: llc -march=amdgcn -mcpu=gfx908 -o - -run-pass si-fix-sgpr-copies -verify-machineinstrs %s | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL: fold_acc_copy_into_valu
+# GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY %0.sub0
+# GCN: %2:vgpr_32 = V_AND_B32_e32 [[COPY]], undef %3:vgpr_32, implicit $exec
+---
+name:            fold_acc_copy_into_valu
+body:             |
+  bb.0.entry:
+
+    %0:areg_1024 = IMPLICIT_DEF
+    %1:sreg_32_xm0 = COPY %0.sub0
+    %3:vgpr_32 = V_AND_B32_e32 %1, undef %2:vgpr_32, implicit $exec
+
+...
Index: llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
@@ -1,5 +1,5 @@
 ; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck -check-prefix=ERR %s
-; RUN: not llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s
+; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck -check-prefix=GCN %s
 
 ; ERR: error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
 ; GCN: ; illegal copy v1 to s9
@@ -43,7 +43,8 @@
 }
 
 ; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
-; GCN: ; illegal copy a1 to s9
+; GCN: v_accvgpr_read_b32 [[COPY1:v[0-9]+]], a1
+; GCN: ; illegal copy [[COPY1]] to s9
 define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_i32() #1 {
   %agpr = call i32 asm sideeffect "; def $0", "=${a1}"()
   call void asm sideeffect "; use $0", "${s9}"(i32 %agpr)
@@ -51,7 +52,9 @@
 }
 
 ; ERR: error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
-; GCN: ; illegal copy a[0:1] to s[10:11]
+; GCN-DAG: v_accvgpr_read_b32 v[[COPY1L:[0-9]+]], a0
+; GCN-DAG: v_accvgpr_read_b32 v[[COPY1H:[0-9]+]], a1
+; GCN: ; illegal copy v{{\[}}[[COPY1L]]:[[COPY1H]]] to s[10:11]
 define amdgpu_kernel void @illegal_agpr_to_sgpr_copy_v2i32() #1 {
   %vgpr = call <2 x i32> asm sideeffect "; def $0", "=${a[0:1]}"()
   call void asm sideeffect "; use $0", "${s[10:11]}"(<2 x i32> %vgpr)