Index: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1095,6 +1095,7 @@
   case 106: return createRegOperand(VCC);
   case 108: return createRegOperand(TBA);
   case 110: return createRegOperand(TMA);
+  case 125: return createRegOperand(SGPR_NULL);
   case 126: return createRegOperand(EXEC);
   case 235: return createRegOperand(SRC_SHARED_BASE);
   case 236: return createRegOperand(SRC_SHARED_LIMIT);
Index: llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
+
+# GFX10: s_ashr_i64 s[0:1], null, s0     ; encoding: [0x7d,0x00,0x80,0x91]
+0x7d,0x00,0x80,0x91
+
+# GFX10: s_and_b64 s[0:1], null, null    ; encoding: [0x7d,0x7d,0x80,0x87]
+0x7d,0x7d,0x80,0x87