diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -117,8 +117,6 @@
 
           if (!AfterBBI->modifiesRegister(Reg, TRI))
             continue;
-          assert(DeadOrKillToUnset &&
-                 "Shouldn't overwrite a register before it is killed");
           // Finish scanning because Reg is overwritten by a non-load
           // instruction.
           if (AfterBBI->getOpcode() != Opc)
@@ -134,12 +132,15 @@
           // It loads same immediate value to the same Reg, which is redundant.
           // We would unset kill flag in previous Reg usage to extend live range
           // of Reg first, then remove the redundancy.
-          LLVM_DEBUG(dbgs() << " Unset dead/kill flag of " << *DeadOrKillToUnset
-                            << " from " << *DeadOrKillToUnset->getParent());
-          if (DeadOrKillToUnset->isDef())
-            DeadOrKillToUnset->setIsDead(false);
-          else
-            DeadOrKillToUnset->setIsKill(false);
+          if (DeadOrKillToUnset) {
+            LLVM_DEBUG(dbgs()
+                       << " Unset dead/kill flag of " << *DeadOrKillToUnset
+                       << " from " << *DeadOrKillToUnset->getParent());
+            if (DeadOrKillToUnset->isDef())
+              DeadOrKillToUnset->setIsDead(false);
+            else
+              DeadOrKillToUnset->setIsKill(false);
+          }
           DeadOrKillToUnset =
               AfterBBI->findRegisterDefOperand(Reg, true, true, TRI);
           if (DeadOrKillToUnset)
diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir
--- a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir
@@ -346,3 +346,25 @@
     BLR8 implicit $lr8, implicit $rm
 
 ...
+---
+name:            overwrite_reg_before_killed
+alignment:       16
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x1
+
+    ; CHECK-LABEL: name: overwrite_reg_before_killed
+    ; CHECK: liveins: $x1
+    ; CHECK: renamable $x3 = LI8 0
+    ; CHECK: STD renamable $x3, 16, $x1
+    ; CHECK: STD killed renamable $x3, 8, $x1
+    ; CHECK: BLR8 implicit $lr8, implicit $rm
+    renamable $x3 = LI8 0
+    STD renamable $x3, 16, $x1
+    renamable $x3 = LI8 0
+    STD killed renamable $x3, 8, $x1
+    BLR8 implicit $lr8, implicit $rm
+
+...