Index: ../llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- ../llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ ../llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -190,7 +190,7 @@
   }
 
   bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
-                           unsigned ListNo, bool IsPop = false);
+                           unsigned ListNo);
   bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
                            unsigned ListNo);
 
@@ -6021,7 +6021,7 @@
 
 bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
                                        const OperandVector &Operands,
-                                       unsigned ListNo, bool IsPop) {
+                                       unsigned ListNo) {
   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
 
@@ -6029,7 +6029,7 @@
   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
 
-  if (!IsPop && ListContainsSP)
+  if (ListContainsSP)
     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
                  "SP may not be in the register list");
   else if (ListContainsPC && ListContainsLR)
@@ -6332,7 +6332,7 @@
         !isThumbTwo())
       return Error(Operands[2]->getStartLoc(),
                    "registers must be in range r0-r7 or pc");
-    if (validatetLDMRegList(Inst, Operands, 2, /*IsPop=*/true))
+    if (validatetLDMRegList(Inst, Operands, 2))
       return true;
     break;
   }
Index: ../llvm/test/MC/ARM/thumb-load-store-multiple.s
===================================================================
--- ../llvm/test/MC/ARM/thumb-load-store-multiple.s
+++ ../llvm/test/MC/ARM/thumb-load-store-multiple.s
@@ -6,7 +6,7 @@
 
 	.global ldm
 	.type ldm,%function
-ldb:
+ldm:
 	ldm r0!, {r1, sp}
 @ CHECK: error: SP may not be in the register list
 @ CHECK: ldm r0!, {r1, sp}
@@ -27,7 +27,7 @@
 ldmdb:
 	ldmdb r0!, {r1, sp}
 @ CHECK: error: SP may not be in the register list
-	ldm r0!, {lr, pc}
+	ldmdb r0!, {lr, pc}
 @ error: PC and LR may not be in the register list simultaneously
 	itt eq
 	ldmeq r0!, {r1, pc}
@@ -63,12 +63,14 @@
 @ CHECK: error: SP may not be in the register list
 	push {pc}
 @ CHECK: error: PC may not be in the register list
-	push {sp,pc}
+	push {sp, pc}
 @ CHECK: error: SP and PC may not be in the register list
 
 	.global pop
 	.type pop,%function
 pop:
+        pop {sp}
+@ CHECK: error: SP may not be in the register list
 	pop {lr, pc}
 @ CHECK: error: PC and LR may not be in the register list simultaneously
 @ CHECK: pop {lr, pc}
@@ -83,10 +85,6 @@
 	.global valid
 	.type valid,%function
 valid:
-	pop {sp}
-@ CHECK: ldr sp, [sp], #4
-	pop {sp, pc}
-@ CHECK: pop.w {sp, pc}
 	push.w {r0}
 @ CHECK: str r0, [sp, #-4]
 	pop.w {r0}