diff --git a/llvm/lib/CodeGen/MachineSSAUpdater.cpp b/llvm/lib/CodeGen/MachineSSAUpdater.cpp
--- a/llvm/lib/CodeGen/MachineSSAUpdater.cpp
+++ b/llvm/lib/CodeGen/MachineSSAUpdater.cpp
@@ -292,7 +292,7 @@
                               MachineSSAUpdater *Updater) {
     // Insert an implicit_def to represent an undef value.
     MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
-                                        BB, BB->getFirstTerminator(),
+                                        BB, BB->getFirstNonPHI(),
                                         Updater->VRC, Updater->MRI,
                                         Updater->TII);
     return NewDef->getOperand(0).getReg();
diff --git a/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir b/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=si-i1-copies -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
+
+# Test that the new IMPLICIT_DEF is inserted in the correct location.
+---
+name:            test_undef
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: test_undef
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.1(0x80000000)
+  ; GCN:   S_BRANCH %bb.1
+  ; GCN: bb.1:
+  ; GCN:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; GCN:   [[COPY:%[0-9]+]]:sreg_64_xexec = COPY [[DEF]]
+  ; GCN:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[COPY]], implicit $exec
+  bb.0:
+    successors: %bb.1
+
+    %0:vreg_1 = IMPLICIT_DEF
+    S_BRANCH %bb.1
+
+  bb.1:
+    %1:vreg_1 = PHI %0, %bb.0
+    %2:sreg_64_xexec = COPY %1
+    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2, implicit $exec
+
+...