[Mips][Disassembler][R6] Disassembler crashes on compact jump instructions for r6

[vmedic]

Summary

When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.

[dsanders]

Please include the full context as per the instructions at http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

415–416 ↗

(On Diff #17743)

Nit: indentation

1771–1773 ↗

(On Diff #17743)

Nit: indentation

lib/Target/Mips/Mips32r6InstrInfo.td

381–382

I'm not sure this one needs a DecoderMethod since there's nothing particularly special about the operands and the new DecodeCompactJump() isn't doing anything tricky. In particular, there aren't any ins/outs that have multiple corresponding MCOperands. It seems like the problem is just innappropriate use of DecodeSimm16.

Could you try deleting this line and see if that fixes the problem too?

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

168

Nit: delete extra blank line

[vmedic]

Removed dedicated decoder method as suggested.

[vmedic]

Commented line removed.

[dsanders]

LGTM

[dsanders]

Oops, I noticed something after clicking submit. LGTM with a whitespace nit. You gained some additional blank-lines at the end of some of the tests.

[vmedic]

Trailing spaces removed. Committed revision 227084.

lib/Target/Mips/Mips32r6InstrInfo.td

   list<dag> Pattern = [];
   bit isTerminator = 1;
   bit hasDelaySlot = 0;
-  string DecoderMethod = "DecodeSimm16";
 }
 
 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

 0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
 0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
 0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
+0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
+0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
 0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
+0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
+0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
+

test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt

 0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
-0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
-0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

 0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
 0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18)
 0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
+0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
+0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
+

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
 0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
+0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
+0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
+

test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt

 0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
-0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
-0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943