Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp
===================================================================
--- lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -252,6 +252,11 @@
                               uint64_t Address,
                               const void *Decoder);
 
+static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
+  unsigned Insn,
+  uint64_t Address,
+  const void *Decoder);
+
 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
                                     unsigned Insn,
                                     uint64_t Address,
@@ -1111,6 +1116,23 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
+  unsigned Insn,
+  uint64_t Address,
+  const void *Decoder) {
+  int Offset = SignExtend32<9>((Insn & 0xff80) >> 7);
+  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  Inst.addOperand(MCOperand::CreateReg(Base));
+  Inst.addOperand(MCOperand::CreateImm(Offset));
+  Inst.addOperand(MCOperand::CreateImm(Hint));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeSyncI(MCInst &Inst,
                               unsigned Insn,
                               uint64_t Address,
Index: lib/Target/Mips/Mips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrInfo.td
+++ lib/Target/Mips/Mips32r6InstrInfo.td
@@ -550,6 +550,7 @@
   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
   list<dag> Pattern = [];
+  string DecoderMethod = "DecodeCacheOpR6";
 }
 
 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
Index: test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -139,3 +139,6 @@
 0x33 0xfe 0x1d 0x02    # CHECK: tltu $16, $sp, 1016
 0x36 0x00 0xd1 0x00    # CHECK: tne $6, $17
 0x76 0xdd 0xe8 0x00    # CHECK: tne $7, $8, 885
+0x25 0x04 0xa1 0x7c    # CHECK: cache 1, 8($5)
+0x35 0x04 0xa1 0x7c    # CHECK: pref 1, 8($5
+
Index: test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -139,3 +139,6 @@
 0x02 0x1d 0xfe 0x33    # CHECK: tltu $16, $sp, 1016
 0x00 0xd1 0x00 0x36    # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76    # CHECK: tne $7, $8, 885
+0x7c 0xa1 0x04 0x25    # CHECK: cache 1, 8($5)
+0x7c 0xa1 0x04 0x35    # CHECK: pref 1, 8($5)
+
Index: test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
+++ test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
@@ -15,10 +15,8 @@
 0x60 0xc0 0x00 0x40    # CHECK: bnec $6, $zero, 256
 0x60 0xa0 0x00 0x40    # CHECK: bnec $5, $zero, 256
 0x60 0xa6 0x00 0x40    # CHECK: bnec $5, $6, 256
-0x7c 0xa1 0x04 0x25    # CHECK: cache 1, 8($5)
 0xf8 0x05 0x01 0x00    # CHECK: jialc $5, 256
 0xd8 0x05 0x01 0x00    # CHECK: jic $5, 256
-0x7c 0xa1 0x04 0x35    # CHECK: pref 1, 8($5)
 0x49 0xc8 0x0d 0x43    # CHECK: ldc2 $8, -701($1)
 0x49 0x52 0x34 0xb7    # CHECK: lwc2 $18, -841($6)
 0x49 0xf4 0x92 0x75    # CHECK: sdc2 $20, 629($18)
Index: test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -157,3 +157,6 @@
 0x33 0xfe 0x1d 0x02    # CHECK: tltu $16, $sp, 1016
 0x36 0x00 0xd1 0x00    # CHECK: tne $6, $17
 0x76 0xdd 0xe8 0x00    # CHECK: tne $7, $8, 885
+0x25 0x04 0xa1 0x7c    # CHECK: cache 1, 8($5)
+0x35 0x04 0xa1 0x7c    # CHECK: pref 1, 8($5
+
Index: test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -157,3 +157,6 @@
 0x02 0x1d 0xfe 0x33    # CHECK: tltu $16, $sp, 1016
 0x00 0xd1 0x00 0x36    # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76    # CHECK: tne $7, $8, 885
+0x7c 0xa1 0x04 0x25    # CHECK: cache 1, 8($5)
+0x7c 0xa1 0x04 0x35    # CHECK: pref 1, 8($5)
+
Index: test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
===================================================================
--- test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
+++ test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt
@@ -15,10 +15,8 @@
 0x60 0xc0 0x00 0x40    # CHECK: bnec $6, $zero, 256
 0x60 0xa0 0x00 0x40    # CHECK: bnec $5, $zero, 256
 0x60 0xa6 0x00 0x40    # CHECK: bnec $5, $6, 256
-0x7c 0xa1 0x04 0x25    # CHECK: cache 1, 8($5)
 0xf8 0x05 0x01 0x00    # CHECK: jialc $5, 256
 0xd8 0x05 0x01 0x00    # CHECK: jic $5, 256
-0x7c 0xa1 0x04 0x35    # CHECK: pref 1, 8($5)
 0x49 0xc8 0x0d 0x43    # CHECK: ldc2 $8, -701($1)
 0x49 0x52 0x34 0xb7    # CHECK: lwc2 $18, -841($6)
 0x49 0xf4 0x92 0x75    # CHECK: sdc2 $20, 629($18)