diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -3863,10 +3863,10 @@
   invalid.
 - ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
   ``d0-d31``, or ``q0-q15``.
+- ``t``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
+  ``d0-d15``, or ``q0-q7``.
 - ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
   ``d0-d7``, or ``q0-q3``.
-- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
-  ``q0-q8``.
 
 ARM's Thumb1 mode:
 
@@ -3883,10 +3883,10 @@
 - ``h``: A high GPR register (``r0-r7``).
 - ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
   ``d0-d31``, or ``q0-q15``.
+- ``t``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``,
+  ``d0-d15``, or ``q0-q7``.
 - ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``,
   ``d0-d7``, or ``q0-q3``.
-- ``t``: A low floating-point/SIMD register: ``s0-s31``, ``d0-d16``, or
-  ``q0-q8``.
 
 
 Hexagon: