Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -189,7 +189,8 @@
 
 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
                                      "true",
-                                     "Enable instructions added in ISA 3.0.">;
+                                     "Enable instructions added in ISA 3.0.",
+                                     [FeatureFPU]>;
 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
                                         "Enable POWER9 Altivec instructions",
                                         [FeatureISA3_0, FeatureP8Altivec]>;
Index: llvm/test/CodeGen/PowerPC/feature-isav30.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/feature-isav30.ll
@@ -0,0 +1,18 @@
+; RUN: not llc -mattr=+isa-v30-instructions,+spe -verify-machineinstrs \
+; RUN:   -mtriple=powerpc-unknown-unknown %s -o - 2>&1 | FileCheck %s
+
+; This IR aims to test how having ISA 3.0 implies that FPU is also enabled, as
+; a compliant implementation of ISA 3.0 should have the floating point unit.
+;
+; Thus, also setting SPE along side of having ISA 3.0 would not be correct as
+; both SPE and traditional floating point cannot be enabled.
+;
+; The triple is set to powerpc-unknown-unknown, as SPE is only supported on
+; 32-bit targets.
+
+define signext i32 @test_fpu_v30_feature () {
+; CHECK: LLVM ERROR: SPE and traditional floating point cannot both be enabled.
+entry:
+  ret i32 0
+}
+