Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6953,9 +6953,11 @@ [&FirstOp](SDUse &U) { return U.get().isUndef() || U.get() == FirstOp; })) { - SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i32, FirstOp, - DAG.getValueType(MVT::i1)); - return DAG.getNode(ARMISD::PREDICATE_CAST, dl, Op.getValueType(), Ext); + SDValue SHL = DAG.getNode(ISD::SHL, dl, MVT::i32, FirstOp, + DAG.getConstant(31, dl, MVT::i32)); + SDValue SHR = DAG.getNode(ISD::SRA, dl, MVT::i32, SHL, + DAG.getConstant(31, dl, MVT::i32)); + return DAG.getNode(ARMISD::PREDICATE_CAST, dl, Op.getValueType(), SHR); } // First create base with bits set where known @@ -7889,9 +7891,11 @@ unsigned LaneWidth = getVectorTyFromPredicateVector(VecVT).getScalarSizeInBits() / 8; unsigned Mask = ((1 << LaneWidth) - 1) << Lane * LaneWidth; - SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i32, - Op.getOperand(1), DAG.getValueType(MVT::i1)); - SDValue BFI = DAG.getNode(ARMISD::BFI, dl, MVT::i32, Conv, Ext, + SDValue SHL = DAG.getNode(ISD::SHL, dl, MVT::i32, Op.getOperand(1), + DAG.getConstant(31, dl, MVT::i32)); + SDValue SHR = DAG.getNode(ISD::SRA, dl, MVT::i32, SHL, + DAG.getConstant(31, dl, MVT::i32)); + SDValue BFI = DAG.getNode(ARMISD::BFI, dl, MVT::i32, Conv, SHR, DAG.getConstant(~Mask, dl, MVT::i32)); return DAG.getNode(ARMISD::PREDICATE_CAST, dl, Op.getValueType(), BFI); } Index: llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll +++ llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll @@ -26,21 +26,17 @@ ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: vcmp.s32 gt, q0, zr ; CHECK-NEXT: @ implicit-def: $q0 ; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r1, lr, #1 -; CHECK-NEXT: ubfx r3, lr, #4, #1 -; CHECK-NEXT: rsb.w r12, r1, #0 -; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r12, lr, #0, #1 +; CHECK-NEXT: sbfx r3, lr, #4, #1 ; CHECK-NEXT: bfi r1, r12, #0, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1 -; CHECK-NEXT: ubfx r3, lr, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #8, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1 -; CHECK-NEXT: ubfx r3, lr, #12, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #12, #1 ; CHECK-NEXT: bfi r1, r3, #3, #1 ; CHECK-NEXT: lsls r3, r1, #31 ; CHECK-NEXT: itt ne @@ -81,21 +77,17 @@ ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: vcmp.s32 gt, q0, zr ; CHECK-NEXT: @ implicit-def: $q0 ; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r1, lr, #1 -; CHECK-NEXT: ubfx r3, lr, #4, #1 -; CHECK-NEXT: rsb.w r12, r1, #0 -; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r12, lr, #0, #1 +; CHECK-NEXT: sbfx r3, lr, #4, #1 ; CHECK-NEXT: bfi r1, r12, #0, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1 -; CHECK-NEXT: ubfx r3, lr, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #8, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1 -; CHECK-NEXT: ubfx r3, lr, #12, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #12, #1 ; CHECK-NEXT: bfi r1, r3, #3, #1 ; CHECK-NEXT: lsls r3, r1, #31 ; CHECK-NEXT: itt ne @@ -135,22 +127,18 @@ ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: vmov.i32 q1, #0xff ; CHECK-NEXT: vcmp.s32 gt, q0, zr ; CHECK-NEXT: @ implicit-def: $q0 ; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r1, lr, #1 -; CHECK-NEXT: ubfx r3, lr, #4, #1 -; CHECK-NEXT: rsb.w r12, r1, #0 -; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r12, lr, #0, #1 +; CHECK-NEXT: sbfx r3, lr, #4, #1 ; CHECK-NEXT: bfi r1, r12, #0, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1 -; CHECK-NEXT: ubfx r3, lr, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #8, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1 -; CHECK-NEXT: ubfx r3, lr, #12, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #12, #1 ; CHECK-NEXT: bfi r1, r3, #3, #1 ; CHECK-NEXT: lsls r3, r1, #31 ; CHECK-NEXT: itt ne @@ -190,21 +178,17 @@ ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: vcmp.s32 gt, q0, zr ; CHECK-NEXT: @ implicit-def: $q0 ; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r1, lr, #1 -; CHECK-NEXT: ubfx r3, lr, #4, #1 -; CHECK-NEXT: rsb.w r12, r1, #0 -; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r12, lr, #0, #1 +; CHECK-NEXT: sbfx r3, lr, #4, #1 ; CHECK-NEXT: bfi r1, r12, #0, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1 -; CHECK-NEXT: ubfx r3, lr, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #8, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1 -; CHECK-NEXT: ubfx r3, lr, #12, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, lr, #12, #1 ; CHECK-NEXT: bfi r1, r3, #3, #1 ; CHECK-NEXT: lsls r3, r1, #31 ; CHECK-NEXT: itt ne @@ -260,33 +244,25 @@ ; CHECK-NEXT: .pad #8 ; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: vldrh.u16 q0, [r1] +; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vcmp.s16 gt, q0, zr ; CHECK-NEXT: @ implicit-def: $q0 ; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r3, lr, #1 -; CHECK-NEXT: ubfx r1, lr, #2, #1 -; CHECK-NEXT: rsb.w r12, r3, #0 -; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r12, lr, #0, #1 +; CHECK-NEXT: sbfx r1, lr, #2, #1 ; CHECK-NEXT: bfi r3, r12, #0, #1 ; CHECK-NEXT: bfi r3, r1, #1, #1 -; CHECK-NEXT: ubfx r1, lr, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #4, #1 ; CHECK-NEXT: bfi r3, r1, #2, #1 -; CHECK-NEXT: ubfx r1, lr, #6, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #6, #1 ; CHECK-NEXT: bfi r3, r1, #3, #1 -; CHECK-NEXT: ubfx r1, lr, #8, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #8, #1 ; CHECK-NEXT: bfi r3, r1, #4, #1 -; CHECK-NEXT: ubfx r1, lr, #10, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #10, #1 ; CHECK-NEXT: bfi r3, r1, #5, #1 -; CHECK-NEXT: ubfx r1, lr, #12, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #12, #1 ; CHECK-NEXT: bfi r3, r1, #6, #1 -; CHECK-NEXT: ubfx r1, lr, #14, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #14, #1 ; CHECK-NEXT: bfi r3, r1, #7, #1 ; CHECK-NEXT: uxtb r1, r3 ; CHECK-NEXT: lsls r3, r3, #31 @@ -343,33 +319,25 @@ ; CHECK-NEXT: .pad #8 ; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: vldrh.u16 q0, [r1] +; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vcmp.s16 gt, q0, zr ; CHECK-NEXT: @ implicit-def: $q0 ; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r3, lr, #1 -; CHECK-NEXT: ubfx r1, lr, #2, #1 -; CHECK-NEXT: rsb.w r12, r3, #0 -; CHECK-NEXT: movs r3, #0 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r12, lr, #0, #1 +; CHECK-NEXT: sbfx r1, lr, #2, #1 ; CHECK-NEXT: bfi r3, r12, #0, #1 ; CHECK-NEXT: bfi r3, r1, #1, #1 -; CHECK-NEXT: ubfx r1, lr, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #4, #1 ; CHECK-NEXT: bfi r3, r1, #2, #1 -; CHECK-NEXT: ubfx r1, lr, #6, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #6, #1 ; CHECK-NEXT: bfi r3, r1, #3, #1 -; CHECK-NEXT: ubfx r1, lr, #8, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #8, #1 ; CHECK-NEXT: bfi r3, r1, #4, #1 -; CHECK-NEXT: ubfx r1, lr, #10, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #10, #1 ; CHECK-NEXT: bfi r3, r1, #5, #1 -; CHECK-NEXT: ubfx r1, lr, #12, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #12, #1 ; CHECK-NEXT: bfi r3, r1, #6, #1 -; CHECK-NEXT: ubfx r1, lr, #14, #1 -; CHECK-NEXT: rsbs r1, r1, #0 +; CHECK-NEXT: sbfx r1, lr, #14, #1 ; CHECK-NEXT: bfi r3, r1, #7, #1 ; CHECK-NEXT: uxtb r1, r3 ; CHECK-NEXT: lsls r3, r3, #31 @@ -440,36 +408,28 @@ ; CHECK-NEXT: .pad #8 ; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: vldrh.u16 q0, [r1] +; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vpt.s16 gt, q0, zr ; CHECK-NEXT: vldrht.u16 q0, [r2] ; CHECK-NEXT: vmrs r1, p0 -; CHECK-NEXT: and r2, r1, #1 -; CHECK-NEXT: rsbs r3, r2, #0 -; CHECK-NEXT: movs r2, #0 -; CHECK-NEXT: bfi r2, r3, #0, #1 -; CHECK-NEXT: ubfx r3, r1, #2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: bfi r2, r3, #1, #1 -; CHECK-NEXT: ubfx r3, r1, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: bfi r2, r3, #2, #1 -; CHECK-NEXT: ubfx r3, r1, #6, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: bfi r2, r3, #3, #1 -; CHECK-NEXT: ubfx r3, r1, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: bfi r2, r3, #4, #1 -; CHECK-NEXT: ubfx r3, r1, #10, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: bfi r2, r3, #5, #1 -; CHECK-NEXT: ubfx r3, r1, #12, #1 -; CHECK-NEXT: ubfx r1, r1, #14, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: bfi r2, r3, #6, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: bfi r2, r1, #7, #1 -; CHECK-NEXT: uxtb r1, r2 -; CHECK-NEXT: lsls r2, r2, #31 +; CHECK-NEXT: sbfx r2, r1, #0, #1 +; CHECK-NEXT: bfi r3, r2, #0, #1 +; CHECK-NEXT: sbfx r2, r1, #2, #1 +; CHECK-NEXT: bfi r3, r2, #1, #1 +; CHECK-NEXT: sbfx r2, r1, #4, #1 +; CHECK-NEXT: bfi r3, r2, #2, #1 +; CHECK-NEXT: sbfx r2, r1, #6, #1 +; CHECK-NEXT: bfi r3, r2, #3, #1 +; CHECK-NEXT: sbfx r2, r1, #8, #1 +; CHECK-NEXT: bfi r3, r2, #4, #1 +; CHECK-NEXT: sbfx r2, r1, #10, #1 +; CHECK-NEXT: bfi r3, r2, #5, #1 +; CHECK-NEXT: sbfx r2, r1, #12, #1 +; CHECK-NEXT: bfi r3, r2, #6, #1 +; CHECK-NEXT: sbfx r1, r1, #14, #1 +; CHECK-NEXT: bfi r3, r1, #7, #1 +; CHECK-NEXT: lsls r2, r3, #31 +; CHECK-NEXT: uxtb r1, r3 ; CHECK-NEXT: itt ne ; CHECK-NEXT: vmovne.u16 r2, q0[0] ; CHECK-NEXT: strbne r2, [r0] @@ -518,21 +478,17 @@ ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: vpt.s32 gt, q0, zr ; CHECK-NEXT: vldrwt.u32 q0, [r2] ; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: and r1, r2, #1 -; CHECK-NEXT: rsbs r3, r1, #0 -; CHECK-NEXT: movs r1, #0 +; CHECK-NEXT: sbfx r3, r2, #0, #1 ; CHECK-NEXT: bfi r1, r3, #0, #1 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, r2, #4, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, r2, #8, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1 -; CHECK-NEXT: rsbs r2, r2, #0 +; CHECK-NEXT: sbfx r2, r2, #12, #1 ; CHECK-NEXT: bfi r1, r2, #3, #1 ; CHECK-NEXT: lsls r2, r1, #31 ; CHECK-NEXT: itt ne @@ -567,21 +523,17 @@ ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: vpt.s32 gt, q0, zr ; CHECK-NEXT: vldrwt.u32 q0, [r2] ; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: and r1, r2, #1 -; CHECK-NEXT: rsbs r3, r1, #0 -; CHECK-NEXT: movs r1, #0 +; CHECK-NEXT: sbfx r3, r2, #0, #1 ; CHECK-NEXT: bfi r1, r3, #0, #1 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, r2, #4, #1 ; CHECK-NEXT: bfi r1, r3, #1, #1 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: sbfx r3, r2, #8, #1 ; CHECK-NEXT: bfi r1, r3, #2, #1 -; CHECK-NEXT: rsbs r2, r2, #0 +; CHECK-NEXT: sbfx r2, r2, #12, #1 ; CHECK-NEXT: bfi r1, r2, #3, #1 ; CHECK-NEXT: lsls r2, r1, #31 ; CHECK-NEXT: itt ne Index: llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll @@ -218,19 +218,15 @@ ; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr -; CHECK-LE-NEXT: vmrs r1, p0 -; CHECK-LE-NEXT: and r0, r1, #1 -; CHECK-LE-NEXT: rsbs r2, r0, #0 ; CHECK-LE-NEXT: movs r0, #0 +; CHECK-LE-NEXT: vmrs r1, p0 +; CHECK-LE-NEXT: sbfx r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r0, r2, #0, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #4, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 +; CHECK-LE-NEXT: sbfx r2, r1, #4, #1 ; CHECK-LE-NEXT: bfi r0, r2, #1, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #8, #1 -; CHECK-LE-NEXT: ubfx r1, r1, #12, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 +; CHECK-LE-NEXT: sbfx r2, r1, #8, #1 ; CHECK-LE-NEXT: bfi r0, r2, #2, #1 -; CHECK-LE-NEXT: rsbs r1, r1, #0 +; CHECK-LE-NEXT: sbfx r1, r1, #12, #1 ; CHECK-LE-NEXT: bfi r0, r1, #3, #1 ; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: bx lr @@ -240,20 +236,16 @@ ; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: vrev64.32 q1, q0 +; CHECK-BE-NEXT: movs r0, #0 ; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr ; CHECK-BE-NEXT: vmrs r1, p0 -; CHECK-BE-NEXT: and r0, r1, #1 -; CHECK-BE-NEXT: rsbs r2, r0, #0 -; CHECK-BE-NEXT: movs r0, #0 +; CHECK-BE-NEXT: sbfx r2, r1, #0, #1 ; CHECK-BE-NEXT: bfi r0, r2, #0, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #4, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 +; CHECK-BE-NEXT: sbfx r2, r1, #4, #1 ; CHECK-BE-NEXT: bfi r0, r2, #1, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #8, #1 -; CHECK-BE-NEXT: ubfx r1, r1, #12, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 +; CHECK-BE-NEXT: sbfx r2, r1, #8, #1 ; CHECK-BE-NEXT: bfi r0, r2, #2, #1 -; CHECK-BE-NEXT: rsbs r1, r1, #0 +; CHECK-BE-NEXT: sbfx r1, r1, #12, #1 ; CHECK-BE-NEXT: bfi r0, r1, #3, #1 ; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: bx lr @@ -269,33 +261,25 @@ ; CHECK-LE-NEXT: .pad #8 ; CHECK-LE-NEXT: sub sp, #8 ; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr -; CHECK-LE-NEXT: vmrs r1, p0 -; CHECK-LE-NEXT: and r0, r1, #1 -; CHECK-LE-NEXT: rsbs r2, r0, #0 -; CHECK-LE-NEXT: movs r0, #0 -; CHECK-LE-NEXT: bfi r0, r2, #0, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #2, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r0, r2, #1, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #4, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r0, r2, #2, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #6, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r0, r2, #3, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #8, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r0, r2, #4, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #10, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r0, r2, #5, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #12, #1 -; CHECK-LE-NEXT: ubfx r1, r1, #14, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r0, r2, #6, #1 -; CHECK-LE-NEXT: rsbs r1, r1, #0 -; CHECK-LE-NEXT: bfi r0, r1, #7, #1 -; CHECK-LE-NEXT: uxtb r0, r0 +; CHECK-LE-NEXT: movs r2, #0 +; CHECK-LE-NEXT: vmrs r0, p0 +; CHECK-LE-NEXT: sbfx r1, r0, #0, #1 +; CHECK-LE-NEXT: bfi r2, r1, #0, #1 +; CHECK-LE-NEXT: sbfx r1, r0, #2, #1 +; CHECK-LE-NEXT: bfi r2, r1, #1, #1 +; CHECK-LE-NEXT: sbfx r1, r0, #4, #1 +; CHECK-LE-NEXT: bfi r2, r1, #2, #1 +; CHECK-LE-NEXT: sbfx r1, r0, #6, #1 +; CHECK-LE-NEXT: bfi r2, r1, #3, #1 +; CHECK-LE-NEXT: sbfx r1, r0, #8, #1 +; CHECK-LE-NEXT: bfi r2, r1, #4, #1 +; CHECK-LE-NEXT: sbfx r1, r0, #10, #1 +; CHECK-LE-NEXT: bfi r2, r1, #5, #1 +; CHECK-LE-NEXT: sbfx r1, r0, #12, #1 +; CHECK-LE-NEXT: bfi r2, r1, #6, #1 +; CHECK-LE-NEXT: sbfx r0, r0, #14, #1 +; CHECK-LE-NEXT: bfi r2, r0, #7, #1 +; CHECK-LE-NEXT: uxtb r0, r2 ; CHECK-LE-NEXT: add sp, #8 ; CHECK-LE-NEXT: bx lr ; @@ -304,34 +288,26 @@ ; CHECK-BE-NEXT: .pad #8 ; CHECK-BE-NEXT: sub sp, #8 ; CHECK-BE-NEXT: vrev64.16 q1, q0 +; CHECK-BE-NEXT: movs r2, #0 ; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr -; CHECK-BE-NEXT: vmrs r1, p0 -; CHECK-BE-NEXT: and r0, r1, #1 -; CHECK-BE-NEXT: rsbs r2, r0, #0 -; CHECK-BE-NEXT: movs r0, #0 -; CHECK-BE-NEXT: bfi r0, r2, #0, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #2, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r0, r2, #1, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #4, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r0, r2, #2, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #6, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r0, r2, #3, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #8, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r0, r2, #4, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #10, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r0, r2, #5, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #12, #1 -; CHECK-BE-NEXT: ubfx r1, r1, #14, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r0, r2, #6, #1 -; CHECK-BE-NEXT: rsbs r1, r1, #0 -; CHECK-BE-NEXT: bfi r0, r1, #7, #1 -; CHECK-BE-NEXT: uxtb r0, r0 +; CHECK-BE-NEXT: vmrs r0, p0 +; CHECK-BE-NEXT: sbfx r1, r0, #0, #1 +; CHECK-BE-NEXT: bfi r2, r1, #0, #1 +; CHECK-BE-NEXT: sbfx r1, r0, #2, #1 +; CHECK-BE-NEXT: bfi r2, r1, #1, #1 +; CHECK-BE-NEXT: sbfx r1, r0, #4, #1 +; CHECK-BE-NEXT: bfi r2, r1, #2, #1 +; CHECK-BE-NEXT: sbfx r1, r0, #6, #1 +; CHECK-BE-NEXT: bfi r2, r1, #3, #1 +; CHECK-BE-NEXT: sbfx r1, r0, #8, #1 +; CHECK-BE-NEXT: bfi r2, r1, #4, #1 +; CHECK-BE-NEXT: sbfx r1, r0, #10, #1 +; CHECK-BE-NEXT: bfi r2, r1, #5, #1 +; CHECK-BE-NEXT: sbfx r1, r0, #12, #1 +; CHECK-BE-NEXT: bfi r2, r1, #6, #1 +; CHECK-BE-NEXT: sbfx r0, r0, #14, #1 +; CHECK-BE-NEXT: bfi r2, r0, #7, #1 +; CHECK-BE-NEXT: uxtb r0, r2 ; CHECK-BE-NEXT: add sp, #8 ; CHECK-BE-NEXT: bx lr entry: Index: llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll @@ -8,8 +8,7 @@ ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #0, #4 ; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 @@ -27,8 +26,7 @@ ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #12, #4 ; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 @@ -45,8 +43,7 @@ ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr @@ -65,8 +62,7 @@ ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #0, #2 ; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 @@ -84,8 +80,7 @@ ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #6, #2 ; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 @@ -102,8 +97,7 @@ ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr @@ -122,8 +116,7 @@ ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #0, #1 ; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 @@ -141,8 +134,7 @@ ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #3, #1 ; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 @@ -159,8 +151,7 @@ ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cset r0, lo -; CHECK-NEXT: and r0, r0, #1 -; CHECK-NEXT: rsbs r0, r0, #0 +; CHECK-NEXT: sbfx r0, r0, #0, #1 ; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr Index: llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll @@ -178,17 +178,13 @@ ; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr ; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: vmrs r1, p0 -; CHECK-LE-NEXT: and r2, r1, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 +; CHECK-LE-NEXT: sbfx r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r3, r2, #0, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #4, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 +; CHECK-LE-NEXT: sbfx r2, r1, #4, #1 ; CHECK-LE-NEXT: bfi r3, r2, #1, #1 -; CHECK-LE-NEXT: ubfx r2, r1, #8, #1 -; CHECK-LE-NEXT: ubfx r1, r1, #12, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 +; CHECK-LE-NEXT: sbfx r2, r1, #8, #1 ; CHECK-LE-NEXT: bfi r3, r2, #2, #1 -; CHECK-LE-NEXT: rsbs r1, r1, #0 +; CHECK-LE-NEXT: sbfx r1, r1, #12, #1 ; CHECK-LE-NEXT: bfi r3, r1, #3, #1 ; CHECK-LE-NEXT: strb r3, [r0] ; CHECK-LE-NEXT: bx lr @@ -199,17 +195,13 @@ ; CHECK-BE-NEXT: movs r3, #0 ; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr ; CHECK-BE-NEXT: vmrs r1, p0 -; CHECK-BE-NEXT: and r2, r1, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 +; CHECK-BE-NEXT: sbfx r2, r1, #0, #1 ; CHECK-BE-NEXT: bfi r3, r2, #0, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #4, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 +; CHECK-BE-NEXT: sbfx r2, r1, #4, #1 ; CHECK-BE-NEXT: bfi r3, r2, #1, #1 -; CHECK-BE-NEXT: ubfx r2, r1, #8, #1 -; CHECK-BE-NEXT: ubfx r1, r1, #12, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 +; CHECK-BE-NEXT: sbfx r2, r1, #8, #1 ; CHECK-BE-NEXT: bfi r3, r2, #2, #1 -; CHECK-BE-NEXT: rsbs r1, r1, #0 +; CHECK-BE-NEXT: sbfx r1, r1, #12, #1 ; CHECK-BE-NEXT: bfi r3, r1, #3, #1 ; CHECK-BE-NEXT: strb r3, [r0] ; CHECK-BE-NEXT: bx lr @@ -223,66 +215,50 @@ ; CHECK-LE-LABEL: store_v8i1: ; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr -; CHECK-LE-NEXT: vmrs r2, p0 -; CHECK-LE-NEXT: and r1, r2, #1 -; CHECK-LE-NEXT: rsbs r3, r1, #0 -; CHECK-LE-NEXT: movs r1, #0 -; CHECK-LE-NEXT: bfi r1, r3, #0, #1 -; CHECK-LE-NEXT: ubfx r3, r2, #2, #1 -; CHECK-LE-NEXT: rsbs r3, r3, #0 -; CHECK-LE-NEXT: bfi r1, r3, #1, #1 -; CHECK-LE-NEXT: ubfx r3, r2, #4, #1 -; CHECK-LE-NEXT: rsbs r3, r3, #0 -; CHECK-LE-NEXT: bfi r1, r3, #2, #1 -; CHECK-LE-NEXT: ubfx r3, r2, #6, #1 -; CHECK-LE-NEXT: rsbs r3, r3, #0 -; CHECK-LE-NEXT: bfi r1, r3, #3, #1 -; CHECK-LE-NEXT: ubfx r3, r2, #8, #1 -; CHECK-LE-NEXT: rsbs r3, r3, #0 -; CHECK-LE-NEXT: bfi r1, r3, #4, #1 -; CHECK-LE-NEXT: ubfx r3, r2, #10, #1 -; CHECK-LE-NEXT: rsbs r3, r3, #0 -; CHECK-LE-NEXT: bfi r1, r3, #5, #1 -; CHECK-LE-NEXT: ubfx r3, r2, #12, #1 -; CHECK-LE-NEXT: ubfx r2, r2, #14, #1 -; CHECK-LE-NEXT: rsbs r3, r3, #0 -; CHECK-LE-NEXT: bfi r1, r3, #6, #1 -; CHECK-LE-NEXT: rsbs r2, r2, #0 -; CHECK-LE-NEXT: bfi r1, r2, #7, #1 -; CHECK-LE-NEXT: strb r1, [r0] +; CHECK-LE-NEXT: movs r3, #0 +; CHECK-LE-NEXT: vmrs r1, p0 +; CHECK-LE-NEXT: sbfx r2, r1, #0, #1 +; CHECK-LE-NEXT: bfi r3, r2, #0, #1 +; CHECK-LE-NEXT: sbfx r2, r1, #2, #1 +; CHECK-LE-NEXT: bfi r3, r2, #1, #1 +; CHECK-LE-NEXT: sbfx r2, r1, #4, #1 +; CHECK-LE-NEXT: bfi r3, r2, #2, #1 +; CHECK-LE-NEXT: sbfx r2, r1, #6, #1 +; CHECK-LE-NEXT: bfi r3, r2, #3, #1 +; CHECK-LE-NEXT: sbfx r2, r1, #8, #1 +; CHECK-LE-NEXT: bfi r3, r2, #4, #1 +; CHECK-LE-NEXT: sbfx r2, r1, #10, #1 +; CHECK-LE-NEXT: bfi r3, r2, #5, #1 +; CHECK-LE-NEXT: sbfx r2, r1, #12, #1 +; CHECK-LE-NEXT: bfi r3, r2, #6, #1 +; CHECK-LE-NEXT: sbfx r1, r1, #14, #1 +; CHECK-LE-NEXT: bfi r3, r1, #7, #1 +; CHECK-LE-NEXT: strb r3, [r0] ; CHECK-LE-NEXT: bx lr ; ; CHECK-BE-LABEL: store_v8i1: ; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE-NEXT: vrev64.16 q1, q0 +; CHECK-BE-NEXT: movs r3, #0 ; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr -; CHECK-BE-NEXT: vmrs r2, p0 -; CHECK-BE-NEXT: and r1, r2, #1 -; CHECK-BE-NEXT: rsbs r3, r1, #0 -; CHECK-BE-NEXT: movs r1, #0 -; CHECK-BE-NEXT: bfi r1, r3, #0, #1 -; CHECK-BE-NEXT: ubfx r3, r2, #2, #1 -; CHECK-BE-NEXT: rsbs r3, r3, #0 -; CHECK-BE-NEXT: bfi r1, r3, #1, #1 -; CHECK-BE-NEXT: ubfx r3, r2, #4, #1 -; CHECK-BE-NEXT: rsbs r3, r3, #0 -; CHECK-BE-NEXT: bfi r1, r3, #2, #1 -; CHECK-BE-NEXT: ubfx r3, r2, #6, #1 -; CHECK-BE-NEXT: rsbs r3, r3, #0 -; CHECK-BE-NEXT: bfi r1, r3, #3, #1 -; CHECK-BE-NEXT: ubfx r3, r2, #8, #1 -; CHECK-BE-NEXT: rsbs r3, r3, #0 -; CHECK-BE-NEXT: bfi r1, r3, #4, #1 -; CHECK-BE-NEXT: ubfx r3, r2, #10, #1 -; CHECK-BE-NEXT: rsbs r3, r3, #0 -; CHECK-BE-NEXT: bfi r1, r3, #5, #1 -; CHECK-BE-NEXT: ubfx r3, r2, #12, #1 -; CHECK-BE-NEXT: ubfx r2, r2, #14, #1 -; CHECK-BE-NEXT: rsbs r3, r3, #0 -; CHECK-BE-NEXT: bfi r1, r3, #6, #1 -; CHECK-BE-NEXT: rsbs r2, r2, #0 -; CHECK-BE-NEXT: bfi r1, r2, #7, #1 -; CHECK-BE-NEXT: strb r1, [r0] +; CHECK-BE-NEXT: vmrs r1, p0 +; CHECK-BE-NEXT: sbfx r2, r1, #0, #1 +; CHECK-BE-NEXT: bfi r3, r2, #0, #1 +; CHECK-BE-NEXT: sbfx r2, r1, #2, #1 +; CHECK-BE-NEXT: bfi r3, r2, #1, #1 +; CHECK-BE-NEXT: sbfx r2, r1, #4, #1 +; CHECK-BE-NEXT: bfi r3, r2, #2, #1 +; CHECK-BE-NEXT: sbfx r2, r1, #6, #1 +; CHECK-BE-NEXT: bfi r3, r2, #3, #1 +; CHECK-BE-NEXT: sbfx r2, r1, #8, #1 +; CHECK-BE-NEXT: bfi r3, r2, #4, #1 +; CHECK-BE-NEXT: sbfx r2, r1, #10, #1 +; CHECK-BE-NEXT: bfi r3, r2, #5, #1 +; CHECK-BE-NEXT: sbfx r2, r1, #12, #1 +; CHECK-BE-NEXT: bfi r3, r2, #6, #1 +; CHECK-BE-NEXT: sbfx r1, r1, #14, #1 +; CHECK-BE-NEXT: bfi r3, r1, #7, #1 +; CHECK-BE-NEXT: strb r3, [r0] ; CHECK-BE-NEXT: bx lr entry: %c = icmp eq <8 x i16> %a, zeroinitializer