Index: lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- lib/Target/ARM/ARMInstrMVE.td
+++ lib/Target/ARM/ARMInstrMVE.td
@@ -328,6 +328,7 @@
     Requires<[HasV8_1MMainline, HasMVEInt]> {
   let D = MVEDomain;
   let DecoderNamespace = "MVE";
+  let invalidForTailPredication = 1;
 }
 
 class MVE_ScalarShift<string iname, dag oops, dag iops, string asm, string cstr,
@@ -1054,6 +1055,7 @@
   let Inst{6} = 0b1;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let invalidForTailPredication = 1;
 }
 
 def MVE_VREV64_8  : MVE_VREV<"vrev64", "8", 0b00, 0b00, "@earlyclobber $Qd">;
@@ -2104,6 +2106,7 @@
   let Inst{11-6} = 0b111111;
   let Inst{4} = 0b0;
   let Inst{0} = 0b1;
+  let invalidForTailPredication = 1;
 }
 
 def MVE_VRSHRNi16bh : MVE_VxSHRN<
@@ -2155,6 +2158,7 @@
   let Inst{11-6} = 0b111111;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let invalidForTailPredication = 1;
 }
 
 def MVE_VQRSHRUNs16bh : MVE_VxQRSHRUN<
@@ -2205,6 +2209,7 @@
   let Inst{11-6} = 0b111101;
   let Inst{4} = 0b0;
   let Inst{0} = bit_0;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VxQRSHRN_types<string iname, bit bit_0, bit bit_12> {
@@ -3338,6 +3343,7 @@
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = round;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
@@ -3462,6 +3468,7 @@
   let Inst{8} = 0b0;
   let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
   let Inst{0} = 0b1;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VxMOVxN_halves<string iname, string suffix,
@@ -3907,6 +3914,7 @@
   let Inst{12} = bit_12;
   let Inst{8} = 0b0;
   let Inst{5} = bit_5;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
@@ -4110,6 +4118,7 @@
 
   let mayLoad = load;
   let mayStore = !eq(load,0);
+  let invalidForTailPredication = 1;
 }
 
 // A parameter class used to encapsulate all the ways the writeback
Index: unittests/Target/ARM/MachineInstrTest.cpp
===================================================================
--- unittests/Target/ARM/MachineInstrTest.cpp
+++ unittests/Target/ARM/MachineInstrTest.cpp
@@ -13,11 +13,9 @@
 // Test for instructions that aren't immediately obviously valid within a
 // tail-predicated loop. This should be marked up in their tablegen
 // descriptions. Currently the horizontal vector operations are tagged.
-// TODO Add instructions that perform:
-// - truncation,
-// - extensions,
-// - byte swapping,
-// - others?
+// TODO: Are there any other instructions that perform narrowing, extending or
+// byte swapping?
+// TODO: Prune this list once we can handle them safely.
 TEST(MachineInstrInvalidTailPredication, IsCorrect) {
   LLVMInitializeARMTargetInfo();
   LLVMInitializeARMTarget();
@@ -150,6 +148,178 @@
     case MVE_VMINAVs8:
     case MVE_VMINAVs16:
     case MVE_VMINAVs32:
+    case MVE_VMOVNi16bh:
+    case MVE_VMOVNi16th:
+    case MVE_VMOVNi32bh:
+    case MVE_VMOVNi32th:
+    case MVE_VQMOVNs16bh:
+    case MVE_VQMOVNs16th:
+    case MVE_VQMOVNs32bh:
+    case MVE_VQMOVNs32th:
+    case MVE_VQMOVNu16bh:
+    case MVE_VQMOVNu16th:
+    case MVE_VQMOVNu32bh:
+    case MVE_VQMOVNu32th:
+    case MVE_VQMOVUNs16bh:
+    case MVE_VQMOVUNs16th:
+    case MVE_VQMOVUNs32bh:
+    case MVE_VQMOVUNs32th:
+    case MVE_VMOV_q_rr:
+    case MVE_VMOV_from_lane_32:
+    case MVE_VMOV_from_lane_s16:
+    case MVE_VMOV_from_lane_s8:
+    case MVE_VMOV_from_lane_u16:
+    case MVE_VMOV_from_lane_u8:
+    case MVE_VMOV_rr_q:
+    case MVE_VMOV_to_lane_16:
+    case MVE_VMOV_to_lane_32:
+    case MVE_VMOV_to_lane_8:
+    case MVE_VQDMLADHXs16:
+    case MVE_VQDMLADHXs32:
+    case MVE_VQDMLADHXs8:
+    case MVE_VQDMLADHs16:
+    case MVE_VQDMLADHs32:
+    case MVE_VQDMLADHs8:
+    case MVE_VQDMLAH_qrs16:
+    case MVE_VQDMLAH_qrs32:
+    case MVE_VQDMLAH_qrs8:
+    case MVE_VQDMLASH_qrs16:
+    case MVE_VQDMLASH_qrs32:
+    case MVE_VQDMLASH_qrs8:
+    case MVE_VQDMLSDHXs16:
+    case MVE_VQDMLSDHXs32:
+    case MVE_VQDMLSDHXs8:
+    case MVE_VQDMLSDHs16:
+    case MVE_VQDMLSDHs32:
+    case MVE_VQDMLSDHs8:
+    case MVE_VQRDMLADHXs16:
+    case MVE_VQRDMLADHXs32:
+    case MVE_VQRDMLADHXs8:
+    case MVE_VQRDMLADHs16:
+    case MVE_VQRDMLADHs32:
+    case MVE_VQRDMLADHs8:
+    case MVE_VQRDMLAH_qrs16:
+    case MVE_VQRDMLAH_qrs32:
+    case MVE_VQRDMLAH_qrs8:
+    case MVE_VQRDMLASH_qrs16:
+    case MVE_VQRDMLASH_qrs32:
+    case MVE_VQRDMLASH_qrs8:
+    case MVE_VQRDMLSDHXs16:
+    case MVE_VQRDMLSDHXs32:
+    case MVE_VQRDMLSDHXs8:
+    case MVE_VQRDMLSDHs16:
+    case MVE_VQRDMLSDHs32:
+    case MVE_VQRDMLSDHs8:
+    case MVE_VQRSHRNbhs16:
+    case MVE_VQRSHRNbhs32:
+    case MVE_VQRSHRNbhu16:
+    case MVE_VQRSHRNbhu32:
+    case MVE_VQRSHRNths16:
+    case MVE_VQRSHRNths32:
+    case MVE_VQRSHRNthu16:
+    case MVE_VQRSHRNthu32:
+    case MVE_VQRSHRUNs16bh:
+    case MVE_VQRSHRUNs16th:
+    case MVE_VQRSHRUNs32bh:
+    case MVE_VQRSHRUNs32th:
+    case MVE_VQSHRNbhs16:
+    case MVE_VQSHRNbhs32:
+    case MVE_VQSHRNbhu16:
+    case MVE_VQSHRNbhu32:
+    case MVE_VQSHRNths16:
+    case MVE_VQSHRNths32:
+    case MVE_VQSHRNthu16:
+    case MVE_VQSHRNthu32:
+    case MVE_VQSHRUNs16bh:
+    case MVE_VQSHRUNs16th:
+    case MVE_VQSHRUNs32bh:
+    case MVE_VQSHRUNs32th:
+    case MVE_VREV16_8:
+    case MVE_VREV32_16:
+    case MVE_VREV32_8:
+    case MVE_VREV64_16:
+    case MVE_VREV64_32:
+    case MVE_VREV64_8:
+    case MVE_VRSHRNi16bh:
+    case MVE_VRSHRNi16th:
+    case MVE_VRSHRNi32bh:
+    case MVE_VRSHRNi32th:
+    case MVE_VSHRNi16bh:
+    case MVE_VSHRNi16th:
+    case MVE_VSHRNi32bh:
+    case MVE_VSHRNi32th:
+    case MVE_VLD20_16:
+    case MVE_VLD20_16_wb:
+    case MVE_VLD20_32:
+    case MVE_VLD20_32_wb:
+    case MVE_VLD20_8:
+    case MVE_VLD20_8_wb:
+    case MVE_VLD21_16:
+    case MVE_VLD21_16_wb:
+    case MVE_VLD21_32:
+    case MVE_VLD21_32_wb:
+    case MVE_VLD21_8:
+    case MVE_VLD21_8_wb:
+    case MVE_VLD40_16:
+    case MVE_VLD40_16_wb:
+    case MVE_VLD40_32:
+    case MVE_VLD40_32_wb:
+    case MVE_VLD40_8:
+    case MVE_VLD40_8_wb:
+    case MVE_VLD41_16:
+    case MVE_VLD41_16_wb:
+    case MVE_VLD41_32:
+    case MVE_VLD41_32_wb:
+    case MVE_VLD41_8:
+    case MVE_VLD41_8_wb:
+    case MVE_VLD42_16:
+    case MVE_VLD42_16_wb:
+    case MVE_VLD42_32:
+    case MVE_VLD42_32_wb:
+    case MVE_VLD42_8:
+    case MVE_VLD42_8_wb:
+    case MVE_VLD43_16:
+    case MVE_VLD43_16_wb:
+    case MVE_VLD43_32:
+    case MVE_VLD43_32_wb:
+    case MVE_VLD43_8:
+    case MVE_VLD43_8_wb:
+    case MVE_VST20_16:
+    case MVE_VST20_16_wb:
+    case MVE_VST20_32:
+    case MVE_VST20_32_wb:
+    case MVE_VST20_8:
+    case MVE_VST20_8_wb:
+    case MVE_VST21_16:
+    case MVE_VST21_16_wb:
+    case MVE_VST21_32:
+    case MVE_VST21_32_wb:
+    case MVE_VST21_8:
+    case MVE_VST21_8_wb:
+    case MVE_VST40_16:
+    case MVE_VST40_16_wb:
+    case MVE_VST40_32:
+    case MVE_VST40_32_wb:
+    case MVE_VST40_8:
+    case MVE_VST40_8_wb:
+    case MVE_VST41_16:
+    case MVE_VST41_16_wb:
+    case MVE_VST41_32:
+    case MVE_VST41_32_wb:
+    case MVE_VST41_8:
+    case MVE_VST41_8_wb:
+    case MVE_VST42_16:
+    case MVE_VST42_16_wb:
+    case MVE_VST42_32:
+    case MVE_VST42_32_wb:
+    case MVE_VST42_8:
+    case MVE_VST42_8_wb:
+    case MVE_VST43_16:
+    case MVE_VST43_16_wb:
+    case MVE_VST43_32:
+    case MVE_VST43_32_wb:
+    case MVE_VST43_8:
+    case MVE_VST43_8_wb:
       return true;
     default:
       return false;