diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2675,6 +2675,23 @@
     }
   }
 
+  // or(ashr(sub(C, V), ScalarSizeInBits - 1), V)  --> V s> C ? -1 : V, where
+  // sub hasNoSignedWrap.
+  {
+    Value *V;
+    const APInt *C, *ShAmt;
+    Type *Ty = I.getType();
+    if (match(&I, m_c_Or(m_OneUse(m_AShr(m_NSWSub(m_APInt(C), m_Value(V)),
+                                         m_APInt(ShAmt))),
+                         m_Deferred(V))) &&
+        *ShAmt == Ty->getScalarSizeInBits() - 1) {
+      Value *NewICmpInst =
+          Builder.CreateICmpSGT(V, ConstantInt::getIntegerValue(Ty, *C));
+      return SelectInst::Create(NewICmpInst, ConstantInt::getAllOnesValue(Ty),
+                                V);
+    }
+  }
+
   return nullptr;
 }
 
diff --git a/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll b/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
--- a/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
@@ -11,9 +11,8 @@
 
 define i32 @clamp255_i32(i32 %v) {
 ; CHECK-LABEL: @clamp255_i32(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[V:%.*]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 [[V]], i32 255
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[OR]], 255
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
@@ -26,9 +25,8 @@
 
 define i8 @sub_ashr_or_i8(i8 %v) {
 ; CHECK-LABEL: @sub_ashr_or_i8(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i8 15, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i8 [[SUB]], 7
-; CHECK-NEXT:    [[OR:%.*]] = or i8 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[V:%.*]], 15
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i8 -1, i8 [[V]]
 ; CHECK-NEXT:    ret i8 [[OR]]
 ;
   %sub = sub nsw i8 15, %v
@@ -39,9 +37,8 @@
 
 define i16 @sub_ashr_or_i16(i16 %v) {
 ; CHECK-LABEL: @sub_ashr_or_i16(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i16 255, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i16 [[SUB]], 15
-; CHECK-NEXT:    [[OR:%.*]] = or i16 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i16 [[V:%.*]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i16 -1, i16 [[V]]
 ; CHECK-NEXT:    ret i16 [[OR]]
 ;
   %sub = sub nsw i16 255, %v
@@ -52,9 +49,8 @@
 
 define i32 @sub_ashr_or_i32(i32 %v) {
 ; CHECK-LABEL: @sub_ashr_or_i32(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[V]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nsw i32 255, %v
@@ -65,9 +61,8 @@
 
 define i64 @sub_ashr_or_i64(i64 %v) {
 ; CHECK-LABEL: @sub_ashr_or_i64(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i64 65535, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i64 [[SUB]], 63
-; CHECK-NEXT:    [[OR:%.*]] = or i64 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i64 [[V:%.*]], 65535
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i64 -1, i64 [[V]]
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
   %sub = sub nsw i64 65535, %v
@@ -80,9 +75,8 @@
 
 define i32 @sub_ashr_or_i32_nuw_nsw(i32 %v) {
 ; CHECK-LABEL: @sub_ashr_or_i32_nuw_nsw(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 255, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[V]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nuw nsw i32 255, %v
@@ -95,9 +89,8 @@
 
 define i32 @sub_ashr_or_i32_commute(i32 %v) {
 ; CHECK-LABEL: @sub_ashr_or_i32_commute(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[V]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nsw i32 255, %v
@@ -110,9 +103,8 @@
 
 define <4 x i32> @sub_ashr_or_i32_vec(<4 x i32> %v) {
 ; CHECK-LABEL: @sub_ashr_or_i32_vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT:    [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[V:%.*]], <i32 255, i32 255, i32 255, i32 255>
+; CHECK-NEXT:    [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[V]]
 ; CHECK-NEXT:    ret <4 x i32> [[OR]]
 ;
   %sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
@@ -123,9 +115,8 @@
 
 define <4 x i32> @sub_ashr_or_i32_vec_nuw_nsw(<4 x i32> %v) {
 ; CHECK-LABEL: @sub_ashr_or_i32_vec_nuw_nsw(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT:    [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[V:%.*]], <i32 255, i32 255, i32 255, i32 255>
+; CHECK-NEXT:    [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[V]]
 ; CHECK-NEXT:    ret <4 x i32> [[OR]]
 ;
   %sub = sub nuw nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
@@ -136,9 +127,8 @@
 
 define <4 x i32> @sub_ashr_or_i32_vec_commute(<4 x i32> %v) {
 ; CHECK-LABEL: @sub_ashr_or_i32_vec_commute(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT:    [[OR:%.*]] = or <4 x i32> [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[V:%.*]], <i32 255, i32 255, i32 255, i32 255>
+; CHECK-NEXT:    [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[V]]
 ; CHECK-NEXT:    ret <4 x i32> [[OR]]
 ;
   %sub = sub nsw <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %v
@@ -153,8 +143,8 @@
 ; CHECK-LABEL: @sub_ashr_or_i32_extra_use_sub(
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
 ; CHECK-NEXT:    store i32 [[SUB]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[V]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nsw i32 255, %v
@@ -166,9 +156,8 @@
 
 define i32 @sub_ashr_or_i32_extra_use_or(i32 %v, i32* %p) {
 ; CHECK-LABEL: @sub_ashr_or_i32_extra_use_or(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 255, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 255
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[V]]
 ; CHECK-NEXT:    store i32 [[OR]], i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;