diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -1924,6 +1924,22 @@
       A->getType()->isIntOrIntVectorTy(1))
     return SelectInst::Create(A, Op0, Constant::getNullValue(I.getType()));
 
+  // and(ashr(sub(0, V), ScalarSizeInBits -1), V) --> V s< 0 ? 0 : V, where sub
+  // hasNoSignedWrap.
+  {
+    Value *V;
+    const APInt *ShAmt;
+    Type *Ty = I.getType();
+    if (match(&I, m_c_And(m_OneUse(m_AShr(m_NSWSub(m_Zero(), m_Value(V)),
+                                          m_APInt(ShAmt))),
+                          m_Deferred(V))) &&
+        *ShAmt == Ty->getScalarSizeInBits() - 1) {
+      Value *NewICmpInst =
+          Builder.CreateICmpSLT(V, ConstantInt::getNullValue(Ty));
+      return SelectInst::Create(NewICmpInst, ConstantInt::getNullValue(Ty), V);
+    }
+  }
+
   return nullptr;
 }
 
diff --git a/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll b/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
--- a/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
+++ b/llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
@@ -11,9 +11,8 @@
 
 define i8 @sub_ashr_and_i8(i8 %v) {
 ; CHECK-LABEL: @sub_ashr_and_i8(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i8 0, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i8 [[SUB]], 7
-; CHECK-NEXT:    [[AND:%.*]] = and i8 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[V:%.*]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i8 [[V]], i8 0
 ; CHECK-NEXT:    ret i8 [[AND]]
 ;
   %sub = sub nsw i8 0, %v
@@ -24,9 +23,8 @@
 
 define i16 @sub_ashr_and_i16(i16 %v) {
 ; CHECK-LABEL: @sub_ashr_and_i16(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i16 0, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i16 [[SUB]], 15
-; CHECK-NEXT:    [[AND:%.*]] = and i16 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i16 [[V:%.*]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i16 [[V]], i16 0
 ; CHECK-NEXT:    ret i16 [[AND]]
 ;
 
@@ -38,9 +36,8 @@
 
 define i32 @sub_ashr_and_i32(i32 %v) {
 ; CHECK-LABEL: @sub_ashr_and_i32(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[V]], i32 0
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 0, %v
@@ -51,9 +48,8 @@
 
 define i64 @sub_ashr_and_i64(i64 %v) {
 ; CHECK-LABEL: @sub_ashr_and_i64(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i64 0, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i64 [[SUB]], 63
-; CHECK-NEXT:    [[AND:%.*]] = and i64 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i64 [[V:%.*]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i64 [[V]], i64 0
 ; CHECK-NEXT:    ret i64 [[AND]]
 ;
   %sub = sub nsw i64 0, %v
@@ -78,9 +74,8 @@
 
 define i32 @sub_ashr_and_i32_commute(i32 %v) {
 ; CHECK-LABEL: @sub_ashr_and_i32_commute(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[V]], i32 0
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 0, %v
@@ -93,9 +88,8 @@
 
 define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %v) {
 ; CHECK-LABEL: @sub_ashr_and_i32_vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[V:%.*]], zeroinitializer
+; CHECK-NEXT:    [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[V]], <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x i32> [[AND]]
 ;
   %sub = sub nsw <4 x i32> zeroinitializer, %v
@@ -116,9 +110,8 @@
 
 define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %v) {
 ; CHECK-LABEL: @sub_ashr_and_i32_vec_commute(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[V:%.*]], zeroinitializer
+; CHECK-NEXT:    [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[V]], <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x i32> [[AND]]
 ;
   %sub = sub nsw <4 x i32> zeroinitializer, %v
@@ -133,8 +126,8 @@
 ; CHECK-LABEL: @sub_ashr_and_i32_extra_use_sub(
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
 ; CHECK-NEXT:    store i32 [[SUB]], i32* [[P:%.*]], align 4
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[V]], i32 0
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 0, %v
@@ -146,9 +139,8 @@
 
 define i32 @sub_ashr_and_i32_extra_use_and(i32 %v, i32* %p) {
 ; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[V:%.*]]
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHR]], [[V]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[V:%.*]], 0
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[V]], i32 0
 ; CHECK-NEXT:    store i32 [[AND]], i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;