Index: llvm/lib/Target/PowerPC/P9InstrResources.td =================================================================== --- llvm/lib/Target/PowerPC/P9InstrResources.td +++ llvm/lib/Target/PowerPC/P9InstrResources.td @@ -150,6 +150,10 @@ (instregex "ADD(4|8)(TLS)?(_)?$"), (instregex "NEG(8)?$"), (instregex "ADDI(S)?toc(HA|L)(8)?$"), + (instregex "ADDIS(dt|gotT)prelHA(32)?$"), + (instregex "ADDIStls(g|l)dHA?$"), + (instregex "ADDI(dtprel|tlsgd|tlsld)L(32)?$"), + (instregex "ADDItls(g|l)dLADDR(32)?$"), COPY, MCRF, MCRXRX, @@ -743,10 +747,14 @@ (instregex "LWARX(L)?$"), (instregex "LWBRX(8)?$"), (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"), + (instregex "LDgotTprelL(32)?$"), + (instregex "LDtoc(L|BA|CPT|JTI)?$"), + (instregex "LWZtoc(L)?$"), CP_ABORT, DARN, EnforceIEIO, ISYNC, + CFENCE8, MSGSYNC, TLBSYNC, SYNC, @@ -758,6 +766,7 @@ // superslice. def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_3SLOTS_1C], (instrs + (instregex "SPILLTOVSR_(LD|ST)X?$"), LFIWZX, LFDX, LFD @@ -1295,6 +1304,7 @@ (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"), (instregex "BCLR(L)?(n)?$"), (instregex "BCTR(L)?(8)?$"), + (instregex "Move(GOT|PC)toLR(8)?$"), B, BA, BC, Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -93,7 +93,8 @@ } let Defs = [LR8] in - def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, + def MovePCtoLR8 : PPCEmitTimePseudoWithSchedInfo< + (outs), (ins), "#MovePCtoLR8", []>, PPC970_Unit_BRU; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { @@ -1046,19 +1047,23 @@ // The following four definitions are selected for small code model only. // Otherwise, we need to create two instructions to form a 32-bit offset, // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). -def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), +def LDtoc: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), "#LDtoc", [(set i64:$rD, (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; -def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), +def LDtocJTI: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), "#LDtocJTI", [(set i64:$rD, (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; -def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), +def LDtocCPT: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), "#LDtocCPT", [(set i64:$rD, (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; -def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), +def LDtocBA: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), "#LDtocCPT", [(set i64:$rD, (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; @@ -1099,24 +1104,29 @@ // Support for medium and large code model. let hasSideEffects = 0 in { let isReMaterializable = 1 in { -def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), - "#ADDIStocHA8", []>, isPPC64; -def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), +def ADDIStocHA8: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), + "#ADDIStocHA8", []>, isPPC64; +def ADDItocL: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), "#ADDItocL", []>, isPPC64; } let mayLoad = 1 in -def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), +def LDtocL: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), "#LDtocL", []>, isPPC64; } // Support for thread-local storage. -def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), +def ADDISgotTprelHA: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDISgotTprelHA", [(set i64:$rD, (PPCaddisGotTprelHA i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), +def LDgotTprelL: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), "#LDgotTprelL", [(set i64:$rD, (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, @@ -1127,12 +1137,14 @@ def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), (ADD8TLS $in, tglobaltlsaddr:$g)>; -def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), +def ADDIStlsgdHA: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDIStlsgdHA", [(set i64:$rD, (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), +def ADDItlsgdL : PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDItlsgdL", [(set i64:$rD, (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, @@ -1153,7 +1165,7 @@ let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in -def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), +def ADDItlsgdLADDR : PPCEmitTimePseudoWithSchedInfo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), "#ADDItlsgdLADDR", [(set i64:$rD, @@ -1161,12 +1173,14 @@ tglobaltlsaddr:$disp, tglobaltlsaddr:$sym))]>, isPPC64; -def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), +def ADDIStlsldHA: PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDIStlsldHA", [(set i64:$rD, (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), +def ADDItlsldL : PPCEmitTimePseudoWithSchedInfo< + (outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDItlsldL", [(set i64:$rD, (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, @@ -1185,7 +1199,7 @@ let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in -def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), +def ADDItlsldLADDR : PPCEmitTimePseudoWithSchedInfo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), "#ADDItlsldLADDR", [(set i64:$rD, @@ -1193,14 +1207,14 @@ tglobaltlsaddr:$disp, tglobaltlsaddr:$sym))]>, isPPC64; -def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), - "#ADDISdtprelHA", +def ADDISdtprelHA: PPCEmitTimePseudoWithSchedInfo<(outs g8rc:$rD), + (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDISdtprelHA", [(set i64:$rD, (PPCaddisDtprelHA i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), - "#ADDIdtprelL", +def ADDIdtprelL : PPCEmitTimePseudoWithSchedInfo<(outs g8rc:$rD), + (ins g8rc_nox0:$reg, s16imm64:$disp), "#ADDIdtprelL", [(set i64:$rD, (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -2148,6 +2148,12 @@ let hasNoSchedulingInfo = 1; } +// Pseudo instructions that require the scheduling information +class PPCEmitTimePseudoWithSchedInfo pattern> : PPCEmitTimePseudo { + let hasNoSchedulingInfo = 0; +} + // Instruction that require custom insertion support // a.k.a. ISelPseudos, however, these won't have isPseudo set class PPCCustomInserterPseudo pattern> - : PPCEmitTimePseudo { + : PPCEmitTimePseudoWithSchedInfo { let isPseudo = 1; } Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1354,10 +1354,12 @@ } let Defs = [LR] in - def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, + def MovePCtoLR : PPCEmitTimePseudoWithSchedInfo< + (outs), (ins), "#MovePCtoLR", []>, PPC970_Unit_BRU; let Defs = [LR] in - def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, + def MoveGOTtoLR : PPCEmitTimePseudoWithSchedInfo< + (outs), (ins), "#MoveGOTtoLR", []>, PPC970_Unit_BRU; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { @@ -3095,14 +3097,16 @@ def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", []>, NoEncode<"$rT">; -def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), +def LDgotTprelL32: PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), "#LDgotTprelL32", [(set i32:$rD, (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), (ADD4TLS $in, tglobaltlsaddr:$g)>; -def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), +def ADDItlsgdL32 : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), "#ADDItlsgdL32", [(set i32:$rD, (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; @@ -3118,14 +3122,15 @@ // are true defines while the rest of the Defs are clobbers. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in -def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), +def ADDItlsgdLADDR32 : PPCEmitTimePseudoWithSchedInfo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), "#ADDItlsgdLADDR32", [(set i32:$rD, (PPCaddiTlsgdLAddr i32:$reg, tglobaltlsaddr:$disp, tglobaltlsaddr:$sym))]>; -def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), +def ADDItlsldL32 : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), "#ADDItlsldL32", [(set i32:$rD, (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; @@ -3142,33 +3147,38 @@ // are true defines while the rest of the Defs are clobbers. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in -def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), +def ADDItlsldLADDR32 : PPCEmitTimePseudoWithSchedInfo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), "#ADDItlsldLADDR32", [(set i32:$rD, (PPCaddiTlsldLAddr i32:$reg, tglobaltlsaddr:$disp, tglobaltlsaddr:$sym))]>; -def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), +def ADDIdtprelL32 : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), "#ADDIdtprelL32", [(set i32:$rD, (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; -def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), +def ADDISdtprelHA32 : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), "#ADDISdtprelHA32", [(set i32:$rD, (PPCaddisDtprelHA i32:$reg, tglobaltlsaddr:$disp))]>; // Support for Position-independent code -def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), +def LWZtoc : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), "#LWZtoc", [(set i32:$rD, (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; -def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), +def LWZtocL : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), "#LWZtocL", [(set i32:$rD, (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; -def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), +def ADDIStocHA : PPCEmitTimePseudoWithSchedInfo< + (outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), "#ADDIStocHA", [(set i32:$rD, (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; Index: llvm/test/CodeGen/PowerPC/sms-cpy-1.ll =================================================================== --- llvm/test/CodeGen/PowerPC/sms-cpy-1.ll +++ llvm/test/CodeGen/PowerPC/sms-cpy-1.ll @@ -64,13 +64,13 @@ ; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: xori 5, 5, 84 ; CHECK-NEXT: cntlzw 5, 5 +; CHECK-NEXT: srwi 5, 5, 5 ; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: std 3, 104(1) ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: li 7, 0 ; CHECK-NEXT: li 8, 3 -; CHECK-NEXT: srwi 5, 5, 5 ; CHECK-NEXT: add 4, 4, 5 ; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: std 5, 120(1)