Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -6010,7 +6010,7 @@
     // If the shift amount is greater than 32 or has a greater bitwidth than 64
     // then do the default optimisation
     if (ShAmt->getValueType(0).getSizeInBits() > 64 ||
-        (Con && Con->getZExtValue() >= 32))
+        (Con && (Con->getZExtValue() == 0 || Con->getZExtValue() >= 32)))
       return SDValue();
 
     // Extract the lower 32 bits of the shift amount if it's not an i32
Index: llvm/test/CodeGen/Thumb2/lsll0.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/lsll0.ll
+++ llvm/test/CodeGen/Thumb2/lsll0.ll
@@ -6,18 +6,14 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrw.u32 q0, [r0]
 ; CHECK-NEXT:    vmov r1, s2
-; CHECK-NEXT:    sxth r2, r1
-; CHECK-NEXT:    asrs r1, r2, #31
-; CHECK-NEXT:    lsll r2, r1, #0
-; CHECK-NEXT:    rsbs r1, r2, #0
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    asr.w r12, r1, #31
 ; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    asrs r3, r2, #31
-; CHECK-NEXT:    lsll r2, r3, #0
+; CHECK-NEXT:    rsbs r1, r1, #0
 ; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    sxth r1, r1
 ; CHECK-NEXT:    sxth r2, r2
+; CHECK-NEXT:    asr.w r12, r1, #31
 ; CHECK-NEXT:    asrs r3, r2, #31
 ; CHECK-NEXT:    strd r2, r3, [r0]
 ; CHECK-NEXT:    strd r1, r12, [r0, #8]