Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -2654,6 +2654,16 @@
   let Inst{15} = 0;
 }
 
+// sub(0, and(shr(x, C), 1)) == SBFX(x, C, 1)
+// The shr can be sra or srl, or be not present (in which case shift is 0)
+// The last parameter ($msb) is really width-1, so 0.
+def : T2Pat<(sub (i32 0), (and rGPR:$Rn, (i32 1))),
+            (t2SBFX $Rn, (i32 0), (i32 0))>;
+def : T2Pat<(sub (i32 0), (and (srl rGPR:$Rn, (i32 imm:$C)), (i32 1))),
+            (t2SBFX $Rn, (i32 imm:$C), (i32 0))>;
+def : T2Pat<(sub (i32 0), (and (sra rGPR:$Rn, (i32 imm:$C)), (i32 1))),
+            (t2SBFX $Rn, (i32 imm:$C), (i32 0))>;
+
 def t2UBFX: T2TwoRegBitFI<
                 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
                  IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
Index: llvm/test/CodeGen/ARM/sbfx.ll
===================================================================
--- llvm/test/CodeGen/ARM/sbfx.ll
+++ llvm/test/CodeGen/ARM/sbfx.ll
@@ -82,8 +82,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_rsb(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %b = lshr i32 %a, 4
@@ -108,8 +107,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_rsb_and(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb_and:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %c = and i32 %a, 1
@@ -120,8 +118,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_shift31(i32 %a) {
 ; CHECK-LABEL: sbfx_shift31:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %ba = lshr i32 %a, 4
@@ -145,8 +142,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_trunci1(i32 %a) {
 ; CHECK-LABEL: sbfx_trunci1:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
 	%t1 = lshr i32 %a, 4
Index: llvm/test/CodeGen/Thumb2/bfx.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/bfx.ll
+++ llvm/test/CodeGen/Thumb2/bfx.ll
@@ -36,8 +36,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_rsb(i32 %a) {
 ; CHECK-LABEL: sbfx_rsb:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %b = lshr i32 %a, 4
@@ -49,8 +48,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_shift(i32 %a) {
 ; CHECK-LABEL: sbfx_shift:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
   %ba = lshr i32 %a, 4
@@ -62,8 +60,7 @@
 define arm_aapcs_vfpcc i32 @sbfx_trunci1(i32 %a) {
 ; CHECK-LABEL: sbfx_trunci1:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    ubfx r0, r0, #4, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #4, #1
 ; CHECK-NEXT:    bx lr
 entry:
 	%t1 = lshr i32 %a, 4
Index: llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
+++ llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
@@ -27,21 +27,17 @@
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
@@ -82,21 +78,17 @@
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
@@ -136,22 +128,18 @@
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vmov.i32 q1, #0xff
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
@@ -191,21 +179,17 @@
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r1, lr, #1
-; CHECK-NEXT:    ubfx r3, lr, #4, #1
-; CHECK-NEXT:    rsb.w r12, r1, #0
-; CHECK-NEXT:    movs r1, #0
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r3, lr, #4, #1
 ; CHECK-NEXT:    bfi r1, r12, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, lr, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, lr, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, lr, #12, #1
 ; CHECK-NEXT:    bfi r1, r3, #3, #1
 ; CHECK-NEXT:    lsls r3, r1, #31
 ; CHECK-NEXT:    itt ne
@@ -262,33 +246,25 @@
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
+; CHECK-NEXT:    movs r3, #0
 ; CHECK-NEXT:    vcmp.s16 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r3, lr, #1
-; CHECK-NEXT:    ubfx r1, lr, #2, #1
-; CHECK-NEXT:    rsb.w r12, r3, #0
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r1, lr, #2, #1
 ; CHECK-NEXT:    bfi r3, r12, #0, #1
 ; CHECK-NEXT:    bfi r3, r1, #1, #1
-; CHECK-NEXT:    ubfx r1, lr, #4, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #4, #1
 ; CHECK-NEXT:    bfi r3, r1, #2, #1
-; CHECK-NEXT:    ubfx r1, lr, #6, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #6, #1
 ; CHECK-NEXT:    bfi r3, r1, #3, #1
-; CHECK-NEXT:    ubfx r1, lr, #8, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #8, #1
 ; CHECK-NEXT:    bfi r3, r1, #4, #1
-; CHECK-NEXT:    ubfx r1, lr, #10, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #10, #1
 ; CHECK-NEXT:    bfi r3, r1, #5, #1
-; CHECK-NEXT:    ubfx r1, lr, #12, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #12, #1
 ; CHECK-NEXT:    bfi r3, r1, #6, #1
-; CHECK-NEXT:    ubfx r1, lr, #14, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #14, #1
 ; CHECK-NEXT:    bfi r3, r1, #7, #1
 ; CHECK-NEXT:    uxtb r1, r3
 ; CHECK-NEXT:    lsls r3, r3, #31
@@ -345,33 +321,25 @@
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
+; CHECK-NEXT:    movs r3, #0
 ; CHECK-NEXT:    vcmp.s16 gt, q0, zr
 ; CHECK-NEXT:    @ implicit-def: $q0
 ; CHECK-NEXT:    vmrs lr, p0
-; CHECK-NEXT:    and r3, lr, #1
-; CHECK-NEXT:    ubfx r1, lr, #2, #1
-; CHECK-NEXT:    rsb.w r12, r3, #0
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r12, lr, #0, #1
+; CHECK-NEXT:    sbfx r1, lr, #2, #1
 ; CHECK-NEXT:    bfi r3, r12, #0, #1
 ; CHECK-NEXT:    bfi r3, r1, #1, #1
-; CHECK-NEXT:    ubfx r1, lr, #4, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #4, #1
 ; CHECK-NEXT:    bfi r3, r1, #2, #1
-; CHECK-NEXT:    ubfx r1, lr, #6, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #6, #1
 ; CHECK-NEXT:    bfi r3, r1, #3, #1
-; CHECK-NEXT:    ubfx r1, lr, #8, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #8, #1
 ; CHECK-NEXT:    bfi r3, r1, #4, #1
-; CHECK-NEXT:    ubfx r1, lr, #10, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #10, #1
 ; CHECK-NEXT:    bfi r3, r1, #5, #1
-; CHECK-NEXT:    ubfx r1, lr, #12, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #12, #1
 ; CHECK-NEXT:    bfi r3, r1, #6, #1
-; CHECK-NEXT:    ubfx r1, lr, #14, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    sbfx r1, lr, #14, #1
 ; CHECK-NEXT:    bfi r3, r1, #7, #1
 ; CHECK-NEXT:    uxtb r1, r3
 ; CHECK-NEXT:    lsls r3, r3, #31
@@ -443,37 +411,29 @@
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    vldrh.u16 q0, [r1]
+; CHECK-NEXT:    movs r3, #0
 ; CHECK-NEXT:    vcmp.s16 gt, q0, zr
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrht.u16 q0, [r2]
 ; CHECK-NEXT:    vmrs r1, p0
-; CHECK-NEXT:    and r2, r1, #1
-; CHECK-NEXT:    rsbs r3, r2, #0
-; CHECK-NEXT:    movs r2, #0
-; CHECK-NEXT:    bfi r2, r3, #0, #1
-; CHECK-NEXT:    ubfx r3, r1, #2, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, r1, #4, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #2, #1
-; CHECK-NEXT:    ubfx r3, r1, #6, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #3, #1
-; CHECK-NEXT:    ubfx r3, r1, #8, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #4, #1
-; CHECK-NEXT:    ubfx r3, r1, #10, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #5, #1
-; CHECK-NEXT:    ubfx r3, r1, #12, #1
-; CHECK-NEXT:    ubfx r1, r1, #14, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
-; CHECK-NEXT:    bfi r2, r3, #6, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
-; CHECK-NEXT:    bfi r2, r1, #7, #1
-; CHECK-NEXT:    uxtb r1, r2
-; CHECK-NEXT:    lsls r2, r2, #31
+; CHECK-NEXT:    sbfx r2, r1, #0, #1
+; CHECK-NEXT:    bfi r3, r2, #0, #1
+; CHECK-NEXT:    sbfx r2, r1, #2, #1
+; CHECK-NEXT:    bfi r3, r2, #1, #1
+; CHECK-NEXT:    sbfx r2, r1, #4, #1
+; CHECK-NEXT:    bfi r3, r2, #2, #1
+; CHECK-NEXT:    sbfx r2, r1, #6, #1
+; CHECK-NEXT:    bfi r3, r2, #3, #1
+; CHECK-NEXT:    sbfx r2, r1, #8, #1
+; CHECK-NEXT:    bfi r3, r2, #4, #1
+; CHECK-NEXT:    sbfx r2, r1, #10, #1
+; CHECK-NEXT:    bfi r3, r2, #5, #1
+; CHECK-NEXT:    sbfx r2, r1, #12, #1
+; CHECK-NEXT:    bfi r3, r2, #6, #1
+; CHECK-NEXT:    sbfx r1, r1, #14, #1
+; CHECK-NEXT:    bfi r3, r1, #7, #1
+; CHECK-NEXT:    lsls r2, r3, #31
+; CHECK-NEXT:    uxtb r1, r3
 ; CHECK-NEXT:    itt ne
 ; CHECK-NEXT:    vmovne.u16 r2, q0[0]
 ; CHECK-NEXT:    strbne r2, [r0]
@@ -522,22 +482,18 @@
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrwt.u32 q0, [r2]
 ; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r1, r2, #1
-; CHECK-NEXT:    rsbs r3, r1, #0
-; CHECK-NEXT:    movs r1, #0
+; CHECK-NEXT:    sbfx r3, r2, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #0, #1
-; CHECK-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #4, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-NEXT:    ubfx r2, r2, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    sbfx r2, r2, #12, #1
 ; CHECK-NEXT:    bfi r1, r2, #3, #1
 ; CHECK-NEXT:    lsls r2, r1, #31
 ; CHECK-NEXT:    itt ne
@@ -572,22 +528,18 @@
 ; CHECK-NEXT:    .pad #4
 ; CHECK-NEXT:    sub sp, #4
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcmp.s32 gt, q0, zr
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrwt.u32 q0, [r2]
 ; CHECK-NEXT:    vmrs r2, p0
-; CHECK-NEXT:    and r1, r2, #1
-; CHECK-NEXT:    rsbs r3, r1, #0
-; CHECK-NEXT:    movs r1, #0
+; CHECK-NEXT:    sbfx r3, r2, #0, #1
 ; CHECK-NEXT:    bfi r1, r3, #0, #1
-; CHECK-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #4, #1
 ; CHECK-NEXT:    bfi r1, r3, #1, #1
-; CHECK-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-NEXT:    ubfx r2, r2, #12, #1
-; CHECK-NEXT:    rsbs r3, r3, #0
+; CHECK-NEXT:    sbfx r3, r2, #8, #1
 ; CHECK-NEXT:    bfi r1, r3, #2, #1
-; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    sbfx r2, r2, #12, #1
 ; CHECK-NEXT:    bfi r1, r2, #3, #1
 ; CHECK-NEXT:    lsls r2, r1, #31
 ; CHECK-NEXT:    itt ne
Index: llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
@@ -218,19 +218,15 @@
 ; CHECK-LE-NEXT:    .pad #4
 ; CHECK-LE-NEXT:    sub sp, #4
 ; CHECK-LE-NEXT:    vcmp.i32 eq, q0, zr
-; CHECK-LE-NEXT:    vmrs r1, p0
-; CHECK-LE-NEXT:    and r0, r1, #1
-; CHECK-LE-NEXT:    rsbs r2, r0, #0
 ; CHECK-LE-NEXT:    movs r0, #0
+; CHECK-LE-NEXT:    vmrs r1, p0
+; CHECK-LE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-LE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-LE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-LE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-LE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-LE-NEXT:    rsbs r1, r1, #0
+; CHECK-LE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-LE-NEXT:    bfi r0, r1, #3, #1
 ; CHECK-LE-NEXT:    add sp, #4
 ; CHECK-LE-NEXT:    bx lr
@@ -240,20 +236,16 @@
 ; CHECK-BE-NEXT:    .pad #4
 ; CHECK-BE-NEXT:    sub sp, #4
 ; CHECK-BE-NEXT:    vrev64.32 q1, q0
+; CHECK-BE-NEXT:    movs r0, #0
 ; CHECK-BE-NEXT:    vcmp.i32 eq, q1, zr
 ; CHECK-BE-NEXT:    vmrs r1, p0
-; CHECK-BE-NEXT:    and r0, r1, #1
-; CHECK-BE-NEXT:    rsbs r2, r0, #0
-; CHECK-BE-NEXT:    movs r0, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-BE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-BE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-BE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-BE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-BE-NEXT:    rsbs r1, r1, #0
+; CHECK-BE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-BE-NEXT:    bfi r0, r1, #3, #1
 ; CHECK-BE-NEXT:    add sp, #4
 ; CHECK-BE-NEXT:    bx lr
@@ -269,33 +261,25 @@
 ; CHECK-LE-NEXT:    .pad #8
 ; CHECK-LE-NEXT:    sub sp, #8
 ; CHECK-LE-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-LE-NEXT:    vmrs r1, p0
-; CHECK-LE-NEXT:    and r0, r1, #1
-; CHECK-LE-NEXT:    rsbs r2, r0, #0
-; CHECK-LE-NEXT:    movs r0, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #2, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #6, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #3, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #4, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #10, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #5, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #12, #1
-; CHECK-LE-NEXT:    ubfx r1, r1, #14, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r0, r2, #6, #1
-; CHECK-LE-NEXT:    rsbs r1, r1, #0
-; CHECK-LE-NEXT:    bfi r0, r1, #7, #1
-; CHECK-LE-NEXT:    uxtb r0, r0
+; CHECK-LE-NEXT:    movs r2, #0
+; CHECK-LE-NEXT:    vmrs r0, p0
+; CHECK-LE-NEXT:    sbfx r1, r0, #0, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #0, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #2, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #1, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #4, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #2, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #6, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #3, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #8, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #4, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #10, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #5, #1
+; CHECK-LE-NEXT:    sbfx r1, r0, #12, #1
+; CHECK-LE-NEXT:    bfi r2, r1, #6, #1
+; CHECK-LE-NEXT:    sbfx r0, r0, #14, #1
+; CHECK-LE-NEXT:    bfi r2, r0, #7, #1
+; CHECK-LE-NEXT:    uxtb r0, r2
 ; CHECK-LE-NEXT:    add sp, #8
 ; CHECK-LE-NEXT:    bx lr
 ;
@@ -304,34 +288,26 @@
 ; CHECK-BE-NEXT:    .pad #8
 ; CHECK-BE-NEXT:    sub sp, #8
 ; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    movs r2, #0
 ; CHECK-BE-NEXT:    vcmp.i16 eq, q1, zr
-; CHECK-BE-NEXT:    vmrs r1, p0
-; CHECK-BE-NEXT:    and r0, r1, #1
-; CHECK-BE-NEXT:    rsbs r2, r0, #0
-; CHECK-BE-NEXT:    movs r0, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #0, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #2, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #1, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #2, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #6, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #3, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #4, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #10, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #5, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #12, #1
-; CHECK-BE-NEXT:    ubfx r1, r1, #14, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r0, r2, #6, #1
-; CHECK-BE-NEXT:    rsbs r1, r1, #0
-; CHECK-BE-NEXT:    bfi r0, r1, #7, #1
-; CHECK-BE-NEXT:    uxtb r0, r0
+; CHECK-BE-NEXT:    vmrs r0, p0
+; CHECK-BE-NEXT:    sbfx r1, r0, #0, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #0, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #2, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #1, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #4, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #2, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #6, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #3, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #8, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #4, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #10, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #5, #1
+; CHECK-BE-NEXT:    sbfx r1, r0, #12, #1
+; CHECK-BE-NEXT:    bfi r2, r1, #6, #1
+; CHECK-BE-NEXT:    sbfx r0, r0, #14, #1
+; CHECK-BE-NEXT:    bfi r2, r0, #7, #1
+; CHECK-BE-NEXT:    uxtb r0, r2
 ; CHECK-BE-NEXT:    add sp, #8
 ; CHECK-BE-NEXT:    bx lr
 entry:
Index: llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
@@ -8,8 +8,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #4
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
@@ -27,8 +26,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #12, #4
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
@@ -46,8 +44,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #4
 ; CHECK-NEXT:    bfi r1, r0, #4, #4
 ; CHECK-NEXT:    bfi r1, r0, #8, #4
@@ -70,8 +67,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #2
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
@@ -89,8 +85,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #6, #2
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
@@ -108,8 +103,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #2
 ; CHECK-NEXT:    bfi r1, r0, #2, #2
 ; CHECK-NEXT:    bfi r1, r0, #4, #2
@@ -136,8 +130,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #1
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
@@ -155,8 +148,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #3, #1
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpsel q0, q0, q1
@@ -174,8 +166,7 @@
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    mov.w r1, #0
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #0, #1
 ; CHECK-NEXT:    bfi r1, r0, #1, #1
 ; CHECK-NEXT:    bfi r1, r0, #2, #1
@@ -209,8 +200,7 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vmov s8, r0
 ; CHECK-NEXT:    vldr s10, .LCPI9_0
 ; CHECK-NEXT:    vmov.f32 s9, s8
@@ -235,8 +225,7 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vmov s10, r0
 ; CHECK-NEXT:    vldr s8, .LCPI10_0
 ; CHECK-NEXT:    vmov.f32 s9, s8
@@ -261,8 +250,7 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    cmp r0, r1
 ; CHECK-NEXT:    cset r0, lo
-; CHECK-NEXT:    and r0, r0, #1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vdup.32 q2, r0
 ; CHECK-NEXT:    vbic q1, q1, q2
 ; CHECK-NEXT:    vand q0, q0, q2
Index: llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
@@ -203,11 +203,9 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov r1, s0
 ; CHECK-NEXT:    vmov r0, s2
-; CHECK-NEXT:    and r1, r1, #1
-; CHECK-NEXT:    rsbs r1, r1, #0
-; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    sbfx r1, r1, #0, #1
 ; CHECK-NEXT:    vmov.32 q1[0], r1
-; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    sbfx r0, r0, #0, #1
 ; CHECK-NEXT:    vmov.32 q1[1], r1
 ; CHECK-NEXT:    vmov.32 q1[2], r0
 ; CHECK-NEXT:    vmov.32 q1[3], r0
Index: llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
@@ -178,17 +178,13 @@
 ; CHECK-LE-NEXT:    vcmp.i32 eq, q0, zr
 ; CHECK-LE-NEXT:    movs r3, #0
 ; CHECK-LE-NEXT:    vmrs r1, p0
-; CHECK-LE-NEXT:    and r2, r1, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-LE-NEXT:    bfi r3, r2, #0, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-LE-NEXT:    bfi r3, r2, #1, #1
-; CHECK-LE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-LE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-LE-NEXT:    bfi r3, r2, #2, #1
-; CHECK-LE-NEXT:    rsbs r1, r1, #0
+; CHECK-LE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-LE-NEXT:    bfi r3, r1, #3, #1
 ; CHECK-LE-NEXT:    strb r3, [r0]
 ; CHECK-LE-NEXT:    bx lr
@@ -199,17 +195,13 @@
 ; CHECK-BE-NEXT:    movs r3, #0
 ; CHECK-BE-NEXT:    vcmp.i32 eq, q1, zr
 ; CHECK-BE-NEXT:    vmrs r1, p0
-; CHECK-BE-NEXT:    and r2, r1, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #0, #1
 ; CHECK-BE-NEXT:    bfi r3, r2, #0, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #4, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #4, #1
 ; CHECK-BE-NEXT:    bfi r3, r2, #1, #1
-; CHECK-BE-NEXT:    ubfx r2, r1, #8, #1
-; CHECK-BE-NEXT:    ubfx r1, r1, #12, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    sbfx r2, r1, #8, #1
 ; CHECK-BE-NEXT:    bfi r3, r2, #2, #1
-; CHECK-BE-NEXT:    rsbs r1, r1, #0
+; CHECK-BE-NEXT:    sbfx r1, r1, #12, #1
 ; CHECK-BE-NEXT:    bfi r3, r1, #3, #1
 ; CHECK-BE-NEXT:    strb r3, [r0]
 ; CHECK-BE-NEXT:    bx lr
@@ -223,66 +215,50 @@
 ; CHECK-LE-LABEL: store_v8i1:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    vcmp.i16 eq, q0, zr
-; CHECK-LE-NEXT:    vmrs r2, p0
-; CHECK-LE-NEXT:    and r1, r2, #1
-; CHECK-LE-NEXT:    rsbs r3, r1, #0
-; CHECK-LE-NEXT:    movs r1, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #0, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #2, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #1, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #2, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #6, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #3, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #4, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #10, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #5, #1
-; CHECK-LE-NEXT:    ubfx r3, r2, #12, #1
-; CHECK-LE-NEXT:    ubfx r2, r2, #14, #1
-; CHECK-LE-NEXT:    rsbs r3, r3, #0
-; CHECK-LE-NEXT:    bfi r1, r3, #6, #1
-; CHECK-LE-NEXT:    rsbs r2, r2, #0
-; CHECK-LE-NEXT:    bfi r1, r2, #7, #1
-; CHECK-LE-NEXT:    strb r1, [r0]
+; CHECK-LE-NEXT:    movs r3, #0
+; CHECK-LE-NEXT:    vmrs r1, p0
+; CHECK-LE-NEXT:    sbfx r2, r1, #0, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #0, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #2, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #1, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #4, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #2, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #6, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #3, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #8, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #4, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #10, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #5, #1
+; CHECK-LE-NEXT:    sbfx r2, r1, #12, #1
+; CHECK-LE-NEXT:    bfi r3, r2, #6, #1
+; CHECK-LE-NEXT:    sbfx r1, r1, #14, #1
+; CHECK-LE-NEXT:    bfi r3, r1, #7, #1
+; CHECK-LE-NEXT:    strb r3, [r0]
 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: store_v8i1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    vrev64.16 q1, q0
+; CHECK-BE-NEXT:    movs r3, #0
 ; CHECK-BE-NEXT:    vcmp.i16 eq, q1, zr
-; CHECK-BE-NEXT:    vmrs r2, p0
-; CHECK-BE-NEXT:    and r1, r2, #1
-; CHECK-BE-NEXT:    rsbs r3, r1, #0
-; CHECK-BE-NEXT:    movs r1, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #0, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #2, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #1, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #4, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #2, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #6, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #3, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #8, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #4, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #10, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #5, #1
-; CHECK-BE-NEXT:    ubfx r3, r2, #12, #1
-; CHECK-BE-NEXT:    ubfx r2, r2, #14, #1
-; CHECK-BE-NEXT:    rsbs r3, r3, #0
-; CHECK-BE-NEXT:    bfi r1, r3, #6, #1
-; CHECK-BE-NEXT:    rsbs r2, r2, #0
-; CHECK-BE-NEXT:    bfi r1, r2, #7, #1
-; CHECK-BE-NEXT:    strb r1, [r0]
+; CHECK-BE-NEXT:    vmrs r1, p0
+; CHECK-BE-NEXT:    sbfx r2, r1, #0, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #0, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #2, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #1, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #4, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #2, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #6, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #3, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #8, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #4, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #10, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #5, #1
+; CHECK-BE-NEXT:    sbfx r2, r1, #12, #1
+; CHECK-BE-NEXT:    bfi r3, r2, #6, #1
+; CHECK-BE-NEXT:    sbfx r1, r1, #14, #1
+; CHECK-BE-NEXT:    bfi r3, r1, #7, #1
+; CHECK-BE-NEXT:    strb r3, [r0]
 ; CHECK-BE-NEXT:    bx lr
 entry:
   %c = icmp eq <8 x i16> %a, zeroinitializer