Index: llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -167,12 +167,6 @@ return decodeRegisterClass(Inst, RegNo, QFRegs); } -static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) { - return decodeRegisterClass(Inst, RegNo, RRegs); -} - static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { Index: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp @@ -469,7 +469,7 @@ (ResultReg ? MRI.getRegClass(ResultReg) : (RC ? RC : (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) : - (VT == MVT::f32 ? (HasSPE ? &PPC::SPE4RCRegClass : &PPC::F4RCRegClass) : + (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) : (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : &PPC::GPRC_and_GPRC_NOR0RegClass))))); @@ -989,7 +989,7 @@ unsigned DestReg; auto RC = MRI.getRegClass(SrcReg); if (PPCSubTarget->hasSPE()) { - DestReg = createResultReg(&PPC::SPE4RCRegClass); + DestReg = createResultReg(&PPC::GPRCRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::EFSCFD), DestReg) .addReg(SrcReg); @@ -1229,9 +1229,9 @@ if (PPCSubTarget->hasSPE()) { DestReg = createResultReg(&PPC::GPRCRegClass); if (IsSigned) - Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ; + Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ; else - Opc = InRC == &PPC::SPE4RCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ; + Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ; } else if (isVSFRCRegClass(RC)) { DestReg = createResultReg(&PPC::VSFRCRegClass); if (DstVT == MVT::i32) @@ -2002,7 +2002,7 @@ const bool HasSPE = PPCSubTarget->hasSPE(); const TargetRegisterClass *RC; if (HasSPE) - RC = ((VT == MVT::f32) ? &PPC::SPE4RCRegClass : &PPC::SPERCRegClass); + RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass); else RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass); Index: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1886,8 +1886,7 @@ assert((!MF.getInfo()->mustSaveTOC() || (Reg != PPC::X2 && Reg != PPC::R2)) && "Not expecting to try to spill R2 in a function that must save TOC"); - if (PPC::GPRCRegClass.contains(Reg) || - PPC::SPE4RCRegClass.contains(Reg)) { + if (PPC::GPRCRegClass.contains(Reg)) { HasGPSaveArea = true; GPRegs.push_back(CSI[i]); Index: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp @@ -145,7 +145,7 @@ addRegisterClass(MVT::i32, &PPC::GPRCRegClass); if (!useSoftFloat()) { if (hasSPE()) { - addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass); + addRegisterClass(MVT::f32, &PPC::GPRCRegClass); addRegisterClass(MVT::f64, &PPC::SPERCRegClass); } else { addRegisterClass(MVT::f32, &PPC::F4RCRegClass); @@ -3482,7 +3482,7 @@ if (Subtarget.hasP8Vector()) RC = &PPC::VSSRCRegClass; else if (Subtarget.hasSPE()) - RC = &PPC::SPE4RCRegClass; + RC = &PPC::GPRCRegClass; else RC = &PPC::F4RCRegClass; break; @@ -14166,7 +14166,7 @@ case 'f': if (Subtarget.hasSPE()) { if (VT == MVT::f32 || VT == MVT::i32) - return std::make_pair(0U, &PPC::SPE4RCRegClass); + return std::make_pair(0U, &PPC::GPRCRegClass); if (VT == MVT::f64 || VT == MVT::i64) return std::make_pair(0U, &PPC::SPERCRegClass); } else { Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -90,7 +90,6 @@ SOK_QuadBitSpill, SOK_SpillToVSR, SOK_SPESpill, - SOK_SPE4Spill, SOK_LastOpcodeSpill // This must be last on the enum. }; @@ -967,11 +966,11 @@ getKillRegState(KillSrc); return; } else if (PPC::SPERCRegClass.contains(SrcReg) && - PPC::SPE4RCRegClass.contains(DestReg)) { + PPC::GPRCRegClass.contains(DestReg)) { BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg); getKillRegState(KillSrc); return; - } else if (PPC::SPE4RCRegClass.contains(SrcReg) && + } else if (PPC::GPRCRegClass.contains(SrcReg) && PPC::SPERCRegClass.contains(DestReg)) { BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg); getKillRegState(KillSrc); @@ -1010,8 +1009,6 @@ Opc = PPC::QVFMRb; else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) Opc = PPC::CROR; - else if (PPC::SPE4RCRegClass.contains(DestReg, SrcReg)) - Opc = PPC::OR; else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) Opc = PPC::EVOR; else @@ -1044,8 +1041,6 @@ OpcodeIndex = SOK_Float4Spill; } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { OpcodeIndex = SOK_SPESpill; - } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { - OpcodeIndex = SOK_SPE4Spill; } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { OpcodeIndex = SOK_CRSpill; } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { @@ -1084,8 +1079,6 @@ OpcodeIndex = SOK_Float4Spill; } else if (PPC::SPERCRegClass.contains(Reg)) { OpcodeIndex = SOK_SPESpill; - } else if (PPC::SPE4RCRegClass.contains(Reg)) { - OpcodeIndex = SOK_SPE4Spill; } else if (PPC::CRRCRegClass.contains(Reg)) { OpcodeIndex = SOK_CRSpill; } else if (PPC::CRBITRCRegClass.contains(Reg)) { @@ -1134,8 +1127,6 @@ OpcodeIndex = SOK_Float4Spill; } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { OpcodeIndex = SOK_SPESpill; - } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) { - OpcodeIndex = SOK_SPE4Spill; } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { OpcodeIndex = SOK_CRSpill; } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { @@ -1174,8 +1165,6 @@ OpcodeIndex = SOK_Float4Spill; } else if (PPC::SPERCRegClass.contains(Reg)) { OpcodeIndex = SOK_SPESpill; - } else if (PPC::SPE4RCRegClass.contains(Reg)) { - OpcodeIndex = SOK_SPE4Spill; } else if (PPC::CRRCRegClass.contains(Reg)) { OpcodeIndex = SOK_CRSpill; } else if (PPC::CRBITRCRegClass.contains(Reg)) { @@ -2433,7 +2422,7 @@ {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, - PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW}, + PPC::SPILLTOVSR_ST, PPC::EVSTDD}, // Power 9 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, @@ -2449,7 +2438,7 @@ {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, - PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ}, + PPC::SPILLTOVSR_LD, PPC::EVLDD}, // Power 9 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32, Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td @@ -579,7 +579,7 @@ def PPCRegSPE4RCAsmOperand : AsmOperandClass { let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; } -def spe4rc : RegisterOperand { +def spe4rc : RegisterOperand { let ParserMatchClass = PPCRegSPE4RCAsmOperand; } @@ -3188,21 +3188,21 @@ def : Pat<(shl i32:$rS, i32:$rB), (SLW $rS, $rB)>; -def : Pat<(zextloadi1 iaddr:$src), +def : Pat<(i32 (zextloadi1 iaddr:$src)), (LBZ iaddr:$src)>; -def : Pat<(zextloadi1 xaddr:$src), +def : Pat<(i32 (zextloadi1 xaddr:$src)), (LBZX xaddr:$src)>; -def : Pat<(extloadi1 iaddr:$src), +def : Pat<(i32 (extloadi1 iaddr:$src)), (LBZ iaddr:$src)>; -def : Pat<(extloadi1 xaddr:$src), +def : Pat<(i32 (extloadi1 xaddr:$src)), (LBZX xaddr:$src)>; -def : Pat<(extloadi8 iaddr:$src), +def : Pat<(i32 (extloadi8 iaddr:$src)), (LBZ iaddr:$src)>; -def : Pat<(extloadi8 xaddr:$src), +def : Pat<(i32 (extloadi8 xaddr:$src)), (LBZX xaddr:$src)>; -def : Pat<(extloadi16 iaddr:$src), +def : Pat<(i32 (extloadi16 iaddr:$src)), (LHZ iaddr:$src)>; -def : Pat<(extloadi16 xaddr:$src), +def : Pat<(i32 (extloadi16 xaddr:$src)), (LHZX xaddr:$src)>; let Predicates = [HasFPU] in { def : Pat<(f64 (extloadf32 iaddr:$src)), Index: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -425,7 +425,6 @@ case PPC::G8RC_NOX0RegClassID: case PPC::GPRC_NOR0RegClassID: case PPC::SPERCRegClassID: - case PPC::SPE4RCRegClassID: case PPC::G8RCRegClassID: case PPC::GPRCRegClassID: { unsigned FP = TFI->hasFP(MF) ? 1 : 0; Index: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td @@ -253,9 +253,9 @@ /// Register classes // Allocate volatiles first // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 -def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), - (sequence "R%u", 30, 13), - R31, R0, R1, FP, BP)> { +def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12), + (sequence "R%u", 30, 13), + R31, R0, R1, FP, BP)> { // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so // put it at the end of the list. let AltOrders = [(add (sub GPRC, R2), R2)]; @@ -278,7 +278,7 @@ // For some instructions r0 is special (representing the value 0 instead of // the value in the r0 register), and we use these register subclasses to // prevent r0 from being allocated for use by those instructions. -def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> { +def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> { // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so // put it at the end of the list. let AltOrders = [(add (sub GPRC_NOR0, R2), R2)]; @@ -300,8 +300,6 @@ (sequence "S%u", 30, 13), S31, S0, S1)>; -def SPE4RC : RegisterClass<"PPC", [f32], 32, (add GPRC)>; - // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 // ABI the size of the Floating-point register save area is determined by the // allocated non-volatile register with the lowest register number, as FP Index: llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll =================================================================== --- llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll +++ llvm/trunk/test/CodeGen/PowerPC/inc-of-add.ll @@ -170,7 +170,6 @@ ; PPC64BE-NEXT: std 23, -72(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 22, -80(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 26, -48(1) # 8-byte Folded Spill -; PPC64BE-NEXT: std 2, -96(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 25, -56(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 24, -64(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 29, -24(1) # 8-byte Folded Spill @@ -191,8 +190,8 @@ ; PPC64BE-NEXT: add 7, 12, 7 ; PPC64BE-NEXT: lbz 12, 239(1) ; PPC64BE-NEXT: lbz 26, 151(1) -; PPC64BE-NEXT: add 2, 21, 23 -; PPC64BE-NEXT: lbz 23, 279(1) +; PPC64BE-NEXT: add 23, 21, 23 +; PPC64BE-NEXT: lbz 21, 279(1) ; PPC64BE-NEXT: lbz 25, 143(1) ; PPC64BE-NEXT: add 11, 11, 22 ; PPC64BE-NEXT: lbz 22, 271(1) @@ -201,8 +200,8 @@ ; PPC64BE-NEXT: lbz 12, 263(1) ; PPC64BE-NEXT: lbz 30, 175(1) ; PPC64BE-NEXT: lbz 29, 303(1) -; PPC64BE-NEXT: add 26, 23, 26 -; PPC64BE-NEXT: lbz 23, 311(1) +; PPC64BE-NEXT: add 26, 21, 26 +; PPC64BE-NEXT: lbz 21, 311(1) ; PPC64BE-NEXT: std 28, -32(1) # 8-byte Folded Spill ; PPC64BE-NEXT: add 25, 22, 25 ; PPC64BE-NEXT: lbz 28, 167(1) @@ -212,7 +211,7 @@ ; PPC64BE-NEXT: lbz 27, 159(1) ; PPC64BE-NEXT: lbz 24, 287(1) ; PPC64BE-NEXT: add 30, 29, 30 -; PPC64BE-NEXT: add 29, 23, 0 +; PPC64BE-NEXT: add 29, 21, 0 ; PPC64BE-NEXT: addi 0, 29, 1 ; PPC64BE-NEXT: add 28, 22, 28 ; PPC64BE-NEXT: stb 0, 15(3) @@ -228,7 +227,7 @@ ; PPC64BE-NEXT: stb 0, 11(3) ; PPC64BE-NEXT: addi 0, 25, 1 ; PPC64BE-NEXT: stb 12, 9(3) -; PPC64BE-NEXT: addi 12, 2, 1 +; PPC64BE-NEXT: addi 12, 23, 1 ; PPC64BE-NEXT: addi 11, 11, 1 ; PPC64BE-NEXT: addi 10, 10, 1 ; PPC64BE-NEXT: addi 9, 9, 1 @@ -247,7 +246,6 @@ ; PPC64BE-NEXT: stb 6, 2(3) ; PPC64BE-NEXT: stb 5, 1(3) ; PPC64BE-NEXT: stb 4, 0(3) -; PPC64BE-NEXT: ld 2, -96(1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld 29, -24(1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld 28, -32(1) # 8-byte Folded Reload Index: llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll =================================================================== --- llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll +++ llvm/trunk/test/CodeGen/PowerPC/sub-of-not.ll @@ -170,7 +170,6 @@ ; PPC64BE-NEXT: std 23, -72(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 22, -80(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 26, -48(1) # 8-byte Folded Spill -; PPC64BE-NEXT: std 2, -96(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 25, -56(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 24, -64(1) # 8-byte Folded Spill ; PPC64BE-NEXT: std 29, -24(1) # 8-byte Folded Spill @@ -191,8 +190,8 @@ ; PPC64BE-NEXT: add 7, 12, 7 ; PPC64BE-NEXT: lbz 12, 239(1) ; PPC64BE-NEXT: lbz 26, 151(1) -; PPC64BE-NEXT: add 2, 21, 23 -; PPC64BE-NEXT: lbz 23, 279(1) +; PPC64BE-NEXT: add 23, 21, 23 +; PPC64BE-NEXT: lbz 21, 279(1) ; PPC64BE-NEXT: lbz 25, 143(1) ; PPC64BE-NEXT: add 11, 11, 22 ; PPC64BE-NEXT: lbz 22, 271(1) @@ -201,8 +200,8 @@ ; PPC64BE-NEXT: lbz 12, 263(1) ; PPC64BE-NEXT: lbz 30, 175(1) ; PPC64BE-NEXT: lbz 29, 303(1) -; PPC64BE-NEXT: add 26, 23, 26 -; PPC64BE-NEXT: lbz 23, 311(1) +; PPC64BE-NEXT: add 26, 21, 26 +; PPC64BE-NEXT: lbz 21, 311(1) ; PPC64BE-NEXT: std 28, -32(1) # 8-byte Folded Spill ; PPC64BE-NEXT: add 25, 22, 25 ; PPC64BE-NEXT: lbz 28, 167(1) @@ -212,7 +211,7 @@ ; PPC64BE-NEXT: lbz 27, 159(1) ; PPC64BE-NEXT: lbz 24, 287(1) ; PPC64BE-NEXT: add 30, 29, 30 -; PPC64BE-NEXT: add 29, 23, 0 +; PPC64BE-NEXT: add 29, 21, 0 ; PPC64BE-NEXT: addi 0, 29, 1 ; PPC64BE-NEXT: add 28, 22, 28 ; PPC64BE-NEXT: stb 0, 15(3) @@ -228,7 +227,7 @@ ; PPC64BE-NEXT: stb 0, 11(3) ; PPC64BE-NEXT: addi 0, 25, 1 ; PPC64BE-NEXT: stb 12, 9(3) -; PPC64BE-NEXT: addi 12, 2, 1 +; PPC64BE-NEXT: addi 12, 23, 1 ; PPC64BE-NEXT: addi 11, 11, 1 ; PPC64BE-NEXT: addi 10, 10, 1 ; PPC64BE-NEXT: addi 9, 9, 1 @@ -247,7 +246,6 @@ ; PPC64BE-NEXT: stb 6, 2(3) ; PPC64BE-NEXT: stb 5, 1(3) ; PPC64BE-NEXT: stb 4, 0(3) -; PPC64BE-NEXT: ld 2, -96(1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld 29, -24(1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld 28, -32(1) # 8-byte Folded Reload