diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1596,7 +1596,6 @@
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
-  CInst.setLoc(Inst.getLoc());
   S.EmitInstruction((Res ? CInst : Inst), getSTI());
 }
 
diff --git a/llvm/test/MC/RISCV/compress-debug-info.s b/llvm/test/MC/RISCV/compress-debug-info.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/compress-debug-info.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple riscv32 -mattr=+c %s -g -o - -riscv-no-aliases \
+# RUN:   | FileCheck %s -check-prefixes=COMPRESS,BOTH
+# RUN: llvm-mc -triple riscv32 %s -g -o - -riscv-no-aliases \
+# RUN:   | FileCheck %s -check-prefixes=UNCOMPRESS,BOTH
+
+
+# This file ensures that compressing an instruction preserves its debug info.
+
+
+# BOTH-LABEL: .text
+
+# BOTH: .file 1
+# BOTH-SAME: "compress-debug-info.s"
+
+# BOTH:            .loc 1 [[# @LINE + 3 ]] 0
+# UNCOMPRESS-NEXT: addi a0, a1, 0
+# COMPRESS-NEXT:   c.mv a0, a1
+addi a0, a1, 0
+
+# BOTH-LABEL: .debug_info
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -728,6 +728,7 @@
       }
       ++OpNo;
     }
+    CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
     CaseStream << mergeCondAndCode(CondStream, CodeStream);
     PrevOp = CurOp;
   }