Index: llvm/include/llvm/MC/MCInstrDesc.h
===================================================================
--- llvm/include/llvm/MC/MCInstrDesc.h
+++ llvm/include/llvm/MC/MCInstrDesc.h
@@ -167,6 +167,7 @@
   Add,
   Trap,
   VariadicOpsAreDefs,
+  VectorReduction,
 };
 }
 
@@ -310,6 +311,10 @@
     return isBranch() & isBarrier() & !isIndirectBranch();
   }
 
+  bool isVectorReduction() const {
+    return Flags & (1ULL << MCID::VectorReduction);
+  }
+
   /// Return true if this is a branch or an instruction which directly
   /// writes to the program counter. Considered 'may' affect rather than
   /// 'does' affect as things like predication are not taken into account.
Index: llvm/include/llvm/Target/Target.td
===================================================================
--- llvm/include/llvm/Target/Target.td
+++ llvm/include/llvm/Target/Target.td
@@ -493,6 +493,7 @@
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isAdd        = 0;     // Is this instruction an add instruction?
+  bit isVectorReduction = 0;
   bit isTrap       = 0;     // Is this instruction a trap instruction?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = ?;     // Is it possible for this inst to read memory?
Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -504,6 +504,8 @@
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+
+  let isVectorReduction = 1;
 }
 
 def MVE_VABAVs8  : MVE_VABAV<"s8", 0b0, 0b00>;
@@ -530,6 +532,8 @@
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VADDV_A<string suffix, bit U, bits<2> size,
@@ -580,6 +584,8 @@
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
@@ -617,6 +623,8 @@
   let Inst{0} = 0b0;
 
   let Predicates = [HasMVEFloat];
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMINMAXNMV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
@@ -653,6 +661,8 @@
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMINMAXV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
@@ -696,6 +706,8 @@
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
@@ -771,6 +783,8 @@
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMLALDAVBase_X<string iname, string suffix, dag iops,
Index: llvm/unittests/Target/ARM/CMakeLists.txt
===================================================================
--- /dev/null
+++ llvm/unittests/Target/ARM/CMakeLists.txt
@@ -0,0 +1,25 @@
+include_directories(
+  ${CMAKE_SOURCE_DIR}/lib/Target/ARM
+  ${CMAKE_BINARY_DIR}/lib/Target/ARM
+  )
+
+set(LLVM_LINK_COMPONENTS
+  ${LLVM_TARGETS_TO_BUILD}
+  Analysis
+  AsmParser
+  AsmPrinter
+  ARMCodeGen
+  ARMDesc
+  ARMInfo
+  CodeGen
+  Core
+  MC
+  MIRParser
+  SelectionDAG
+  Support
+  Target
+  )
+
+add_llvm_unittest(ARMTests
+  MachineInstrTest.cpp
+  )
Index: llvm/unittests/Target/ARM/MachineInstrTest.cpp
===================================================================
--- /dev/null
+++ llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -0,0 +1,170 @@
+#include "ARMBaseInstrInfo.h"
+#include "ARMSubtarget.h"
+#include "ARMTargetMachine.h"
+#include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+TEST(MachineInstrVecReductionFlag, IsCorrect) {
+  Triple TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
+  std::string Error;
+
+  LLVMInitializeARMTargetInfo();
+  LLVMInitializeARMTarget();
+  LLVMInitializeARMTargetMC();
+
+  const Target *T = TargetRegistry::lookupTarget("", TT, Error);
+  if (!T) {
+    dbgs() << Error;
+    return;
+  }
+
+  TargetOptions Options;
+  TargetMachine *TM = T->createTargetMachine("Thumb2", "", "", Options, None,
+                                             None, CodeGenOpt::Aggressive);
+  auto MII = TM->getMCInstrInfo();
+
+  auto IsVecReductionOpcode = [](unsigned Opcode) {
+    switch (Opcode) {
+    case ARM::MVE_VABAVs8:
+    case ARM::MVE_VABAVs16:
+    case ARM::MVE_VABAVs32:
+    case ARM::MVE_VABAVu8:
+    case ARM::MVE_VABAVu16:
+    case ARM::MVE_VABAVu32:
+    case ARM::MVE_VADDVs8acc:
+    case ARM::MVE_VADDVs16acc:
+    case ARM::MVE_VADDVs32acc:
+    case ARM::MVE_VADDVu8acc:
+    case ARM::MVE_VADDVu16acc:
+    case ARM::MVE_VADDVu32acc:
+    case ARM::MVE_VADDVs8no_acc:
+    case ARM::MVE_VADDVs16no_acc:
+    case ARM::MVE_VADDVs32no_acc:
+    case ARM::MVE_VADDVu8no_acc:
+    case ARM::MVE_VADDVu16no_acc:
+    case ARM::MVE_VADDVu32no_acc:
+    case ARM::MVE_VADDLVs32no_acc:
+    case ARM::MVE_VADDLVu32no_acc:
+    case ARM::MVE_VADDLVs32acc:
+    case ARM::MVE_VADDLVu32acc:
+    case ARM::MVE_VMAXNMVf16:
+    case ARM::MVE_VMINNMVf16:
+    case ARM::MVE_VMAXNMVf32:
+    case ARM::MVE_VMINNMVf32:
+    case ARM::MVE_VMAXNMAVf16:
+    case ARM::MVE_VMINNMAVf16:
+    case ARM::MVE_VMAXNMAVf32:
+    case ARM::MVE_VMINNMAVf32:
+    case ARM::MVE_VMAXVs8:
+    case ARM::MVE_VMAXVs16:
+    case ARM::MVE_VMAXVs32:
+    case ARM::MVE_VMAXVu8:
+    case ARM::MVE_VMAXVu16:
+    case ARM::MVE_VMAXVu32:
+    case ARM::MVE_VMINVs8:
+    case ARM::MVE_VMINVs16:
+    case ARM::MVE_VMINVs32:
+    case ARM::MVE_VMINVu8:
+    case ARM::MVE_VMINVu16:
+    case ARM::MVE_VMINVu32:
+    case ARM::MVE_VMAXAVs8:
+    case ARM::MVE_VMAXAVs16:
+    case ARM::MVE_VMAXAVs32:
+    case ARM::MVE_VMINAVs8:
+    case ARM::MVE_VMINAVs16:
+    case ARM::MVE_VMINAVs32:
+    case ARM::MVE_VMLADAVs8_noacc_noexch:
+    case ARM::MVE_VMLADAVs16_noacc_noexch:
+    case ARM::MVE_VMLADAVs32_noacc_noexch:
+    case ARM::MVE_VMLADAVu8_noacc_noexch:
+    case ARM::MVE_VMLADAVu16_noacc_noexch:
+    case ARM::MVE_VMLADAVu32_noacc_noexch:
+    case ARM::MVE_VMLADAVs8_acc_noexch:
+    case ARM::MVE_VMLADAVs16_acc_noexch:
+    case ARM::MVE_VMLADAVs32_acc_noexch:
+    case ARM::MVE_VMLADAVu8_acc_noexch:
+    case ARM::MVE_VMLADAVu16_acc_noexch:
+    case ARM::MVE_VMLADAVu32_acc_noexch:
+    case ARM::MVE_VMLADAVs8_noacc_exch:
+    case ARM::MVE_VMLADAVs16_noacc_exch:
+    case ARM::MVE_VMLADAVs32_noacc_exch:
+    case ARM::MVE_VMLADAVu8_noacc_exch:
+    case ARM::MVE_VMLADAVu16_noacc_exch:
+    case ARM::MVE_VMLADAVu32_noacc_exch:
+    case ARM::MVE_VMLADAVs8_acc_exch:
+    case ARM::MVE_VMLADAVs16_acc_exch:
+    case ARM::MVE_VMLADAVs32_acc_exch:
+    case ARM::MVE_VMLADAVu8_acc_exch:
+    case ARM::MVE_VMLADAVu16_acc_exch:
+    case ARM::MVE_VMLADAVu32_acc_exch:
+    case ARM::MVE_VMLALDAVs16_noacc_noexch:
+    case ARM::MVE_VMLALDAVs32_noacc_noexch:
+    case ARM::MVE_VMLALDAVu16_noacc_noexch:
+    case ARM::MVE_VMLALDAVu32_noacc_noexch:
+    case ARM::MVE_VMLALDAVs16_acc_noexch:
+    case ARM::MVE_VMLALDAVs32_acc_noexch:
+    case ARM::MVE_VMLALDAVu16_acc_noexch:
+    case ARM::MVE_VMLALDAVu32_acc_noexch:
+    case ARM::MVE_VMLALDAVs16_noacc_exch:
+    case ARM::MVE_VMLALDAVs32_noacc_exch:
+    case ARM::MVE_VMLALDAVu16_noacc_exch:
+    case ARM::MVE_VMLALDAVu32_noacc_exch:
+    case ARM::MVE_VMLALDAVs16_acc_exch:
+    case ARM::MVE_VMLALDAVs32_acc_exch:
+    case ARM::MVE_VMLALDAVu16_acc_exch:
+    case ARM::MVE_VMLALDAVu32_acc_exch:
+    case ARM::MVE_VMLSDAVs8_noacc_noexch:
+    case ARM::MVE_VMLSDAVs16_noacc_noexch:
+    case ARM::MVE_VMLSDAVs32_noacc_noexch:
+    case ARM::MVE_VMLSDAVs8_acc_noexch:
+    case ARM::MVE_VMLSDAVs16_acc_noexch:
+    case ARM::MVE_VMLSDAVs32_acc_noexch:
+    case ARM::MVE_VMLSDAVs8_noacc_exch:
+    case ARM::MVE_VMLSDAVs16_noacc_exch:
+    case ARM::MVE_VMLSDAVs32_noacc_exch:
+    case ARM::MVE_VMLSDAVs8_acc_exch:
+    case ARM::MVE_VMLSDAVs16_acc_exch:
+    case ARM::MVE_VMLSDAVs32_acc_exch:
+    case ARM::MVE_VMLSLDAVs16_noacc_noexch:
+    case ARM::MVE_VMLSLDAVs32_noacc_noexch:
+    case ARM::MVE_VMLSLDAVs16_acc_noexch:
+    case ARM::MVE_VMLSLDAVs32_acc_noexch:
+    case ARM::MVE_VMLSLDAVs16_noacc_exch:
+    case ARM::MVE_VMLSLDAVs32_noacc_exch:
+    case ARM::MVE_VMLSLDAVs16_acc_exch:
+    case ARM::MVE_VMLSLDAVs32_acc_exch:
+    case ARM::MVE_VRMLALDAVHs32_noacc_noexch:
+    case ARM::MVE_VRMLALDAVHs32_acc_noexch:
+    case ARM::MVE_VRMLALDAVHs32_noacc_exch:
+    case ARM::MVE_VRMLALDAVHs32_acc_exch:
+    case ARM::MVE_VRMLALDAVHu32_noacc_noexch:
+    case ARM::MVE_VRMLALDAVHu32_acc_noexch:
+    case ARM::MVE_VRMLALDAVHu32_noacc_exch:
+    case ARM::MVE_VRMLALDAVHu32_acc_exch:
+    case ARM::MVE_VRMLSLDAVHs32_noacc_noexch:
+    case ARM::MVE_VRMLSLDAVHs32_acc_noexch:
+    case ARM::MVE_VRMLSLDAVHs32_noacc_exch:
+    case ARM::MVE_VRMLSLDAVHs32_acc_exch:
+      return true;
+    default:
+      return false;
+    }
+  };
+
+  unsigned i = 0;
+  while (i < ARM::INSTRUCTION_LIST_END) {
+    ASSERT_EQ(IsVecReductionOpcode(i), MII->get(i).isVectorReduction())
+        << MII->getName(i)
+        << " has the wrong isVectorReduction flag value or should be added to "
+           "this test's list of vector reductions\n";
+    i++;
+  }
+}
Index: llvm/utils/TableGen/CodeGenInstruction.h
===================================================================
--- llvm/utils/TableGen/CodeGenInstruction.h
+++ llvm/utils/TableGen/CodeGenInstruction.h
@@ -243,6 +243,7 @@
     bool isBarrier : 1;
     bool isCall : 1;
     bool isAdd : 1;
+    bool isVectorReduction : 1;
     bool isTrap : 1;
     bool canFoldAsLoad : 1;
     bool mayLoad : 1;
Index: llvm/utils/TableGen/CodeGenInstruction.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenInstruction.cpp
+++ llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -375,6 +375,7 @@
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   isAdd        = R->getValueAsBit("isAdd");
+  isVectorReduction = R->getValueAsBit("isVectorReduction");
   isTrap       = R->getValueAsBit("isTrap");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
   isPredicable = !R->getValueAsBit("isUnpredicable") && (
Index: llvm/utils/TableGen/InstrDocsEmitter.cpp
===================================================================
--- llvm/utils/TableGen/InstrDocsEmitter.cpp
+++ llvm/utils/TableGen/InstrDocsEmitter.cpp
@@ -109,6 +109,7 @@
     FLAG(isBarrier)
     FLAG(isCall)
     FLAG(isAdd)
+    FLAG(isVectorReduction)
     FLAG(isTrap)
     FLAG(canFoldAsLoad)
     FLAG(mayLoad)
Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
===================================================================
--- llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -661,6 +661,7 @@
   if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
   if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
   if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
+  if (Inst.isVectorReduction)  OS << "|(1ULL<<MCID::VectorReduction)";
   if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";