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Differential D67320

[mips] Fix decoding of microMIPS JALX instruction
ClosedPublic

Authored by atanasyan on Sep 7 2019, 9:45 AM.

Details

Reviewers
Petar.Avramovic
• espindola
Commits
rG56e4ea2bff9e: [mips] Fix decoding of microMIPS JALX instruction
rL371428: [mips] Fix decoding of microMIPS JALX instruction
rLLD371428: [mips] Fix decoding of microMIPS JALX instruction
Summary

microMIPS jump and link exchange instruction stores a target in a 26-bits field. Despite other microMIPS JAL instructions these bits are target address shifted right 2 bits [1]. The patch fixes the JALX instruction decoding and uses 2-bit shift.

[1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set

Diff Detail

Repository
rL LLVM

Event Timeline

atanasyan created this revision.Sep 7 2019, 9:45 AM
Herald added a reviewer: • espindola. · View Herald TranscriptSep 7 2019, 9:45 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: MaskRay, jrtc27, hiraditya and 3 others. · View Herald Transcript
Petar.Avramovic accepted this revision.Sep 9 2019, 8:08 AM

LGTM.

This revision is now accepted and ready to land.Sep 9 2019, 8:08 AM
Closed by commit rL371428: [mips] Fix decoding of microMIPS JALX instruction (authored by atanasyan). · Explain WhySep 9 2019, 10:28 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lld/
trunk/
test/
ELF/
4 lines
llvm/
trunk/
lib/
Target/
Mips/
Disassembler/
16 lines
9 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
1 line
1 line

Diff 219390

lld/trunk/test/ELF/mips-micro-cross-calls.s

Show All 16 Lines
# REG-NEXT: 20004: 00 00 00 00 nop # REG-NEXT: 20004: 00 00 00 00 nop
# REG-NEXT: 20008: 74 00 80 08 jalx 131104 <__microLA25Thunk_foo> # REG-NEXT: 20008: 74 00 80 08 jalx 131104 <__microLA25Thunk_foo>
# REG: __LA25Thunk_bar: # REG: __LA25Thunk_bar:
# REG-NEXT: 20030: 3c 19 00 02 lui $25, 2 # REG-NEXT: 20030: 3c 19 00 02 lui $25, 2
# REG-NEXT: 20034: 08 00 80 11 j 131140 <bar> # REG-NEXT: 20034: 08 00 80 11 j 131140 <bar>
# MICRO: micro: # MICRO: micro:
# MICRO-NEXT: 20010: f0 00 80 00 jalx 65536 # MICRO-NEXT: 20010: f0 00 80 00 jalx 131072 <__start>
# MICRO-NEXT: 20014: 00 00 00 00 nop # MICRO-NEXT: 20014: 00 00 00 00 nop
# MICRO-NEXT: 20018: f0 00 80 0c jalx 65560 # MICRO-NEXT: 20018: f0 00 80 0c jalx 131120 <__LA25Thunk_bar>
# MICRO: __microLA25Thunk_foo: # MICRO: __microLA25Thunk_foo:
# MICRO-NEXT: 20020: 41 b9 00 02 lui $25, 2 # MICRO-NEXT: 20020: 41 b9 00 02 lui $25, 2
# MICRO-NEXT: 20024: d4 01 00 20 j 131136 # MICRO-NEXT: 20024: d4 01 00 20 j 131136
.text .text
.set nomicromips .set nomicromips
.global __start .global __start
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llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

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// DecodeJumpTargetMM - Decode microMIPS jump target, which is // DecodeJumpTargetMM - Decode microMIPS jump target, which is
// shifted left by 1 bit. // shifted left by 1 bit.
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
// which is shifted left by 2 bit.
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMem(MCInst &Inst, static DecodeStatus DecodeMem(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMemEVA(MCInst &Inst, static DecodeStatus DecodeMemEVA(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
▲ Show 20 Lines • Show All 2,008 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
Inst.addOperand(MCOperand::createImm(JumpOffset)); Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (Value == 0) if (Value == 0)
Inst.addOperand(MCOperand::createImm(1)); Inst.addOperand(MCOperand::createImm(1));
else if (Value == 0x7) else if (Value == 0x7)
Inst.addOperand(MCOperand::createImm(-1)); Inst.addOperand(MCOperand::createImm(-1));
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llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 949 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips" in {
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5, def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>, immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
immZExt5, immZExt5Plus1>, immZExt5, immZExt5Plus1>,
EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6; EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Jump Instructions /// Jump Instructions
let DecoderMethod = "DecodeJumpTargetMM" in let DecoderMethod = "DecodeJumpTargetMM" in {
def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">, def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>, J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6; IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
let DecoderMethod = "DecodeJumpTargetMM" in {
def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>, def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
}
let DecoderMethod = "DecodeJumpTargetXMM" in
def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>, def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
}
def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>, def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>, def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
/// Jump Instructions - Short Delay Slot /// Jump Instructions - Short Delay Slot
def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>, def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>,
ISA_MICROMIPS32_NOT_MIPS32R6; ISA_MICROMIPS32_NOT_MIPS32R6;
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llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

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0x26 0x01 0x3c 0x2b # CHECK: seb $9, $6 0x26 0x01 0x3c 0x2b # CHECK: seb $9, $6
0x26 0x01 0x3c 0x3b # CHECK: seh $9, $6 0x26 0x01 0x3c 0x3b # CHECK: seh $9, $6
0x26 0x01 0x3c 0x7b # CHECK: wsbh $9, $6 0x26 0x01 0x3c 0x7b # CHECK: wsbh $9, $6
0x26 0x01 0xec 0x30 # CHECK: ext $9, $6, 3, 7 0x26 0x01 0xec 0x30 # CHECK: ext $9, $6, 3, 7
0x26 0x01 0xcc 0x48 # CHECK: ins $9, $6, 3, 7 0x26 0x01 0xcc 0x48 # CHECK: ins $9, $6, 3, 7
0x00 0xd4 0x98 0x02 # CHECK: j 1328 0x00 0xd4 0x98 0x02 # CHECK: j 1328
0x00 0xf4 0x98 0x02 # CHECK: jal 1328 0x00 0xf4 0x98 0x02 # CHECK: jal 1328
0xe6 0x03 0x3c 0x0f # CHECK: jalr $ra, $6 0xe6 0x03 0x3c 0x0f # CHECK: jalr $ra, $6
0x10 0xf0 0x34 0x00 # CHECK: jalx 4194512
0x07 0x00 0x3c 0x0f # CHECK: jr $7 0x07 0x00 0x3c 0x0f # CHECK: jr $7
0xc9 0x94 0x9a 0x02 # CHECK: beq $9, $6, 1336 0xc9 0x94 0x9a 0x02 # CHECK: beq $9, $6, 1336
0x46 0x40 0x9a 0x02 # CHECK: bgez $6, 1336 0x46 0x40 0x9a 0x02 # CHECK: bgez $6, 1336
0x66 0x40 0x9a 0x02 # CHECK: bgezal $6, 1336 0x66 0x40 0x9a 0x02 # CHECK: bgezal $6, 1336
0x26 0x40 0x9a 0x02 # CHECK: bltzal $6, 1336 0x26 0x40 0x9a 0x02 # CHECK: bltzal $6, 1336
0xc6 0x40 0x9a 0x02 # CHECK: bgtz $6, 1336 0xc6 0x40 0x9a 0x02 # CHECK: bgtz $6, 1336
0x86 0x40 0x9a 0x02 # CHECK: blez $6, 1336 0x86 0x40 0x9a 0x02 # CHECK: blez $6, 1336
0xc9 0xb4 0x9a 0x02 # CHECK: bne $9, $6, 1336 0xc9 0xb4 0x9a 0x02 # CHECK: bne $9, $6, 1336
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llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

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0x01 0x26 0x2b 0x3c # CHECK: seb $9, $6 0x01 0x26 0x2b 0x3c # CHECK: seb $9, $6
0x01 0x26 0x3b 0x3c # CHECK: seh $9, $6 0x01 0x26 0x3b 0x3c # CHECK: seh $9, $6
0x01 0x26 0x7b 0x3c # CHECK: wsbh $9, $6 0x01 0x26 0x7b 0x3c # CHECK: wsbh $9, $6
0x01 0x26 0x30 0xec # CHECK: ext $9, $6, 3, 7 0x01 0x26 0x30 0xec # CHECK: ext $9, $6, 3, 7
0x01 0x26 0x48 0xcc # CHECK: ins $9, $6, 3, 7 0x01 0x26 0x48 0xcc # CHECK: ins $9, $6, 3, 7
0xd4 0x00 0x02 0x98 # CHECK: j 1328 0xd4 0x00 0x02 0x98 # CHECK: j 1328
0xf4 0x00 0x02 0x98 # CHECK: jal 1328 0xf4 0x00 0x02 0x98 # CHECK: jal 1328
0x03 0xe6 0x0f 0x3c # CHECK: jalr $ra, $6 0x03 0xe6 0x0f 0x3c # CHECK: jalr $ra, $6
0xf0 0x10 0x00 0x34 # CHECK: jalx 4194512
0x00 0x07 0x0f 0x3c # CHECK: jr $7 0x00 0x07 0x0f 0x3c # CHECK: jr $7
0x94 0xc9 0x02 0x9a # CHECK: beq $9, $6, 1336 0x94 0xc9 0x02 0x9a # CHECK: beq $9, $6, 1336
0x40 0x46 0x02 0x9a # CHECK: bgez $6, 1336 0x40 0x46 0x02 0x9a # CHECK: bgez $6, 1336
0x40 0x66 0x02 0x9a # CHECK: bgezal $6, 1336 0x40 0x66 0x02 0x9a # CHECK: bgezal $6, 1336
0x40 0x26 0x02 0x9a # CHECK: bltzal $6, 1336 0x40 0x26 0x02 0x9a # CHECK: bltzal $6, 1336
0x40 0xc6 0x02 0x9a # CHECK: bgtz $6, 1336 0x40 0xc6 0x02 0x9a # CHECK: bgtz $6, 1336
0x40 0x86 0x02 0x9a # CHECK: blez $6, 1336 0x40 0x86 0x02 0x9a # CHECK: blez $6, 1336
0xb4 0xc9 0x02 0x9a # CHECK: bne $9, $6, 1336 0xb4 0xc9 0x02 0x9a # CHECK: bne $9, $6, 1336
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